Chip Power On/Off Sequence

Power-up/down sequence

No limitation for core VDD power-up/down sequence: VDD can be powered on/off first or last.

Power-up

First power up 1.8 V by external 1.8 V system power through PVDD18RGM; after at least 20us, power up 3.3 V through PVDD3RGM.

Power-down

First power down 3.3V through PVDD3RGM; after at least 20us, power down 1.8V system power through PVDD18RGM.

Figure 1. Chip Power on/off Sequence