DDR

• DDR controller
• Support 2 channel of x32
• DDR4/3 and LPDDR4/3 modes & signaling, rates up to following speed:
  • 2133Mbps (DDR3/LPDDR3)
  • 3200 Mbps (DDR4/LPDDR4)
• Internal de-skew PLLs for high speed, low jitter clock generation (clk4x)
• x16/x32 data path interface extendable
• DRAM ranks of 1, 2 (could be asymmetric)
• Bank-interleaving & rank-interleaving (symmetric ranks only)
• Support for dynamic DRAM frequency scaling
• Automated clock gating of internal logics
• Error-correction code (SECDED) to select DRAM memory space
• Address region-based security control support
• Automated low power control of DRAM devices
• AMBA AXI4 protocol for main data path interface for DDR controller
• AMBA APB4 protocol for configuration register access interface for DDR controller
• Flexible refresh control
  • Automated adjustment of refresh interval
  • Pulled-in or postponed of refreshes
  • Dynamic per-bank / all-bank refresh switching
  • Opportunistic advanced per-bank refresh
• Open page based advanced page policy
  • Programmable timeout pre-charge
  • Auto pre-charge for reducing command congestion
• Independent read and write timing adjustments with auto calibration
• Various power-down modes for low power including self-refresh support
• DFI 4.0 specification between DDR controller and DDR PHY
• DDR PHY
• High resolution write/read timing control
• Per-bit de-skew on the write data path
• Per-bit de-skew on the read data path
• Support for multiple leveling/training modes through PHY evaluation mode
• Register programming interface to all PHY parameters
• PHY independent mode training logic
• Write/read data timing per-chip select
• Low-power modes
• Low-speed test interface (PHY BIST)
• At-speed ATPG support (OPCG)
• DBI support
• PHY controller frequency ratio of 2:1
• IO calibration
• JTAG interface
• Boundary scan support
• Testability features