Camera MIPI IN/OUT Interface

  • CSI-2 RX Controller
    • Support of the MIPI CSI-2 v1.3 protocol over DPHY PPI interface up to maximum 4 × 1.5 Gbps
    • Pixel interface supporting
    • Byte to pixel conversion one-pixel interface
    • Direct memory dump using packed byte operation
    • Flow control
    • Payload FIFO operation
    • Monitoring of frame for automatic start/end of frame synchronization when enable
    • Extended Functions for Virtual Channel extension and RAW16/20 modes as defined for MIPI CSI-2 V2.0 Specification
    • Enable by setting v2p0_support_enable bit in the static_cfg configuration register
    • RAW16/RAW20 become valid data types
    • VCX (Virtual Channel Extension) will be employed - Effects ECC handing
  • MIPI RX DPHY
    • Support standard 8b PPI interface compliant of MIPI DPHY spec
    • Support total up to 6 lanes in DPHY and data rate up to 1.5Gbps
    • Support 1 clock Lane and up to 4 Data Lane scalability in DPHY mode
    • Support independent (1 Clock Lane and up to 2 Data lanes) x2 in DPHY mode
    • Support lane swap in MIPI DPHY configuration for convenient package and PCB board routing
    • Support clock and data lane swapping function
    • Support Triggers, ULPS and LPDT
  • CSI-2 TX Controller
    • CSI-2 Protocol handling
    • CSI-2 interface up to a maximum of four 2.5Gbps data lanes
    • High Speed data transmission
    • Automatic LP control for clock and data lane power saving
    • Automatic synchronization short packets generation (frame start, frame end, line start, line end)
    • Automatic frame counting when enabled
    • Automatic line counting when enabled
    • Pixel byte-to-packet conversion
    • Virtual Channel/Data type interleaving
    • Protocol error detection
    • Interrupt generation
    • Bypass mode
    • Share MIPI TX DPHY with DSI controller