DDR Interface and Timing

DDR4/DDR3

READ Burst Operation RL=11(AL=0, CL=11, BL8)

Figure 1. DDR Read Burst Operation

WRITE Burst Operation WL=9(AL=0, CWL=9, BL8)

Figure 2. DDR Write Burst Operation

LPDDR4

Burst Read

Figure 3. LPDDR4 Burst Read

Burst Write

Figure 4. LPDDR4 Burst Write

LPDDR3

Burst Read: RL=12, BL=8, tDQSCK > tCK

Figure 5. LPDDR3 Burst Read

Burst Write

Figure 6. LPDDR3 Burst Write