MIPI Display Interface

  • MIPI TX DPHY
  • Support standard 8-bit/16-bit PPI interface compliant to MIPI D-PHY spec
  • Support 1 Clock Lane and up to 4 Data Lanes scalability
  • Support MIPI D-PHY HS-Tx data rate from 80Mbps up to 2.5Gbps. (< 0.1ppm/step)
  • Support MIPI D-PHY LP-Tx data rate of 10Mbps
  • Support Triggers, ULPS and LPDT
  • Support MIPI DSI and MIPI CSI applications.
  • Integrates switchable on-die termination
  • Support clock and data lane swapping function
  • Support reverse direction ULPS and LPDT