SiFive U74 Dual Core

  • Fully-compliant with the RISC-V ISA specification
  • Dual-core with Cache coherence
  • RV64GFC U74 Application Core, each core has
    • 32KB L1 I-cache with ECC (8-way)
    • 32KB L1 D-cache with ECC (8-way)
    • 8 Region Physical Memory Protection
    • Embedded MMU support Linux OS
    • Sv39 Virtual Memory support with 38 Physical Address bits
    • PMP with 8 regions and a minimum granularity of 4096 bytes.
  • CLINT for timer and software interrupts
  • PLIC with support for up to 127 interrupts with 7 priority levels
  • Support SCIE (SiFive Customer Inst Extension)
  • Support JTAG as Debug port
  • Support Multiple AXI Interface including system, peripheral, memory port and front port