VP6

• Highly efficient 32-bit base architecture
• Extend with designer-defined, application-specific instructions, execution units, register files, and I/Os
• 7-stage pipeline depth for core instruction set architecture (ISA)
• Histogram operations
• Up to 32 interrupts
• Local memories configurable up to 256KB ITCM and 256KB DTCM
• 32KB instruction Cache
• Up to 128b-wide flexible-length instruction extensions (FLIX) instructions
• Multi-core on-chip debug (OCD) with break-in/break-out
• Dual-load/stores each up to wide with data cache support and multi-bank RAM support
• Compatible interfaces for ARM® CoreSight™ debug and trace technology
• IEEE 754-compliant single-/double-precision scalar floating-point unit
• 1 AXI Master port and 1 AXI Slave port
• single-channel integrated DMA engine
• Complete matching software development tool chain
• Support generic RTOS Compatibility