Board Level Configuration
The board level device tree file (DTSI file) stores all differentiation information for each board-level device. (For example, common.dtsi, pinctrl.dtsi, and evb.dts, etc. )
The common.dtsi file is stored in the following path:
freelight-u-sdk/linux/arch/riscv/boot/dts/starfive/jh7110-common.dtsiIn the file, spi0 has the following settings.
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&ssp0_pins>;
status = "disabled";
spi_dev0: spi@0 {
compatible = "rohm,dh2228fv";
pl022,com-mode = <1>;
spi-max-frequency = <10000000>;
reg = <0>;
status = "okay";
};
};The following list provides more descriptions for the configuration bits.
- spi-max-frequency: Edit this bit to configure the communication clock frequency of SPI.
- status: Edit this bit to define whether this module is enabled.
VisionFive 2 Board Level Configuration
The pinctrl.dtsi file contains the pin control configuration. The file is stored in
the following
path:
freelight-u-sdk/linux/arch/riscv/boot/dts/starfive/jh7110-visionfive-v2.dtsThe following code block provides an example of the pins used by spi0 including
tx (Transceiver), rx (Receiver),
clk (clock), and cs (chip select)
signals.
ssp0_pins: ssp0-pins {
ssp0-pins_tx {
sf,pins = <PAD_GPIO52>;
sf,pinmux = <PAD_GPIO52_FUNC_SEL 0>;
sf,pin-ioconfig = <IO(GPIO_IE(1))>;
sf,pin-gpio-dout = <GPO_SPI0_SSPTXD>;
sf,pin-gpio-doen = <OEN_LOW>;
};
ssp0-pins_rx {
sf,pins = <PAD_GPIO53>;
sf,pinmux = <PAD_GPIO53_FUNC_SEL 0>;
sf,pin-ioconfig = <IO(GPIO_IE(1))>;
sf,pin-gpio-doen = <OEN_HIGH>;
sf,pin-gpio-din = <GPI_SPI0_SSPRXD>;
};
ssp0-pins_clk {
sf,pins = <PAD_GPIO48>;
sf,pinmux = <PAD_GPIO48_FUNC_SEL 0>;
sf,pin-ioconfig = <IO(GPIO_IE(1))>;
sf,pin-gpio-dout = <GPO_SPI0_SSPCLKOUT>;
sf,pin-gpio-doen = <OEN_LOW>;
};
ssp0-pins_cs {
sf,pins = <PAD_GPIO49>;
sf,pinmux = <PAD_GPIO49_FUNC_SEL 0>;
sf,pin-ioconfig = <IO(GPIO_IE(1))>;
sf,pin-gpio-dout = <GPO_SPI0_SSPFSSOUT>;
sf,pin-gpio-doen = <OEN_LOW>;
};
};
