SiFive E24 Core

• Fully-compliant with the RISC-V 32 ISA specification
• RV32IMAFC E24 Core
  • 16KB I-cache with 32 Byte cache line
  • 64KB TIM with two banks and atomic operation
  • 4 Region Physical Memory Protection
• CLIC with support for up to 127 interrupts with 16 priority levels
• Support JTAG as Debug port
• Support AHB-Lite system bus for2GB memory map