CHIPLINK

• An off-chip serialization of the TileLink protocol, used to connect to an optional expansion board
• It is implemented as a source-synchronous single-data rate parallel bus
• Off-chip cache-coherent bus masters (e.g., in an FPGA)
• Off-chip memory-mapped slave devices
• Credit-based flow control to absorb off-chip latency
• Out-of-order completion to unblock concurrent operations
• Devices in the FPGA to connect their interrupts to the PLIC via this ChipLink bus