USB 2.0/3.0

  • USB2.0/3.0 controller
  • USB Interface:
    • Compliant with USB 3.0 Specification
    • Compliant with xHCI 1.0 Specification
    • SuperSpeed, Hi Speed and Full Speed supported
    • Single USB2.0 Port
    • Single USB3.0 Port
    • USB 3.0 PIPE interface compliant
    • USB 2.0 UTMI+ interface compliant
    • USB2 L1/L2 Support
    • USB3 U1/U2/U3 Support
  • Application Interface:
    • AXI3/4 Master Interface with 64-bit data and 32-bit address
    • APB4 Slave interface with 32-bit data and address
  • Dual Mode Operation:
    • HW selectable default mode selection supporting operation without any SW interaction
    • Programmable runtime mode change
    • Host Negotiate Protocol (HNP) support
    • SRP support
    • Separate Power Domains for Host and Peripheral Device logic
  • Host Mode (CDNSXHCI):
    • Configurable total slots supported (maximum of 3264)
    • 32 endpoints per slot
    • 256 Primary Streams supported
    • MSI Support
    • Root Hub functionality implemented
    • xHCI Dynamic and Static Low Power Management Support
    • xHCI DMA engine with 64-bit @ 125MHz Full Duplex Data Path
  • Peripheral Mode (USBSS-DEV):
    • Control transfers supported by Endpoint #0
    • Up to 15 IN and 15 OUT configurable/ programmable endpoints
    • Scatter-gather DMA
    • Dynamic data buffering
  • Integrated Protocol Stack
    • Memory integration
    • Clock, reset and power management integration
  • USB3.0 PHY
  • 5.0-Gbps super-speed data rate through 3m USB3.0 cable
  • Support 25MHz clock inputs
  • Support down-spread Spread Spectrum Clock (SSC) transmission and receiving (0~-5000ppm)
  • PIPE3.0 compliant interface for USB3.0
  • Support 16-bit interface at 250MHz operation and 32-bit interface at 125MHz operation
  • Support super-speed power down modes: U0, U1, U2 and U3
  • Integrated PHY with TX, RX, SSC, PLL, digital core and ESD
  • With adaptive RX equalizer to support different channel conditions
  • Accessible programmable controls allow user specific optimization of critical parameters
  • Integrated PLL to provide a variety of stand-alone clock outputs for USB related applications (25, 30, 48, 60, 120, 125 and 480MHz)
  • Provides robust BIST function for mass production tests
  • Built-in SSTX de-multiplexing and SSRX multiplexing for type-C or dual connectors
  • USB2.0 PHY
  • 480-Mbps high-speed, 12-Mbps full-speed and 1.5-Mbps low-speed data transmission through 5m USB2.0 cable
  • Support USB2.0 normal mode, suspend, resume and remote wakeup
  • Compliant with UTMI+ interface (High-speed, Full-speed, Low-speed and Preamble Packet)
  • Support all USB2.0 test modes
  • Built-in 45Ω termination and 1.5KΩ pull-up resistor
  • SYNC and EOP generation and checking
  • NRZI encoding and decoding
  • Accessible register controls allow user specific optimization of critical parameters