EQOS_DMA Registers

Ethernet GMAC has the following EQOS_DMA registers.

DMA_Mode

  • Description: The Bus Mode register establishes the bus operating modes for the DMA.
  • Size: 32 bits
  • Offset: 0x1000
Table 1. DMA_Mode Register Description
Bits Name Memory Access Description
31:24 Reserved_31_24 R

Reserved.
23:22 RNDF R/W

Rx DMA's Maximum Number of Descriptors to be fetched in a burst

  • 00:DWC_EQOS_DCRX_DEP
  • 01:DWC_EQOS_DCRX_DEP/2
  • 10:DWC_EQOS_DCRX_DEP/4
  • 11: DWC_EQOS_DCRX_DEP/8 (Reserved when DWC_EQOS_DCRX_DEP= 4)
21:20 TNDF R/W

Tx DMA's Maximum Number of Descriptors to be fetched in a burst

  • 00:DWC_EQOS_DCTX_DEP
  • 01:DWC_EQOS_DCTX_DEP/2
  • 10:DWC_EQOS_DCTX_DEP/4
  • 11: DWC_EQOS_DCTX_DEP/8 (Reserved when DWC_EQOS_DCTX_DEP= 4)
19 DCHE R/W

Descriptor Cache Enable When set enables prefetching of descriptors to the Descriptor Cache. When reset descriptor cache feature is disabled.

Values:

  • 0x0(DISABLE): Descriptor Cache Support is disabled
  • 0x1(ENABLE): Descriptor Cache Support is enabled
18 Reserved_18 R

Reserved.
17:16 INTM R/W

Interrupt Mode

This field defines the interrupt mode of DWC_ether_qos.

The behavior of the following outputs change depending on the following settings:

  • sbd_perch_tx_intr_o[] (Transmit Per Channel Interrupt)
  • sbd_perch_rx_intr_o[] (Receive Per Channel Interrupt)
  • sbd_intr_o (Common Interrupt)

It also changes the behavior ofthe RI/TI bits in the DMA_CH0_Status.

  • 00: sbd_perch_* are pulse signals for each TX/RX packet transfer completion events (irrespective of whether corresponding interrupts are enabled) for which IOC bits are enabled in descriptor. sbd_intr_o is also asserted when corresponding interrupts are enabled and cleared only when software clears the corresponding RI/TI status bits.
  • 01: sbd_perch_* are level signals asserted on TX/RX packet transfer completion event when corresponding interrupts are enabled and de-asserted when the software clears the corresponding RI/TI status bits. The sbd_intr_o is not asserted for these TX/RX packet transfer completion events.
  • 10: sbd_perch_* are level signals asserted on TX/RX packet transfer completion event when corresponding interrupts are enabled and de-asserted when the software clears the corresponding RI/TI status bits. However, the signal is asserted again if the same event occurred again before it was cleared. The sbd_intr_o is not asserted for these TX/RX packet transfer completion events.
  • 11: Reserved

Values:

  • 0x0(MODE0): See above description
  • 0x1(MODE1): See above description
  • 0x2(MODE2): See above description
  • 0x3(RSVD): Reserved
15 Reserved_15 R

Reserved.
14:12 PR R/W

Priority Ratio

These bits control the priority ratio in weighted round-robin arbitration between the Rx DMA and Tx DMA. These bits are valid only when the DA bit is reset. The priority ratio is Rx:Tx or Tx:Rx depending on whether the TXPR bit is reset or set.

Values:

  • 0x0(R_1_1): The priority ratio is 1:1
  • 0x1(R_2_1): The priority ratio is 2:1
  • 0x2(R_3_1): The priority ratio is 3:1
  • 0x3(R_4_1): The priority ratio is 4:1
  • 0x4(R_5_1): The priority ratio is 5:1
  • 0x5(R_6_1): The priority ratio is 6:1
  • 0x6(R_7_1): The priority ratio is 7:1
  • 0x7(R_8_1): The priority ratio is 8:1
11 TXPR R/W

Transmit Priority

When set, this bit indicates that the Tx DMA has higher priority than the Rx DMA during arbitration for the system-side bus or Descriptor reads from DCACHE memory when DWC_EQOS_DCEXT is enabled

Values:

  • 0x0(DISABLE): Transmit Priority is disabled
  • 0x1(ENABLE): Transmit Priority is enabled
10 SCSW R/W

SCSW is Synopsys Reserved, This field must be set to "0". This field is reserved for Synopsys Internal use, and must always be set to "0" unless instructed by Synopsys.

Setting this field to "1" might cause unexpected behavior in the IP.

Values:

  • 0x0(DISABLE): Synopsys reserved field disabled
  • 0x1(ENABLE): Synopsys reserved field enabled up on Synopsys request
9 ARBC R/W

ARBC is Synopsys Reserved, This field must be set to "0".

  • This field is reserved for Synopsys Internal use, and must always be set to "0" unless instructed by Synopsys.
  • Setting this field to "1"might cause unexpected behavior in the IP.

Values:

  • 0x0(DISABLE): Synopsys reserved field disabled
  • 0x1(ENABLE): Synopsys reserved field enabled up on Synopsys request
8 DSPW R/W

Descriptor Posted Write When this bit is set to

  • 0: The descriptor writes are always non-posted.
  • 1: The descriptor writes are non-posted only when IOC(Interrupt on completion) is set in last descriptor. Other- wise, the descriptor writes are always posted.

Values:

  • 0x0(DISABLE): Descriptor Posted Write is disabled
  • 0x1(ENABLE): Descriptor Posted Write is enabled
7:5 Reserved_7_5 R

Reserved.
4:2 TAA R/W

Transmit Arbitration Algorithm

This field is used to select the arbitration algorithm for the Transmit side when multiple Tx DMAs are selected.

Values:

  • 0x0(FP): Fixed priority (Channel 0 has the lowest priority and the last channel has the highest priority)
  • 0x1(WSP): Weighted Strict Priority (WSP)
  • 0x2(WRR): Weighted Round-Robin (WRR)
  • 0x3(RSVD): Reserved (for 3'b011 to 3'b111)
1 DA R/W

DMA Tx or Rx Arbitration Scheme

This bit specifies the arbitration scheme between the Transmit and Receive paths of all channels:

  • 0: Weighted Round-Robin with Rx:Tx orTx:Rx

The priority between the paths is according to the priority specified in Bits[14:12] and the priority weight is specified in the TXPR bit.

  • 1: Fixed Priority

The Tx path has priority over the Rx path when the TXPR bit is set. Otherwise, the Rx path has priority over the Tx path.

Values:

  • 0x0(WRR): Weighted Round-Robin with Rx:Tx or Tx:Rx
  • 0x1(FP): Fixed Priority
0 SWR R/W

Software Reset

When this bit is set, the MAC and the DMA controller reset the logic and all internal registers of the DMA, MTL, and MAC. This bit is automatically cleared after the reset operation is complete in all DWC_ether_qos clock domains. Before reprogramming any DWC_ether_qos register, a value of zero should be read in this bit.

This bit must be read at least 4 CSR clock cycles after it is written to 1.

Note:The reset operation is complete only when all resets in all active clock domains are de-asserted. Therefore, it is essential that all PHY inputs clocks (applicable for the selected PHY interface) are present for software reset completion. The time to complete the software reset operation depends on the frequency of the slowest active clock.

Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect.

Values:

  • 0x0(DISABLE): Software Reset is disabled
  • 0x1(ENABLE): Software Reset is enabled

DMA_SysBus_Mode

  • Description: The System Bus mode register controls the behavior of the AHB or AXI master. It mainly controls burst splitting and number of outstanding requests.
  • Size: 32 bits
  • Offset: 0x1004
Table 2. DMA_SysBus_Mode Register Description
Bits Name Memory Access Description
31 EN_LPI R/W

Enable Low Power Interface (LPI) When set to

  • 1: This bit enables the LPI mode supported by the

EQOS-AXI configuration and accepts the LPI request from the AXI System Clock controller.

  • 0: This bit disables the LPI mode. Denies the LPI request from the AXI System Clock controller.

Values:

  • 0x0(DISABLE): Low Power Interface (LPI) is disabled
  • 0x1(ENABLE): Low Power Interface (LPI) is enabled
30 LPI_XIT_PKT R/W

Unlock on Magic Packet or Remote Wake-Up Packet

When set to 1, this bit enables the AXI master to come out of the LPI mode only when the magic packet or remote wake-up packet is received. When set to 0, this bit enables the AXI master to come out of the LPI mode when any packet is received.

Values:

  • 0x0(DISABLE): Unlock on Magic Packet or Remote Wake-Up Packet is disabled
  • 0x1(ENABLE): Unlock on Magic Packet or Remote Wake-Up Packet is enabled
29:y Reserved_29_y R

Reserved.
x:24 WR_OSR_LMT R/W

AXI Maximum Write Outstanding Request Limit

This value limits the maximum outstanding request on the AXI write interface. Maximum outstanding requests = WR_OSR_LMT + 1
23:y Reserved_23_y R

Reserved.
x:16 RD_OSR_LMT R/W

AXI Maximum Read Outstanding Request Limit

This value limits the maximum outstanding request on the AXI read interface. Maximum outstanding requests = RD_OSR_LMT + 1
15 RB R/W

Rebuild INCRx Burst

When this bit is set high and the AHB master gets SPLIT, RETRY, or Early Burst Termination (EBT) response, the AHB master interface rebuilds the pending beats of any initiated burst transfer with INCRx and SINGLE transfers. By default, the AHB master interface rebuilds the pending beats of an EBT with an unspecified (INCR) burst.

Values:

  • 0x0(DISABLE): Rebuild INCRx Burst is disabled
  • 0x1(ENABLE): Rebuild INCRx Burst is enabled
14 MB R/W

Mixed Burst

When this bit is high and the FB bit is low, the AHB master performs undefined bursts transfers (INCR) for burst length of 16 or more. For burst length of 16 or less, the AHB master performs fixed burst transfers (INCRx and SINGLE).

Values:

  • 0x0(DISABLE): Mixed Burst is disabled
  • 0x1(ENABLE): Mixed Burst is enabled
13 ONEKBBE R/W

1KB Boundary Crossing Enable for the EQOS-AXI Master

  • 1: The burst transfers performed by the EQOS-AXI master do not cross 1 KB boundary.
  • 0: The burst transfers performed by the EQOS-AXI master do not cross 4 KB boundary.

Values:

  • 0x0(DISABLE): 1 KB Boundary Crossing for the EQOS-AXI Master Beats is disabled
  • 0x1(ENABLE): 1 KB Boundary Crossing for the EQOS-AXI Master Beats is enabled
12 AAL R/W

Address-Aligned Beats

When this bit is set to 1, the EQOS-AXI or EQOS-AHB master performs address-aligned burst transfers on Read and Write channels.

When this bit is set to 0, the EQOS-AXI or EQOS-AHB master performs burst transfers on Read and Write channels without aligning to address boundaries.

Values:

  • 0x0(DISABLE): Address-Aligned Beats is disabled
  • 0x1(ENABLE): Address-Aligned Beats is enabled
11 EAME R/W

Enhanced Address Mode Enable. When set to

  • 1: the DMA master enables the enhanced address mode (40-bit or 48-bit addressing mode). In this mode, the DMA engine uses either the 40- or 48-bit address, depending on the configuration.
  • 0: the DMA master enables the normal address mode (32-bit).

Values:

  • 0x0(DISABLE): Enhanced Address Mode is disabled
  • 0x1(ENABLE): Enhanced Address Mode is enabled
10 AALE R/W

Automatic AXI LPI enable

When set to 1, enables the AXI master to enter into LPI state when there is no activity in the DWC_ether_qos for number of system clock cycles programmed in the LPIEI field of AXI_LPI_Entry_Interval register.

Values:

  • 0x0(DISABLE): Automatic AXI LPI is disabled
  • 0x1(ENABLE): Automatic AXI LPI is enabled
9:8 Reserved_9_8 R

Reserved.
7 BLEN256 R/W

AXI Burst Length 256 When set to

  • 1: the EQOS-AXI master can select a burst length of 256 on the AXI interface.
  • 0: the EQOS-AXI master cannot select a burst length of greater than 128 on the AXI interface.

Values:

  • 0x0(DISABLE): No effect
  • 0x1(ENABLE): AXI Burst Length 256
6 BLEN128 R/W

AXI Burst Length 128 When set to

  • 1: the EQOS-AXI master can select a burst length of 128 on the AXI interface.
  • 0: the EQOS-AXI master cannot select a burst length of greater than 64 on the AXI interface.

Values:

  • 0x0(DISABLE): No effect
  • 0x1(ENABLE): AXI Burst Length 128
5 BLEN64 R/W

AXI Burst Length 64When set to

  • 1: the EQOS-AXI master can select a burst length of 64 on the AXI interface.
  • 0: the EQOS-AXI master cannot select a burst length of greater than 32 on the AXI interface.

Values:

  • 0x0(DISABLE): No effect
  • 0x1(ENABLE): AXI Burst Length 64
4 BLEN32 R/W

AXI Burst Length 32When set to

  • 1: the EQOS-AXI master can select a burst length of 32 on the AXI interface.
  • 0: the EQOS-AXI master cannot select a burst length of greater than 16 on the AXI interface.

Values:

  • 0x0(DISABLE): No effect
  • 0x1(ENABLE): AXI Burst Length 32
3 BLEN16 R/W

AXI Burst Length 16

When this bit is set to 1 or the FB bit is set to 1, the EQOS-AXI master can select a burst length of 16 on the AXI interface.

When the FB bit is set to 0, setting this bit has no effect.

Values:

  • 0x0(DISABLE): No effect
  • 0x1(ENABLE): AXI Burst Length 16
2 BLEN8 R/W

AXI Burst Length 8

When this bit is set to 1 or the FB bit is set to 1, the EQOS-AXI master can select a burst length of 8 on the AXI interface.

When the FB bit is set to 0, setting this bit has no effect.

Values:

  • 0x0(DISABLE): No effect
  • 0x1(ENABLE): AXI Burst Length 8
1 BLEN4 R/W

AXI Burst Length 4

When this bit is set to 1 or the FB bit is set to 1, the EQOS-AXI master can select a burst length of 4 on the AXI interface.

When the FB bit is set to 0, setting this bit has no effect.

Values:

  • 0x0(DISABLE): No effect
  • 0x1(ENABLE): AXI Burst Length 4
0 FB R/W

Fixed Burst Length

ForEQOS-AXI Configurations:

  • 1: the EQOS-AXI master initiates burst transfers of specified lengths:
    • Burst transfers of fixed burst lengths as indicated by the BLEN256, BLEN128, BLEN64, BLEN32, BLEN16, BLEN8, or BLEN4 field
    • Burst transfers of length 1
  • 0: EQOS-AXI master initiates burst transfers that are equal to or less than the maximum allowed burst length programmed in Bits[4:7].

ForEQOS-AHB Configurations:\

  • 1: AHB master initiates burst transfers of specified length (INCRx or SINGLE).
  • 0: AHB master initiates transfers of unspecified length (INCR) or SINGLE transfers.

ForEQOS-DMAConfigurations:

The value of this bit is driven on the mdc_burst_count_o output signal.

Values:

  • 0x0(DISABLE): Fixed Burst Length is disabled
  • 0x1(ENABLE): Fixed Burst Length is enabled

DMA_Interrupt_Status

  • Description: The application reads this Interrupt Status register during interrupt service routine or polling to determine the interrupt status of DMA channels, MTL queues, and the MAC.
  • Size: 32 bits
  • Offset: 0x1008
Table 3. DMA_Interrupt_Status Register Description
Bits Name Memory Access Description
31:18 Reserved_31_18 R

Reserved.
17 MACIS R

MAC Interrupt Status

This bit indicates an interrupt event in the MAC. To reset this bit to 1'b0, the software must read the corresponding register in the MAC to get the exact cause of the interrupt and clear its source.

Values:

  • 0x0(INACTIVE): MAC Interrupt Status not detected
  • 0x1(ACTIVE): MAC Interrupt Status detected
16 MTLIS R

MTL Interrupt Status

This bit indicates an interrupt event in the MTL. To reset this bit to 1'b0, the software must read the corresponding register in the MTL to get the exact cause of the interrupt and clear its source.

Values:

  • 0x0(INACTIVE): MTL Interrupt Status not detected
  • 0x1(ACTIVE): MTL Interrupt Status detected
15:8 Reserved_15_8 R

Reserved.
7 DC7IS R

DMA Channel 7 Interrupt Status

This bit indicates an interrupt event in DMA Channel 7. To reset this bit to 1'b0, the software must read the corresponding register in DMA Channel 7 to get the exact cause of the interrupt and clear its source.

Values:

  • 0x0(INACTIVE): DMA Channel 7 Interrupt Status not detected
  • 0x1(ACTIVE): DMA Channel 7 Interrupt Status detected
6 DC6IS R

DMA Channel 6 Interrupt Status

This bit indicates an interrupt event in DMA Channel 6. To reset this bit to 1'b0, the software must read the corresponding register in DMA Channel 6 to get the exact cause of the interrupt and clear its source.

Values:

  • 0x0(INACTIVE): DMA Channel 6 Interrupt Status not detected
  • 0x1(ACTIVE): DMA Channel 6 Interrupt Status detected
5 DC5IS R

DMA Channel 5 Interrupt Status

This bit indicates an interrupt event in DMA Channel 5. To reset this bit to 1'b0, the software must read the corresponding register in DMA Channel 5 to get the exact cause of the interrupt and clear its source.

Values:

  • 0x0(INACTIVE): DMA Channel 5 Interrupt Status not detected
  • 0x1(ACTIVE): DMA Channel 5 Interrupt Status detected
4 DC4IS R

DMA Channel 4 Interrupt Status

This bit indicates an interrupt event in DMA Channel 4. To reset this bit to 1'b0, the software must read the corresponding register in DMA Channel 4 to get the exact cause of the interrupt and clear its source.

Values:

  • 0x0(INACTIVE): DMA Channel 4 Interrupt Status not detected
  • 0x1(ACTIVE): DMA Channel 4 Interrupt Status detected
3 DC3IS R

DMA Channel 3 Interrupt Status

This bit indicates an interrupt event in DMA Channel 3. To reset this bit to 1'b0, the software must read the corresponding register in DMA Channel 3 to get the exact cause of the interrupt and clear its source.

Values:

  • 0x0(INACTIVE): DMA Channel 3 Interrupt Status not detected
  • 0x1(ACTIVE): DMA Channel 3 Interrupt Status detected
2 DC2IS R

DMA Channel 2 Interrupt Status

This bit indicates an interrupt event in DMA Channel 2. To reset this bit to 1'b0, the software must read the corresponding register in DMA Channel 2 to get the exact cause of the interrupt and clear its source.

Values:

  • 0x0(INACTIVE): DMA Channel 2 Interrupt Status not detected
  • 0x1(ACTIVE): DMA Channel 2 Interrupt Status detected
1 DC1IS R

DMA Channel 1 Interrupt Status

This bit indicates an interrupt event in DMA Channel 1. To reset this bit to 1'b0, the software must read the corresponding register in DMA Channel 1 to get the exact cause of the interrupt and clear its source.

Values:

  • 0x0(INACTIVE): DMA Channel 1 Interrupt Status not detected
  • 0x1(ACTIVE): DMA Channel 1 Interrupt Status detected
0 DC0IS R

DMA Channel 0 Interrupt Status

This bit indicates an interrupt event in DMA Channel 0. To reset this bit to 1'b0, the software must read the corresponding register in DMA Channel 0 to get the exact cause of the interrupt and clear its source.

Values:

  • 0x0(INACTIVE): DMA Channel 0 Interrupt Status not detected
  • 0x1(ACTIVE): DMA Channel 0 Interrupt Status detected

DMA_Debug_Status0

  • Description: The Debug Status 0 register gives the Receive and Transmit process status for DMA Channel 0-Channel 2 for debugging purpose.
  • Size: 32 bits
  • Offset: 0x100c
Table 4. DMA_Debug_Status0 Register Description
Bits Name Memory Access Description
31:28 TPS2 R

DMA Channel 2 Transmit Process State

This field indicates the Tx DMA FSM state for Channel 2. The MSB of this field always returns 0. This field does not generate an interrupt.

Values:

  • 0x0(STOP): Stopped (Reset or Stop Transmit Command issued)
  • 0x1(RUN_FTTD): Running (Fetching Tx Transfer Descriptor)
  • 0x2(RUN_WS): Running (Waiting for status)
  • 0x3(RUN_RDS): Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))
  • 0x4(TSTMP_WS): Timestamp write state
  • 0x5(RSVD): Reserved for future use
  • 0x6(SUSPND): Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)
  • 0x7(RUN_CTD): Running (Closing Tx Descriptor)
27:24 RPS2 R

DMA Channel 2 Receive Process State

This field indicates the Rx DMA FSM state for Channel 2. The MSB of this field always returns 0. This field does not generate an interrupt.

Values:

  • 0x0(STOP): Stopped (Reset or Stop Receive Command issued)
  • 0x1(RUN_FRTD): Running (Fetching Rx Transfer Descriptor)
  • 0x2(RSVD): Reserved for future use
  • 0x3(RUN_WRP): Running (Waiting for Rx packet)
  • 0x4(SUSPND): Suspended (Rx Descriptor Unavailable)
  • 0x5(RUN_CRD): Running (Closing the Rx Descriptor)
  • 0x6(TSTMP): Timestamp write state
  • 0x7(RUN_TRP): Running (Transferring the received packet data from the Rx buffer to the system memory)
23:20 TPS1 R

DMA Channel 1 Transmit Process State

This field indicates the Tx DMA FSM state for Channel 1. The MSB of this field always returns 0. This field does not generate an interrupt.

Values:

  • 0x0(STOP): Stopped (Reset or Stop Transmit Command issued)
  • 0x1(RUN_FTTD): Running (Fetching Tx Transfer Descriptor)
  • 0x2(RUN_WS): Running (Waiting for status)
  • 0x3(RUN_RDS): Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))
  • 0x4(TSTMP_WS): Timestamp write state
  • 0x5(RSVD): Reserved for future use
  • 0x6(SUSPND): Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)
  • 0x7(RUN_CTD): Running (Closing Tx Descriptor)
19:16 RPS1 R

DMA Channel 1 Receive Process State

This field indicates the Rx DMA FSM state for Channel 1. The MSB of this field always returns 0. This field does not generate an interrupt.

Values:

  • 0x0(STOP): Stopped (Reset or Stop Receive Command issued)
  • 0x1(RUN_FRTD): Running (Fetching Rx Transfer Descriptor)
  • 0x2(RSVD): Reserved for future use
  • 0x3(RUN_WRP): Running (Waiting for Rx packet)
  • 0x4(SUSPND): Suspended (Rx Descriptor Unavailable)
  • 0x5(RUN_CRD): Running (Closing the Rx Descriptor)
  • 0x6(TSTMP): Timestamp write state
  • 0x7(RUN_TRP): Running (Transferring the received packet data from the Rx buffer to the system memory)
15:12 TPS0 R

DMA Channel 0 Transmit Process State

This field indicates the Tx DMA FSM state for Channel 0. The MSB of this field always returns 0. This field does not generate an interrupt.

Values:

  • 0x0(STOP): Stopped (Reset or Stop Transmit Command issued)
  • 0x1(RUN_FTTD): Running (Fetching Tx Transfer Descriptor)
  • 0x2(RUN_WS): Running (Waiting for status)
  • 0x3(RUN_RDS): Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))
  • 0x4(TSTMP_WS): Timestamp write state
  • 0x5(RSVD): Reserved for future use
  • 0x6(SUSPND): Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)
  • 0x7(RUN_CTD): Running (Closing Tx Descriptor)
11:8 RPS0 R

DMA Channel 0 Receive Process State

This field indicates the Rx DMA FSM state for Channel 0. The MSB of this field always returns 0. This field does not generate an interrupt.

Values:

  • 0x0(STOP): Stopped (Reset or Stop Receive Command issued)
  • 0x1(RUN_FRTD): Running (Fetching Rx Transfer Descriptor)
  • 0x2(RSVD): Reserved for future use
  • 0x3(RUN_WRP): Running (Waiting for Rx packet)
  • 0x4(SUSPND): Suspended (Rx Descriptor Unavailable)
  • 0x5(RUN_CRD): Running (Closing the Rx Descriptor)
  • 0x6(TSTMP): Timestamp write state
  • 0x7(RUN_TRP): Running (Transferring the received packet data from the Rx buffer to the system memory)
7:2 Reserved_7_2 R

Reserved.
1 AXRHSTS R

AXI Master Read Channel Status

When high, this bit indicates that the read channel of the AXI master is active, and it is transferring the data.

Values:

  • 0x0(INACTIVE): AXI Master Read Channel Status not detected
  • 0x1(ACTIVE): AXI Master Read Channel Status detected
0 AXWHSTS R

AXI Master Write Channel or AHB Master Status EQOS-AXI Configuration:

When high, this bit indicates that the write channel of the AXI master is active, and it is transferring data.

EQOS-AHB Configuration:

When high, this bit indicates that the AHB master FSMs are in the non-idle state.

Values:

  • 0x0(INACTIVE): AXI Master Write Channel or AHB Master Status not detected
  • 0x1(ACTIVE): AXI Master Write Channel or AHB Master Status detected

DMA_Debug_Status1

  • Description: The Debug Status1 register gives the Receive and Transmit process status for DMA Channel 3-Channel 6.
  • Size: 32 bits
  • Offset: 0x1010
Table 5. DMA_Debug_Status1 Register Description
Bits Name Memory Access Description
31:28 TPS6 R

DMA Channel 6 Transmit Process State

This field indicates the Tx DMA FSM state for Channel 6. The MSB of this field always returns 0. This field does not generate an interrupt.

Values:

  • 0x0(STOP): Stopped (Reset or Stop Transmit Command issued)
  • 0x1(RUN_FTTD): Running (Fetching Tx Transfer Descriptor)
  • 0x2(RUN_WS): Running (Waiting for status)
  • 0x3(RUN_RDS): Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))
  • 0x4(TSTMP_WS): Timestamp write state
  • 0x5(RSVD): Reserved for future use
  • 0x6(SUSPND): Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)
  • 0x7(RUN_CTD): Running (Closing Tx Descriptor)
27:24 RPS6 R

DMA Channel 6 Receive Process State

This field indicates the Rx DMA FSM state for Channel 6. The MSB of this field always returns 0. This field does not generate an interrupt.

Values:

  • 0x0(STOP): Stopped (Reset or Stop Receive Command issued)
  • 0x1(RUN_FRTD): Running (Fetching Rx Transfer Descriptor)
  • 0x2(RSVD): Reserved for future use
  • 0x3(RUN_WRP): Running (Waiting for Rx packet)
  • 0x4(SUSPND): Suspended (Rx Descriptor Unavailable)
  • 0x5(RUN_CRD): Running (Closing the Rx Descriptor)
  • 0x6(TSTMP): Timestamp write state
  • 0x7(RUN_TRP): Running (Transferring the received packet data from the Rx buffer to the system memory)
23:20 TPS5 R

DMA Channel 5 Transmit Process State

This field indicates the Tx DMA FSM state for Channel 5. The MSB of this field always returns 0. This field does not generate an interrupt.

Values:

  • 0x0(STOP): Stopped (Reset or Stop Transmit Command issued)
  • 0x1(RUN_FTTD): Running (Fetching Tx Transfer Descriptor)
  • 0x2(RUN_WS): Running (Waiting for status)
  • 0x3(RUN_RDS): Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))
  • 0x4(TSTMP_WS): Timestamp write state
  • 0x5(RSVD): Reserved for future use
  • 0x6(SUSPND): Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)
  • 0x7(RUN_CTD): Running (Closing Tx Descriptor)
19:16 RPS5 R

DMA Channel 5 Receive Process State

This field indicates the Rx DMA FSM state for Channel 5. The MSB of this field always returns 0. This field does not generate an interrupt.

Values:

  • 0x0(STOP): Stopped (Reset or Stop Receive Command issued)
  • 0x1(RUN_FRTD): Running (Fetching Rx Transfer Descriptor)
  • 0x2(RSVD): Reserved for future use
  • 0x3(RUN_WRP): Running (Waiting for Rx packet)
  • 0x4(SUSPND): Suspended (Rx Descriptor Unavailable)
  • 0x5(RUN_CRD): Running (Closing the Rx Descriptor)
  • 0x6(TSTMP): Timestamp write state
  • 0x7(RUN_TRP): Running (Transferring the received packet data from the Rx buffer to the system memory)
15:12 TPS4 R

DMA Channel 4 Transmit Process State

This field indicates the Tx DMA FSM state for Channel 4. The MSB of this field always returns 0. This field does not generate an interrupt.

Values:

  • 0x0(STOP): Stopped (Reset or Stop Transmit Command issued)
  • 0x1(RUN_FTTD): Running (Fetching Tx Transfer Descriptor)
  • 0x2(RUN_WS): Running (Waiting for status)
  • 0x3(RUN_RDS): Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))
  • 0x4(TSTMP_WS): Timestamp write state
  • 0x5(RSVD): Reserved for future use
  • 0x6(SUSPND): Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)
  • 0x7(RUN_CTD): Running (Closing Tx Descriptor)
11:8 RPS4 R

DMA Channel 4 Receive Process State

This field indicates the Rx DMA FSM state for Channel 4. The MSB of this field always returns 0. This field does not generate an interrupt.

Values:

  • 0x0(STOP): Stopped (Reset or Stop Receive Command issued)
  • 0x1(RUN_FRTD): Running (Fetching Rx Transfer Descriptor)
  • 0x2(RSVD): Reserved for future use
  • 0x3(RUN_WRP): Running (Waiting for Rx packet)
  • 0x4(SUSPND): Suspended (Rx Descriptor Unavailable)
  • 0x5(RUN_CRD): Running (Closing the Rx Descriptor)
  • 0x6(TSTMP): Timestamp write state
  • 0x7(RUN_TRP): Running (Transferring the received packet data from the Rx buffer to the system memory)
7:4 TPS3 R

DMA Channel 3 Transmit Process State

This field indicates the Tx DMA FSM state for Channel 3. The MSB of this field always returns 0. This field does not generate an interrupt.

Values:

  • 0x0(STOP): Stopped (Reset or Stop Transmit Command issued)
  • 0x1(RUN_FTTD): Running (Fetching Tx Transfer Descriptor)
  • 0x2(RUN_WS): Running (Waiting for status)
  • 0x3(RUN_RDS): Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))
  • 0x4(TSTMP_WS): Timestamp write state
  • 0x5(RSVD): Reserved for future use
  • 0x6(SUSPND): Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)
  • 0x7(RUN_CTD): Running (Closing Tx Descriptor)
3:0 RPS3 R

DMA Channel 3 Receive Process State

This field indicates the Rx DMA FSM state for Channel 3. The MSB of this field always returns 0. This field does not generate an interrupt.

Values:

  • 0x0(STOP): Stopped (Reset or Stop Receive Command issued)
  • 0x1(RUN_FRTD): Running (Fetching Rx Transfer Descriptor)
  • 0x2(RSVD): Reserved for future use
  • 0x3(RUN_WRP): Running (Waiting for Rx packet)
  • 0x4(SUSPND): Suspended (Rx Descriptor Unavailable)
  • 0x5(RUN_CRD): Running (Closing the Rx Descriptor)
  • 0x6(TSTMP): Timestamp write state
  • 0x7(RUN_TRP): Running (Transferring the received packet data from the Rx buffer to the system memory)

DMA_Debug_Status2

  • Description: The Debug Status Register 2 gives the Receive and Transmit process status for DMA Channel 7.
  • Size: 32 bits
  • Offset: 0x1014
Table 6. DMA_Debug_Status2 Register Description
Bits Name Memory Access Description
31:8 Reserved_31_8 R

Reserved.
7:4 TPS7 R

DMA Channel 7 Transmit Process State

This field indicates the Tx DMA FSM state for Channel 7. The MSB of this field always returns 0. This field does not generate an interrupt.

Values:

  • 0x0(STOP): Stopped (Reset or Stop Transmit Command issued)
  • 0x1(RUN_FTTD): Running (Fetching Tx Transfer Descriptor)
  • 0x2(RUN_WS): Running (Waiting for status)
  • 0x3(RUN_RDS): Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))
  • 0x4(TSTMP_WS): Timestamp write state
  • 0x5(RSVD): Reserved for future use
  • 0x6(SUSPND): Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)
  • 0x7(RUN_CTD): Running (Closing Tx Descriptor)
3:0 RPS7 R

DMA Channel 7 Receive Process State

This field indicates the Rx DMA FSM state for Channel 7. The MSB of this field always returns 0. This field does not generate an interrupt.

Values:

  • 0x0(STOP): Stopped (Reset or Stop Receive Command issued)
  • 0x1(RUN_FRTD): Running (Fetching Rx Transfer Descriptor)
  • 0x2(RSVD): Reserved for future use
  • 0x3(RUN_WRP): Running (Waiting for Rx packet)
  • 0x4(SUSPND): Suspended (Rx Descriptor Unavailable)
  • 0x5(RUN_CRD): Running (Closing the Rx Descriptor)
  • 0x6(TSTMP): Timestamp write state
  • 0x7(RUN_TRP): Running (Transferring the received packet data from the Rx buffer to the system memory)

AXI4_Tx_AR_ACE_Control

  • Description: This register is used to control the AXI4 Cache Coherency Signals for read transactions by all the Transmit DMA channels. The following signals of the AXI4 interface are driven with different values as programmed for corresponding type (descriptor, buffer1, buffer2) of access.
    • arcache_m_o[3:0]
    • ardomain_m_o[1:0]
  • Size: 32 bits
  • Offset: 0x1020
Table 7. AXI4_Tx_AR_ACE_Control Register Description
Bits Name Memory Access Description
31:22 Reserved_31_22 R

Reserved.
21:20 THD R/W

Transmit DMA First Packet Buffer or TSO Header Domain Control

When TSO is NOT enabled, This field is used to drive ardomain_o[1:0] signal when Transmit DMA is accessing First Buffer of the Packet (First valid buffer with FD being set in the TDES3 of the Descriptor). When TSO is enabled, This field is used to drive ardomain_o[1:0] signal when the Transmit DMA is accessing the TSO Header data.
19:16 THC R/W

Transmit DMA First Packet Buffer or TSO Header Cache Control

When TSO is NOT enabled, This field is used to drive arcache_o[3:0] signal when Transmit DMA is accessing First Buffer of the Packet (First valid buffer with FD being set in the TDES3 of the Descriptor). When TSO is enabled, This field is used to drive arcache_o[3:0] signal when the Transmit DMA is accessing the TSO Header data.
15:14 Reserved_15_14 R

Reserved.
13:12 TED R/W

Transmit DMA Extended Packet Buffer or TSO Payload Domain Control

When TSO is NOT enabled, This field is used to drive ardomain_o[1:0] signal when Transmit DMA is accessing the extended buffers (when packet is distributed across multiple buffers). When TSO is enabled, This field is used to drive ardomain_o[1:0] signal when the Transmit DMA is accessing the TSO payload data.
11:8 TEC R/W

Transmit DMA Extended Packet Buffer or TSO Payload Cache Control

When TSO is NOT enabled, This field is used to drive arcache_o[3:0] signal when Transmit DMA is accessing the extended buffers (when packet is distributed across multiple buffers). When TSO is enabled, This field is used to drive arcache_o[3:0] signal when the Transmit DMA is accessing the TSO payload data.
7:6 Reserved_7_6 R

Reserved.
5:4 TDRD R/W

Transmit DMA Read Descriptor Domain Control

This field is used to drive ardomain_o[1:0] signal when Transmit DMA engines access the Descriptor.
3:0 TDRC R/W

Transmit DMA Read Descriptor Cache Control

This field is used to drive arcache_o[3:0] signal when Transmit DMA engines access the Descriptor.

AXI4_Rx_AW_ACE_Control

  • Description: This register is used to control the AXI4 Cache Coherency Signals for write transactions by all the Receive DMA channels. The following signals of the AXI4 interface are driven with different values as programmed for corresponding type (descriptor, buffer1, buffer2) of access.
    • awcache_m_o[3:0]
    • awdomain_m_o[1:0]
  • Size: 32 bits
  • Offset: 0x1024
Table 8. AXI4_Rx_AW_ACE_Control Register Description
Bits Name Memory Access Description
31:30 Reserved_31_30 R

Reserved.
29:28 RDD R/W

Receive DMA Buffer Domain Control

This field is used to drive the awdomain_o[1:0] signal when Receive DMA is accessing the Buffer when Header and payload are NOT separated.
27:24 RDC R/W

Receive DMA Buffer Cache Control

This field is used to drive awcache_o[3:0] signal when Receive DMA is accessing the Buffer when Header and payload are NOT separated.
23:22 Reserved_23_22 R

Reserved.
21:20 RHD R/W

Receive DMA Header Domain Control

This field is used to drive awdomain_o[1:0] and signal when Receive DMA is accessing the header Buffer when Header and payload are separated.
19:16 RHC R/W

Receive DMA Header Cache Control

This field is used to drive awcache_o[3:0] and signal when Receive DMA is accessing the header Buffer when Header and payload are separated.
15:14 Reserved_15_14 R

Reserved.
13:12 RPD R/W

Receive DMA Payload Domain Control

This field is used to drive awdomain_o[1:0] signal when Receive DMA is accessing the Payload Buffer when Header and payload are separated.
11:8 RPC R/W

Receive DMA Payload Cache Control

This field is used to drive awcache_o[3:0] signal when Receive DMA is accessing the Payload Buffer when Header and payload are separated.
7:6 Reserved_7_6 R

Reserved.
5:4 RDWD R/W

Receive DMA Write Descriptor Domain Control

This field is used to drive awdomain_o[1:0] signal when Receive DMA accesses the Descriptor.
3:0 RDWC R/W

Receive DMA Write Descriptor Cache Control

This field is used to drive awcache_o[3:0] signal when Receive DMA accesses the Descriptor.

AXI4_TxRx_AWAR_ACE_Control

  • Description: This register is used to control the AXI4 Cache Coherency Signals for Descriptor write transactions by all the TxDMA channels and Descriptor read transactions by all the RxDMA channels. It also controls the values to be driven on awprot_m_o and arprot_m_o.
  • Size: 32 bits
  • Offset: 0x1028
Table 9. AXI4_TxRx_AWAR_ACE_Control Register Description
Bits Name Memory Access Description
31:23 Reserved_31_23 R

Reserved.
22:20 WRP R/W

DMA Write Protection control

This field is used to drive awprot_m_o[2:0] signal on the AXI Write Channel.
19 Reserved_19 R

Reserved.
18:16 RDP R/W

DMA Read Protection control

This field is used to drive arprot_m_o[2:0] signal during all read requests.
15:14 Reserved_15_14 R

Reserved.
13:12 RDRD R/W

Receive DMA Read Descriptor Domain control

This field is used to drive ardomain_o[1:0] signal when Receive DMA engines read the Descriptor.
11:8 RDRC R/W

Receive DMA Read Descriptor Cache control

This field is used to drive arcache_o[3:0] signal when Receive DMA engines read the Descriptor.
7:6 Reserved_7_6 R

Reserved.
5:4 TDWD R/W

Transmit DMA Write Descriptor Domain control

This field is used to drive awdomain_o[1:0] signal when Transmit DMA write to the Descriptor.
3:0 TDWC R/W

Transmit DMA Write Descriptor Cache control

This field is used to drive awcache_o[3:0] signal when Transmit DMA writes to the Descriptor.

AXI_LPI_Entry_Interval

  • Description: This register is used to control the AXI LPI entry interval.
  • Size: 32 bits
  • Offset: 0x1040
Table 10. AXI_LPI_Entry_Interval Register Description
Bits Name Memory Access Description
31:4 Reserved_31_4 R

Reserved.
3:0 LPIEI R/W

LPI Entry Interval

Contains the number of system clock cycles, multiplied by 64, to wait for an activity in the DWC_ether_qos to enter into the AXI low power state

0 indicates 64 clock cycles

DMA_TBS_CTRL0

  • Description: This register is used to control the TBS attributes.
  • Size: 32 bits
  • Offset: 0x1050
Table 11. DMA_TBS_CTRL0 Register Description
Bits Name Memory Access Description
31:8 FTOS R/W

Fetch Time Offset

The value in units of 256 nanoseconds, that has to be deducted from the Launch time to compute the Fetch Time. Max value: 999,999,999 ns, additionally should be smaller than CTR-1 value when ESTM mode is set since this value is a modulo CTR value.
7 Reserved_7 R

Reserved.
6:4 FGOS R/W

Fetch GSN Offset

The number GSN slots that must be deducted from the Launch GSN to compute the Fetch GSN. Value valid only when FTOV is set.
3:1 Reserved_3_1 R

Reserved.
0 FTOV R/W

Fetch Time Offset Valid

When set indicates the FTOS field is valid. When not set, indicates the Fetch Offset is not valid and the DMA engine can fetch the frames from host memory without any time restrictions.

Values:

  • 0x0(INVALID): Fetch Time Offset is invalid
  • 0x1(VALID): Fetch Time Offset is valid

DMA_TBS_CTRL1

  • Description: This register is used to control the TBS attributes.
  • Size: 32 bits
  • Offset: 0x1054
Table 12. DMA_TBS_CTRL1 Register Description
Bits Name Memory Access Description
31:8 FTOS R/W

Fetch Time Offset

The value in units of 256 nanoseconds, that has to be deducted from the Launch time to compute the Fetch Time. Max value: 999,999,999 ns, additionally should be smaller than CTR-1 value when ESTM mode is set since this value is a modulo CTR value.
7 Reserved_7 R

Reserved.
6:4 FGOS R/W

Fetch GSN Offset

The number GSN slots that must be deducted from the Launch GSN to compute the Fetch GSN. Value valid only when FTOV is set.
3:1 Reserved_3_1 R

Reserved.
0 FTOV R/W

Fetch Time Offset Valid

When set indicates the FTOS field is valid. When not set, indicates the Fetch Offset is not valid and the DMA engine can fetch the frames from host memory without any time restrictions.

Values:

  • 0x0(INVALID): Fetch Time Offset is invalid
  • 0x1(VALID): Fetch Time Offset is valid

DMA_TBS_CTRL2

  • Description: This register is used to control the TBS attributes.
  • Size: 32 bits
  • Offset: 0x1058
Table 13. DMA_TBS_CTRL2 Register Description
Bits Name Memory Access Description
31:8 FTOS R/W

Fetch Time Offset

The value in units of 256 nanoseconds, that has to be deducted from the Launch time to compute the Fetch Time. Max value: 999,999,999 ns, additionally should be smaller than CTR-1 value when ESTM mode is set since this value is a modulo CTR value.
7 Reserved_7 R

Reserved.
6:4 FGOS R/W

Fetch GSN Offset

The number GSN slots that must be deducted from the Launch GSN to compute the Fetch GSN. Value valid only when FTOV is set.
3:1 Reserved_3_1 R

Reserved.
0 FTOV R/W

Fetch Time Offset Valid

When set indicates the FTOS field is valid. When not set, indicates the Fetch Offset is not valid and the DMA engine can fetch the frames from host memory without any time restrictions.

Values:

  • 0x0(INVALID): Fetch Time Offset is invalid
  • 0x1(VALID): Fetch Time Offset is valid

DMA_TBS_CTRL3

  • Description: This register is used to control the TBS attributes.
  • Size: 32 bits
  • Offset: 0x105c
Table 14. DMA_TBS_CTRL3 Register Description
Bits Name Memory Access Description
31:8 FTOS R/W

Fetch Time Offset

The value in units of 256 nanoseconds, that has to be deducted from the Launch time to compute the Fetch Time. Max value: 999,999,999 ns, additionally should be smaller than CTR-1 value when ESTM mode is set since this value is a modulo CTR value.
7 Reserved_7 R

Reserved.
6:4 FGOS R/W

Fetch GSN Offset

The number GSN slots that must be deducted from the Launch GSN to compute the Fetch GSN. Value valid only when FTOV is set.
3:1 Reserved_3_1 R

Reserved.
0 FTOV R/W

Fetch Time Offset Valid

When set indicates the FTOS field is valid. When not set, indicates the Fetch Offset is not valid and the DMA engine can fetch the frames from host memory without any time restrictions.

Values:

  • 0x0(INVALID): Fetch Time Offset is invalid
  • 0x1(VALID): Fetch Time Offset is valid

DMA_Safety_Interrupt_Status

  • Description: This register indicates summary (whether error occurred in DMA/MTL/MAC and correctable/uncorrectable) of the Automotive Safety related error interrupts.
  • Size: 32 bits
  • Offset: 0x1080
Table 15. DMA_Safety_Interrupt_Status Register Description
Bits Name Memory Access Description
31 MCSIS R

MAC Safety Uncorrectable Interrupt Status

Indicates a uncorrectable Safety related Interrupt is set in the MAC module. MAC_DPP_FSM_Interrupt_Status register should be read when this bit is set, to get the cause of the Safety Interrupt in MAC.

Values:

  • 0x0(INACTIVE): MAC Safety Uncorrectable Interrupt Status not detected
  • 0x1(ACTIVE): MAC Safety Uncorrectable Interrupt Status detected
30 Reserved_30 R

Reserved.
29 MSUIS R

MTL Safety Uncorrectable error Interrupt Status

This bit indicates an uncorrectable error interrupt event in MTL. To get exact cause of the interrupt the software should read the MTL_Safety_Interrupt_Status register.

Values:

  • 0x0(INACTIVE): MTL Safety Uncorrectable error Interrupt Status not detected
  • 0x1(ACTIVE): MTL Safety Uncorrectable error Interrupt Status detected
28 MSCIS R

MTL Safety Correctable error Interrupt Status

This bit indicates a correctable error interrupt event in MTL. To get exact cause of the interrupt the software should read the MTL_Safety_Interrupt_Status register.

Values:

  • 0x0(INACTIVE): MTL Safety Correctable error Interrupt Status not detected
  • 0x1(ACTIVE): MTL Safety Correctable error Interrupt Status detected
27:2 Reserved_27_2 R

Reserved.
1 DEUIS R

DMAECC Uncorrectable error Interrupt Status

This bit indicates an interrupt event in the DMA ECC safety feature. To get the exact cause of the interrupt the application should read the DMA_ECC_Interrupt_Status register.

Values:

  • 0x0(INACTIVE): DMA ECC Uncorrectable error Interrupt Status not detected
  • 0x1(ACTIVE): DMA ECC Uncorrectable error Interrupt Status detected
0 DECIS R

DMAECC Correctable error Interrupt Status

This bit indicates an interrupt event in the DMA ECC safety feature. To get the exact cause of the interrupt the application should read the DMA_ECC_Interrupt_Status register.

Values:

  • 0x0(INACTIVE): DMA ECC Correctable error Interrupt Status not detected
  • 0x1(ACTIVE): DMA ECC Correctable error Interrupt Status detected

DMA_ECC_Interrupt_enable

  • Description: This register is used to enable the Automotive Safety related TSO memory/DCACHE ECC error interrupt.
  • Size: 32 bits
  • Offset: 0x1084
Table 16. DMA_ECC_Interrupt_enable Register Description
Bits Name Memory Access Description
31:2 Reserved_31_2 R

Reserved.
1 DCEIE R/W

DCACHE memory Correctable Error Interrupt Enable

  • 1: Generates an interrupt when a correctable error is detected at the DMA DCACHE memory interface. It is indicated in the DCES bit of DMA_ECC_Interrupt_Status register.
  • 0: Does not generates an interrupt.
0 TCEIE R/W

TSO memory Correctable Error Interrupt Enable

  • 1: Generates an interrupt when a correctable error is detected at the DMA TSO memory interface. It is indicated in the TCES bit of DMA_ECC_Interrupt_Status register.
  • 0: Does not generates an interrupt.

DMA_ECC_Interrupt_Status

  • Description: This register indicates the Automotive Safety related TSO memory/DCACHE memory ECC error interrupt status.
  • Size: 32 bits
  • Offset: 0x1088
Table 17. DMA_ECC_Interrupt_Status Register Description
Bits Name Memory Access Description
31:7 Reserved_31_7 R

Reserved.
6 DUES R/W

DMADCACHE memory Uncorrectable Error status

When set, indicates that an uncorrectable error is detected at DMADCACHE memory interface.
5 DAMS R/W

DMADCACHE memory Address Mismatch status

This bit when set indicates that address mismatch is found for address bus of DMA DCACHE memory.
4 DCES R/W

DMADCACHE memory Correctable Error status

This bit when set indicates that correctable error is detected at DMA DCACHE memory interface.
3 Reserved_3 R

Reserved.
2 TUES R/W

DMATSO memory Uncorrectable Error status

When set, indicates that an uncorrectable error is detected at DMATSO memory interface.
1 TAMS R/W

DMATSO memory Address Mismatch status

This bit when set indicates that address mismatch is found for address bus of DMA TSO memory.
0 TCES R/W

DMA TSO memory Correctable Error status

This bit when set indicates that correctable error is detected at DMA TSO memory interface.