EQOS_DMA Registers
Ethernet GMAC has the following EQOS_DMA registers.
DMA_Mode
- Description: The Bus Mode register establishes the bus operating modes for the DMA.
- Size: 32 bits
- Offset: 0x1000
Bits | Name | Memory Access | Description |
---|---|---|---|
31:24 | Reserved_31_24 | R |
Reserved. |
23:22 | RNDF | R/W |
Rx DMA's Maximum Number of Descriptors to be fetched in a burst
|
21:20 | TNDF | R/W |
Tx DMA's Maximum Number of Descriptors to be fetched in a burst
|
19 | DCHE | R/W |
Descriptor Cache Enable When set enables prefetching of descriptors to the Descriptor Cache. When reset descriptor cache feature is disabled. Values:
|
18 | Reserved_18 | R |
Reserved. |
17:16 | INTM | R/W |
Interrupt Mode This field defines the interrupt mode of DWC_ether_qos. The behavior of the following outputs change depending on the following settings:
It also changes the behavior ofthe RI/TI bits in the DMA_CH0_Status.
Values:
|
15 | Reserved_15 | R |
Reserved. |
14:12 | PR | R/W |
Priority Ratio These bits control the priority ratio in weighted round-robin arbitration between the Rx DMA and Tx DMA. These bits are valid only when the DA bit is reset. The priority ratio is Rx:Tx or Tx:Rx depending on whether the TXPR bit is reset or set. Values:
|
11 | TXPR | R/W |
Transmit Priority When set, this bit indicates that the Tx DMA has higher priority than the Rx DMA during arbitration for the system-side bus or Descriptor reads from DCACHE memory when DWC_EQOS_DCEXT is enabled Values:
|
10 | SCSW | R/W |
SCSW is Synopsys Reserved, This field must be set to "0". This field is reserved for Synopsys Internal use, and must always be set to "0" unless instructed by Synopsys. Setting this field to "1" might cause unexpected behavior in the IP. Values:
|
9 | ARBC | R/W |
ARBC is Synopsys Reserved, This field must be set to "0".
Values:
|
8 | DSPW | R/W |
Descriptor Posted Write When this bit is set to
Values:
|
7:5 | Reserved_7_5 | R |
Reserved. |
4:2 | TAA | R/W |
Transmit Arbitration Algorithm This field is used to select the arbitration algorithm for the Transmit side when multiple Tx DMAs are selected. Values:
|
1 | DA | R/W |
DMA Tx or Rx Arbitration Scheme This bit specifies the arbitration scheme between the Transmit and Receive paths of all channels:
The priority between the paths is according to the priority specified in Bits[14:12] and the priority weight is specified in the TXPR bit.
The Tx path has priority over the Rx path when the TXPR bit is set. Otherwise, the Rx path has priority over the Tx path. Values:
|
0 | SWR | R/W |
Software Reset When this bit is set, the MAC and the DMA controller reset the logic and all internal registers of the DMA, MTL, and MAC. This bit is automatically cleared after the reset operation is complete in all DWC_ether_qos clock domains. Before reprogramming any DWC_ether_qos register, a value of zero should be read in this bit. This bit must be read at least 4 CSR clock cycles after it is written to 1. Note:The reset operation is complete only when all resets in all active clock domains are de-asserted. Therefore, it is essential that all PHY inputs clocks (applicable for the selected PHY interface) are present for software reset completion. The time to complete the software reset operation depends on the frequency of the slowest active clock. Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect. Values:
|
DMA_SysBus_Mode
- Description: The System Bus mode register controls the behavior of the AHB or AXI master. It mainly controls burst splitting and number of outstanding requests.
- Size: 32 bits
- Offset: 0x1004
Bits | Name | Memory Access | Description |
---|---|---|---|
31 | EN_LPI | R/W |
Enable Low Power Interface (LPI) When set to
EQOS-AXI configuration and accepts the LPI request from the AXI System Clock controller.
Values:
|
30 | LPI_XIT_PKT | R/W |
Unlock on Magic Packet or Remote Wake-Up Packet When set to 1, this bit enables the AXI master to come out of the LPI mode only when the magic packet or remote wake-up packet is received. When set to 0, this bit enables the AXI master to come out of the LPI mode when any packet is received. Values:
|
29:y | Reserved_29_y | R |
Reserved. |
x:24 | WR_OSR_LMT | R/W |
AXI Maximum Write Outstanding Request Limit This value limits the maximum outstanding request on the AXI write interface. Maximum outstanding requests = WR_OSR_LMT + 1 |
23:y | Reserved_23_y | R |
Reserved. |
x:16 | RD_OSR_LMT | R/W |
AXI Maximum Read Outstanding Request Limit This value limits the maximum outstanding request on the AXI read interface. Maximum outstanding requests = RD_OSR_LMT + 1 |
15 | RB | R/W |
Rebuild INCRx Burst When this bit is set high and the AHB master gets SPLIT, RETRY, or Early Burst Termination (EBT) response, the AHB master interface rebuilds the pending beats of any initiated burst transfer with INCRx and SINGLE transfers. By default, the AHB master interface rebuilds the pending beats of an EBT with an unspecified (INCR) burst. Values:
|
14 | MB | R/W |
Mixed Burst When this bit is high and the FB bit is low, the AHB master performs undefined bursts transfers (INCR) for burst length of 16 or more. For burst length of 16 or less, the AHB master performs fixed burst transfers (INCRx and SINGLE). Values:
|
13 | ONEKBBE | R/W |
1KB Boundary Crossing Enable for the EQOS-AXI Master
Values:
|
12 | AAL | R/W |
Address-Aligned Beats When this bit is set to 1, the EQOS-AXI or EQOS-AHB master performs address-aligned burst transfers on Read and Write channels. When this bit is set to 0, the EQOS-AXI or EQOS-AHB master performs burst transfers on Read and Write channels without aligning to address boundaries. Values:
|
11 | EAME | R/W |
Enhanced Address Mode Enable. When set to
Values:
|
10 | AALE | R/W |
Automatic AXI LPI enable When set to 1, enables the AXI master to enter into LPI state when there is no activity in the DWC_ether_qos for number of system clock cycles programmed in the LPIEI field of AXI_LPI_Entry_Interval register. Values:
|
9:8 | Reserved_9_8 | R |
Reserved. |
7 | BLEN256 | R/W |
AXI Burst Length 256 When set to
Values:
|
6 | BLEN128 | R/W |
AXI Burst Length 128 When set to
Values:
|
5 | BLEN64 | R/W |
AXI Burst Length 64When set to
Values:
|
4 | BLEN32 | R/W |
AXI Burst Length 32When set to
Values:
|
3 | BLEN16 | R/W |
AXI Burst Length 16 When this bit is set to 1 or the FB bit is set to 1, the EQOS-AXI master can select a burst length of 16 on the AXI interface. When the FB bit is set to 0, setting this bit has no effect. Values:
|
2 | BLEN8 | R/W |
AXI Burst Length 8 When this bit is set to 1 or the FB bit is set to 1, the EQOS-AXI master can select a burst length of 8 on the AXI interface. When the FB bit is set to 0, setting this bit has no effect. Values:
|
1 | BLEN4 | R/W |
AXI Burst Length 4 When this bit is set to 1 or the FB bit is set to 1, the EQOS-AXI master can select a burst length of 4 on the AXI interface. When the FB bit is set to 0, setting this bit has no effect. Values:
|
0 | FB | R/W |
Fixed Burst Length ForEQOS-AXI Configurations:
ForEQOS-AHB Configurations:\
ForEQOS-DMAConfigurations: The value of this bit is driven on the mdc_burst_count_o output signal. Values:
|
DMA_Interrupt_Status
- Description: The application reads this Interrupt Status register during interrupt service routine or polling to determine the interrupt status of DMA channels, MTL queues, and the MAC.
- Size: 32 bits
- Offset: 0x1008
Bits | Name | Memory Access | Description |
---|---|---|---|
31:18 | Reserved_31_18 | R |
Reserved. |
17 | MACIS | R |
MAC Interrupt Status This bit indicates an interrupt event in the MAC. To reset this bit to 1'b0, the software must read the corresponding register in the MAC to get the exact cause of the interrupt and clear its source. Values:
|
16 | MTLIS | R |
MTL Interrupt Status This bit indicates an interrupt event in the MTL. To reset this bit to 1'b0, the software must read the corresponding register in the MTL to get the exact cause of the interrupt and clear its source. Values:
|
15:8 | Reserved_15_8 | R |
Reserved. |
7 | DC7IS | R |
DMA Channel 7 Interrupt Status This bit indicates an interrupt event in DMA Channel 7. To reset this bit to 1'b0, the software must read the corresponding register in DMA Channel 7 to get the exact cause of the interrupt and clear its source. Values:
|
6 | DC6IS | R |
DMA Channel 6 Interrupt Status This bit indicates an interrupt event in DMA Channel 6. To reset this bit to 1'b0, the software must read the corresponding register in DMA Channel 6 to get the exact cause of the interrupt and clear its source. Values:
|
5 | DC5IS | R |
DMA Channel 5 Interrupt Status This bit indicates an interrupt event in DMA Channel 5. To reset this bit to 1'b0, the software must read the corresponding register in DMA Channel 5 to get the exact cause of the interrupt and clear its source. Values:
|
4 | DC4IS | R |
DMA Channel 4 Interrupt Status This bit indicates an interrupt event in DMA Channel 4. To reset this bit to 1'b0, the software must read the corresponding register in DMA Channel 4 to get the exact cause of the interrupt and clear its source. Values:
|
3 | DC3IS | R |
DMA Channel 3 Interrupt Status This bit indicates an interrupt event in DMA Channel 3. To reset this bit to 1'b0, the software must read the corresponding register in DMA Channel 3 to get the exact cause of the interrupt and clear its source. Values:
|
2 | DC2IS | R |
DMA Channel 2 Interrupt Status This bit indicates an interrupt event in DMA Channel 2. To reset this bit to 1'b0, the software must read the corresponding register in DMA Channel 2 to get the exact cause of the interrupt and clear its source. Values:
|
1 | DC1IS | R |
DMA Channel 1 Interrupt Status This bit indicates an interrupt event in DMA Channel 1. To reset this bit to 1'b0, the software must read the corresponding register in DMA Channel 1 to get the exact cause of the interrupt and clear its source. Values:
|
0 | DC0IS | R |
DMA Channel 0 Interrupt Status This bit indicates an interrupt event in DMA Channel 0. To reset this bit to 1'b0, the software must read the corresponding register in DMA Channel 0 to get the exact cause of the interrupt and clear its source. Values:
|
DMA_Debug_Status0
- Description: The Debug Status 0 register gives the Receive and Transmit process status for DMA Channel 0-Channel 2 for debugging purpose.
- Size: 32 bits
- Offset: 0x100c
Bits | Name | Memory Access | Description |
---|---|---|---|
31:28 | TPS2 | R |
DMA Channel 2 Transmit Process State This field indicates the Tx DMA FSM state for Channel 2. The MSB of this field always returns 0. This field does not generate an interrupt. Values:
|
27:24 | RPS2 | R |
DMA Channel 2 Receive Process State This field indicates the Rx DMA FSM state for Channel 2. The MSB of this field always returns 0. This field does not generate an interrupt. Values:
|
23:20 | TPS1 | R |
DMA Channel 1 Transmit Process State This field indicates the Tx DMA FSM state for Channel 1. The MSB of this field always returns 0. This field does not generate an interrupt. Values:
|
19:16 | RPS1 | R |
DMA Channel 1 Receive Process State This field indicates the Rx DMA FSM state for Channel 1. The MSB of this field always returns 0. This field does not generate an interrupt. Values:
|
15:12 | TPS0 | R |
DMA Channel 0 Transmit Process State This field indicates the Tx DMA FSM state for Channel 0. The MSB of this field always returns 0. This field does not generate an interrupt. Values:
|
11:8 | RPS0 | R |
DMA Channel 0 Receive Process State This field indicates the Rx DMA FSM state for Channel 0. The MSB of this field always returns 0. This field does not generate an interrupt. Values:
|
7:2 | Reserved_7_2 | R |
Reserved. |
1 | AXRHSTS | R |
AXI Master Read Channel Status When high, this bit indicates that the read channel of the AXI master is active, and it is transferring the data. Values:
|
0 | AXWHSTS | R |
AXI Master Write Channel or AHB Master Status EQOS-AXI Configuration: When high, this bit indicates that the write channel of the AXI master is active, and it is transferring data. EQOS-AHB Configuration: When high, this bit indicates that the AHB master FSMs are in the non-idle state. Values:
|
DMA_Debug_Status1
- Description: The Debug Status1 register gives the Receive and Transmit process status for DMA Channel 3-Channel 6.
- Size: 32 bits
- Offset: 0x1010
Bits | Name | Memory Access | Description |
---|---|---|---|
31:28 | TPS6 | R |
DMA Channel 6 Transmit Process State This field indicates the Tx DMA FSM state for Channel 6. The MSB of this field always returns 0. This field does not generate an interrupt. Values:
|
27:24 | RPS6 | R |
DMA Channel 6 Receive Process State This field indicates the Rx DMA FSM state for Channel 6. The MSB of this field always returns 0. This field does not generate an interrupt. Values:
|
23:20 | TPS5 | R |
DMA Channel 5 Transmit Process State This field indicates the Tx DMA FSM state for Channel 5. The MSB of this field always returns 0. This field does not generate an interrupt. Values:
|
19:16 | RPS5 | R |
DMA Channel 5 Receive Process State This field indicates the Rx DMA FSM state for Channel 5. The MSB of this field always returns 0. This field does not generate an interrupt. Values:
|
15:12 | TPS4 | R |
DMA Channel 4 Transmit Process State This field indicates the Tx DMA FSM state for Channel 4. The MSB of this field always returns 0. This field does not generate an interrupt. Values:
|
11:8 | RPS4 | R |
DMA Channel 4 Receive Process State This field indicates the Rx DMA FSM state for Channel 4. The MSB of this field always returns 0. This field does not generate an interrupt. Values:
|
7:4 | TPS3 | R |
DMA Channel 3 Transmit Process State This field indicates the Tx DMA FSM state for Channel 3. The MSB of this field always returns 0. This field does not generate an interrupt. Values:
|
3:0 | RPS3 | R |
DMA Channel 3 Receive Process State This field indicates the Rx DMA FSM state for Channel 3. The MSB of this field always returns 0. This field does not generate an interrupt. Values:
|
DMA_Debug_Status2
- Description: The Debug Status Register 2 gives the Receive and Transmit process status for DMA Channel 7.
- Size: 32 bits
- Offset: 0x1014
Bits | Name | Memory Access | Description |
---|---|---|---|
31:8 | Reserved_31_8 | R |
Reserved. |
7:4 | TPS7 | R |
DMA Channel 7 Transmit Process State This field indicates the Tx DMA FSM state for Channel 7. The MSB of this field always returns 0. This field does not generate an interrupt. Values:
|
3:0 | RPS7 | R |
DMA Channel 7 Receive Process State This field indicates the Rx DMA FSM state for Channel 7. The MSB of this field always returns 0. This field does not generate an interrupt. Values:
|
AXI4_Tx_AR_ACE_Control
- Description: This register is used to control the AXI4 Cache
Coherency Signals for read transactions by all the Transmit DMA channels.
The following signals of the AXI4 interface are driven with different values
as programmed for corresponding type (descriptor, buffer1, buffer2) of
access.
- arcache_m_o[3:0]
- ardomain_m_o[1:0]
- Size: 32 bits
- Offset: 0x1020
Bits | Name | Memory Access | Description |
---|---|---|---|
31:22 | Reserved_31_22 | R |
Reserved. |
21:20 | THD | R/W |
Transmit DMA First Packet Buffer or TSO Header Domain Control When TSO is NOT enabled, This field is used to drive ardomain_o[1:0] signal when Transmit DMA is accessing First Buffer of the Packet (First valid buffer with FD being set in the TDES3 of the Descriptor). When TSO is enabled, This field is used to drive ardomain_o[1:0] signal when the Transmit DMA is accessing the TSO Header data. |
19:16 | THC | R/W |
Transmit DMA First Packet Buffer or TSO Header Cache Control When TSO is NOT enabled, This field is used to drive arcache_o[3:0] signal when Transmit DMA is accessing First Buffer of the Packet (First valid buffer with FD being set in the TDES3 of the Descriptor). When TSO is enabled, This field is used to drive arcache_o[3:0] signal when the Transmit DMA is accessing the TSO Header data. |
15:14 | Reserved_15_14 | R |
Reserved. |
13:12 | TED | R/W |
Transmit DMA Extended Packet Buffer or TSO Payload Domain Control When TSO is NOT enabled, This field is used to drive ardomain_o[1:0] signal when Transmit DMA is accessing the extended buffers (when packet is distributed across multiple buffers). When TSO is enabled, This field is used to drive ardomain_o[1:0] signal when the Transmit DMA is accessing the TSO payload data. |
11:8 | TEC | R/W |
Transmit DMA Extended Packet Buffer or TSO Payload Cache Control When TSO is NOT enabled, This field is used to drive arcache_o[3:0] signal when Transmit DMA is accessing the extended buffers (when packet is distributed across multiple buffers). When TSO is enabled, This field is used to drive arcache_o[3:0] signal when the Transmit DMA is accessing the TSO payload data. |
7:6 | Reserved_7_6 | R |
Reserved. |
5:4 | TDRD | R/W |
Transmit DMA Read Descriptor Domain Control This field is used to drive ardomain_o[1:0] signal when Transmit DMA engines access the Descriptor. |
3:0 | TDRC | R/W |
Transmit DMA Read Descriptor Cache Control This field is used to drive arcache_o[3:0] signal when Transmit DMA engines access the Descriptor. |
AXI4_Rx_AW_ACE_Control
- Description: This register is used to control the AXI4 Cache
Coherency Signals for write transactions by all the Receive DMA channels.
The following signals of the AXI4 interface are driven with different values
as programmed for corresponding type (descriptor, buffer1, buffer2) of
access.
- awcache_m_o[3:0]
- awdomain_m_o[1:0]
- Size: 32 bits
- Offset: 0x1024
Bits | Name | Memory Access | Description |
---|---|---|---|
31:30 | Reserved_31_30 | R |
Reserved. |
29:28 | RDD | R/W |
Receive DMA Buffer Domain Control This field is used to drive the awdomain_o[1:0] signal when Receive DMA is accessing the Buffer when Header and payload are NOT separated. |
27:24 | RDC | R/W |
Receive DMA Buffer Cache Control This field is used to drive awcache_o[3:0] signal when Receive DMA is accessing the Buffer when Header and payload are NOT separated. |
23:22 | Reserved_23_22 | R |
Reserved. |
21:20 | RHD | R/W |
Receive DMA Header Domain Control This field is used to drive awdomain_o[1:0] and signal when Receive DMA is accessing the header Buffer when Header and payload are separated. |
19:16 | RHC | R/W |
Receive DMA Header Cache Control This field is used to drive awcache_o[3:0] and signal when Receive DMA is accessing the header Buffer when Header and payload are separated. |
15:14 | Reserved_15_14 | R |
Reserved. |
13:12 | RPD | R/W |
Receive DMA Payload Domain Control This field is used to drive awdomain_o[1:0] signal when Receive DMA is accessing the Payload Buffer when Header and payload are separated. |
11:8 | RPC | R/W |
Receive DMA Payload Cache Control This field is used to drive awcache_o[3:0] signal when Receive DMA is accessing the Payload Buffer when Header and payload are separated. |
7:6 | Reserved_7_6 | R |
Reserved. |
5:4 | RDWD | R/W |
Receive DMA Write Descriptor Domain Control This field is used to drive awdomain_o[1:0] signal when Receive DMA accesses the Descriptor. |
3:0 | RDWC | R/W |
Receive DMA Write Descriptor Cache Control This field is used to drive awcache_o[3:0] signal when Receive DMA accesses the Descriptor. |
AXI4_TxRx_AWAR_ACE_Control
- Description: This register is used to control the AXI4 Cache Coherency Signals for Descriptor write transactions by all the TxDMA channels and Descriptor read transactions by all the RxDMA channels. It also controls the values to be driven on awprot_m_o and arprot_m_o.
- Size: 32 bits
- Offset: 0x1028
Bits | Name | Memory Access | Description |
---|---|---|---|
31:23 | Reserved_31_23 | R |
Reserved. |
22:20 | WRP | R/W |
DMA Write Protection control This field is used to drive awprot_m_o[2:0] signal on the AXI Write Channel. |
19 | Reserved_19 | R |
Reserved. |
18:16 | RDP | R/W |
DMA Read Protection control This field is used to drive arprot_m_o[2:0] signal during all read requests. |
15:14 | Reserved_15_14 | R |
Reserved. |
13:12 | RDRD | R/W |
Receive DMA Read Descriptor Domain control This field is used to drive ardomain_o[1:0] signal when Receive DMA engines read the Descriptor. |
11:8 | RDRC | R/W |
Receive DMA Read Descriptor Cache control This field is used to drive arcache_o[3:0] signal when Receive DMA engines read the Descriptor. |
7:6 | Reserved_7_6 | R |
Reserved. |
5:4 | TDWD | R/W |
Transmit DMA Write Descriptor Domain control This field is used to drive awdomain_o[1:0] signal when Transmit DMA write to the Descriptor. |
3:0 | TDWC | R/W |
Transmit DMA Write Descriptor Cache control This field is used to drive awcache_o[3:0] signal when Transmit DMA writes to the Descriptor. |
AXI_LPI_Entry_Interval
- Description: This register is used to control the AXI LPI entry interval.
- Size: 32 bits
- Offset: 0x1040
Bits | Name | Memory Access | Description |
---|---|---|---|
31:4 | Reserved_31_4 | R |
Reserved. |
3:0 | LPIEI | R/W |
LPI Entry Interval Contains the number of system clock cycles, multiplied by 64, to wait for an activity in the DWC_ether_qos to enter into the AXI low power state 0 indicates 64 clock cycles |
DMA_TBS_CTRL0
- Description: This register is used to control the TBS attributes.
- Size: 32 bits
- Offset: 0x1050
Bits | Name | Memory Access | Description |
---|---|---|---|
31:8 | FTOS | R/W |
Fetch Time Offset The value in units of 256 nanoseconds, that has to be deducted from the Launch time to compute the Fetch Time. Max value: 999,999,999 ns, additionally should be smaller than CTR-1 value when ESTM mode is set since this value is a modulo CTR value. |
7 | Reserved_7 | R |
Reserved. |
6:4 | FGOS | R/W |
Fetch GSN Offset The number GSN slots that must be deducted from the Launch GSN to compute the Fetch GSN. Value valid only when FTOV is set. |
3:1 | Reserved_3_1 | R |
Reserved. |
0 | FTOV | R/W |
Fetch Time Offset Valid When set indicates the FTOS field is valid. When not set, indicates the Fetch Offset is not valid and the DMA engine can fetch the frames from host memory without any time restrictions. Values:
|
DMA_TBS_CTRL1
- Description: This register is used to control the TBS attributes.
- Size: 32 bits
- Offset: 0x1054
Bits | Name | Memory Access | Description |
---|---|---|---|
31:8 | FTOS | R/W |
Fetch Time Offset The value in units of 256 nanoseconds, that has to be deducted from the Launch time to compute the Fetch Time. Max value: 999,999,999 ns, additionally should be smaller than CTR-1 value when ESTM mode is set since this value is a modulo CTR value. |
7 | Reserved_7 | R |
Reserved. |
6:4 | FGOS | R/W |
Fetch GSN Offset The number GSN slots that must be deducted from the Launch GSN to compute the Fetch GSN. Value valid only when FTOV is set. |
3:1 | Reserved_3_1 | R |
Reserved. |
0 | FTOV | R/W |
Fetch Time Offset Valid When set indicates the FTOS field is valid. When not set, indicates the Fetch Offset is not valid and the DMA engine can fetch the frames from host memory without any time restrictions. Values:
|
DMA_TBS_CTRL2
- Description: This register is used to control the TBS attributes.
- Size: 32 bits
- Offset: 0x1058
Bits | Name | Memory Access | Description |
---|---|---|---|
31:8 | FTOS | R/W |
Fetch Time Offset The value in units of 256 nanoseconds, that has to be deducted from the Launch time to compute the Fetch Time. Max value: 999,999,999 ns, additionally should be smaller than CTR-1 value when ESTM mode is set since this value is a modulo CTR value. |
7 | Reserved_7 | R |
Reserved. |
6:4 | FGOS | R/W |
Fetch GSN Offset The number GSN slots that must be deducted from the Launch GSN to compute the Fetch GSN. Value valid only when FTOV is set. |
3:1 | Reserved_3_1 | R |
Reserved. |
0 | FTOV | R/W |
Fetch Time Offset Valid When set indicates the FTOS field is valid. When not set, indicates the Fetch Offset is not valid and the DMA engine can fetch the frames from host memory without any time restrictions. Values:
|
DMA_TBS_CTRL3
- Description: This register is used to control the TBS attributes.
- Size: 32 bits
- Offset: 0x105c
Bits | Name | Memory Access | Description |
---|---|---|---|
31:8 | FTOS | R/W |
Fetch Time Offset The value in units of 256 nanoseconds, that has to be deducted from the Launch time to compute the Fetch Time. Max value: 999,999,999 ns, additionally should be smaller than CTR-1 value when ESTM mode is set since this value is a modulo CTR value. |
7 | Reserved_7 | R |
Reserved. |
6:4 | FGOS | R/W |
Fetch GSN Offset The number GSN slots that must be deducted from the Launch GSN to compute the Fetch GSN. Value valid only when FTOV is set. |
3:1 | Reserved_3_1 | R |
Reserved. |
0 | FTOV | R/W |
Fetch Time Offset Valid When set indicates the FTOS field is valid. When not set, indicates the Fetch Offset is not valid and the DMA engine can fetch the frames from host memory without any time restrictions. Values:
|
DMA_Safety_Interrupt_Status
- Description: This register indicates summary (whether error occurred in DMA/MTL/MAC and correctable/uncorrectable) of the Automotive Safety related error interrupts.
- Size: 32 bits
- Offset: 0x1080
Bits | Name | Memory Access | Description |
---|---|---|---|
31 | MCSIS | R |
MAC Safety Uncorrectable Interrupt Status Indicates a uncorrectable Safety related Interrupt is set in the MAC module. MAC_DPP_FSM_Interrupt_Status register should be read when this bit is set, to get the cause of the Safety Interrupt in MAC. Values:
|
30 | Reserved_30 | R |
Reserved. |
29 | MSUIS | R |
MTL Safety Uncorrectable error Interrupt Status This bit indicates an uncorrectable error interrupt event in MTL. To get exact cause of the interrupt the software should read the MTL_Safety_Interrupt_Status register. Values:
|
28 | MSCIS | R |
MTL Safety Correctable error Interrupt Status This bit indicates a correctable error interrupt event in MTL. To get exact cause of the interrupt the software should read the MTL_Safety_Interrupt_Status register. Values:
|
27:2 | Reserved_27_2 | R |
Reserved. |
1 | DEUIS | R |
DMAECC Uncorrectable error Interrupt Status This bit indicates an interrupt event in the DMA ECC safety feature. To get the exact cause of the interrupt the application should read the DMA_ECC_Interrupt_Status register. Values:
|
0 | DECIS | R |
DMAECC Correctable error Interrupt Status This bit indicates an interrupt event in the DMA ECC safety feature. To get the exact cause of the interrupt the application should read the DMA_ECC_Interrupt_Status register. Values:
|
DMA_ECC_Interrupt_enable
- Description: This register is used to enable the Automotive Safety related TSO memory/DCACHE ECC error interrupt.
- Size: 32 bits
- Offset: 0x1084
Bits | Name | Memory Access | Description |
---|---|---|---|
31:2 | Reserved_31_2 | R |
Reserved. |
1 | DCEIE | R/W |
DCACHE memory Correctable Error Interrupt Enable
|
0 | TCEIE | R/W |
TSO memory Correctable Error Interrupt Enable
|
DMA_ECC_Interrupt_Status
- Description: This register indicates the Automotive Safety related TSO memory/DCACHE memory ECC error interrupt status.
- Size: 32 bits
- Offset: 0x1088
Bits | Name | Memory Access | Description |
---|---|---|---|
31:7 | Reserved_31_7 | R |
Reserved. |
6 | DUES | R/W |
DMADCACHE memory Uncorrectable Error status When set, indicates that an uncorrectable error is detected at DMADCACHE memory interface. |
5 | DAMS | R/W |
DMADCACHE memory Address Mismatch status This bit when set indicates that address mismatch is found for address bus of DMA DCACHE memory. |
4 | DCES | R/W |
DMADCACHE memory Correctable Error status This bit when set indicates that correctable error is detected at DMA DCACHE memory interface. |
3 | Reserved_3 | R |
Reserved. |
2 | TUES | R/W |
DMATSO memory Uncorrectable Error status When set, indicates that an uncorrectable error is detected at DMATSO memory interface. |
1 | TAMS | R/W |
DMATSO memory Address Mismatch status This bit when set indicates that address mismatch is found for address bus of DMA TSO memory. |
0 | TCES | R/W |
DMA TSO memory Correctable Error status This bit when set indicates that correctable error is detected at DMA TSO memory interface. |