EQOS_MAC Registers (Edit Done with Comments)

When this bit is set, the MAC can recognize an incoming ARP request packet and schedules the ARP packet for transmission. It forwards the ARP packet to the application and also indicates the events in the Rx Status.

When this bit is reset, the MAC receiver does not recognize any ARP packet and indicates them as Type frame in the Rx Status.

This bit is available only when the Enable IPv4 ARP Offload is selected.

Values:

• 0x0(DISABLE): ARP Offload is disabled
• 0x1(ENABLE): ARP Offload is enabled

This field controls the source address insertion or replacement for all transmitted packets. Bit 30 specifies which MAC Address register (0 or 1) is used for source address insertion or replacement based on the values of Bits[29:28]:

2'b0x:

• The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation.

2'b10:

• If Bit 30 is set to 0, the MAC inserts the content of the MAC Address 0 registers in the SA field of all transmitted packets.
• If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected while configuring the IP, the MAC inserts the content of the MAC Address 1 registers in the SA field of all transmitted packets.

2'b11:

• If Bit 30 is set to 0, the MAC replaces the content of the MAC Address 0 registers in the SA field of all transmitted packets.
• If Bit 30 is set to 1 and the MAC Address Register 1 is enabled, the MAC replaces the content of the MAC Address 1 registers in the SA field of all transmitted packets.

Values:

• 0x0(SA_CTRL_IN): mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation
• 0x2(MAC0_INS_SA): Contents of MAC Addr-0 inserted in SA field
• 0x3(MAC0_REP_SA): Contents of MAC Addr-0 replaces SA field
• 0x6(MAC1_INS_SA): Contents of MAC Addr-1 inserted in SA field
• 0x7(MAC1_REP_SA): Contents of MAC Addr-1 replaces SA field

When set, this bit enables the IPv4 header checksum checking and IPv4 or IPv6 TCP, UDP, or ICMP payload checksum checking. When this bit is reset, the COE function in the receiver is disabled.

The Layer 3 and Layer 4 Packet Filter and Enable Split Header features automatically select the IPC Full Checksum Offload Engine on the Receive side. When any of these features are enabled, you must set the IPC bit.

Values:

• 0x0(DISABLE): IP header/payload checksum checking is disabled
• 0x1(ENABLE): IP header/payload checksum checking is enabled

Inter-Packet Gap

These bits control the minimum IPG between packets during transmission. This range of minimum IPG is valid in full-duplex mode.

In the half-duplex mode, the minimum IPG can be configured only for 64-bit times (IPG = 100). Lower values are not considered.

When a JAM pattern is being transmitted because of back pressure activation, the MAC does not consider the minimum IPG.

This function (IPG less than 96bit times) is valid only when EIPGEN bit in MAC_Ext_Configuration register is reset. When EIPGEN is set, then the minimum IPG (greater than 96 bit times) is controlled as per the description given in EIPG field in MAC_Ext_Configuration register.

Values:

• 0x0(IPG96): 96 bit times IPG
• 0x1(IPG88): 88 bit times IPG
• 0x2(IPG80): 80 bit times IPG
• 0x3(IPG72): 72 bit times IPG
• 0x4(IPG64): 64 bit times IPG
• 0x5(IPG56): 56 bit times IPG
• 0x6(IPG48): 48 bit times IPG
• 0x7(IPG40): 40 bit times IPG

When this bit is set, the MAC considers the value in GPSL field in MAC_Ext_Configuration register to declare a received packet as Giant packet. This field must be programmed to more than 1518 bytes. Otherwise, the MAC considers 1518 bytes as giant packet limit.

When this bit is reset, the MAC considers a received packet as Giant packet when its size is greater than 1518 bytes (1522 bytes for tagged packet).

The watchdog timeout limit. Jumbo Packet Enable and 2KPacket Enable have higher precedence over this bit, that is the MAC considers a received packet as Giant packet when its size is greater than 9018 bytes (9022 bytes for tagged packet) with Jumbo Packet Enabled and greater than 2000 bytes with 2K Packet Enabled.

The watchdog timeout, if enabled, terminates the received packet when watchdog limit is reached. Therefore, the programmed giant packet limit should be less than the watchdog limit to get the giant packet status.

Values:

• 0x0(DISABLE): Giant Packet Size Limit Control is disabled
• 0x1(ENABLE): Giant Packet Size Limit Control is enabled

When this bit is set, the MAC considers all packets with up to 2,000 bytes in length as normal packets. When the JE bit is not set, the MAC considers all received packets of size more than 2K bytes as Giant packets.

When this bit is reset and the JE bit is not set, the MAC considers all received packets of size more than 1518 bytes (1522 bytes for tagged) as giant packets.

Values:

• 0x0(DISABLE): Support up to 2K packet is disabled
• 0x1(ENABLE): Support up to 2K packet is Enabled

CRC stripping for Type packets

When this bit is set, the last four bytes (FCS) of all packets of Ether type (type field greater than 1536) are stripped and dropped before forwarding the packet to the application.

Values:

• 0x0(DISABLE): CRC stripping for Type packets is disabled
• 0x1(ENABLE): CRC stripping for Type packets is enabled

When this bit is set, the MAC strips the Pad or FCS field on the incoming packets only if the value of the length field is less than 1536 bytes. All received packets with length field greater than or equal to 1536 bytes are passed to the application without stripping the Pad or FCS field.

When this bit is reset, the MAC passes all incoming packets to the application, without any modification.

Values:

• 0x0(DISABLE): Automatic Pad or CRC Stripping is disabled
• 0x1(ENABLE): Automatic Pad or CRC Stripping is enabled

When this bit is set, the MAC disables the watchdog timer on the receiver. The MAC can receive packets of up to 16,383 bytes.

When this bit is reset, the MAC does not allow more than 2,048 bytes (10,240 if JE is set high) of the packet being received. The MAC cuts off any bytes received after 2,048 bytes.

Values:

• 0x0(ENABLE): Watchdog is enabled
• 0x1(DISABLE): Watchdog is disabled

When this bit is set, the MAC allows packet bursting during transmission in the GMII half-duplex mode.

Values:

• 0x0(DISABLE): Packet Burst is disabled
• 0x1(ENABLE): Packet Burst is enabled

When this bit is set, the MAC disables the jabber timer on the transmitter. The MAC can transfer packets of up to 16,383 bytes.

When this bit is reset, if the application sends more than 2,048 bytes of data (10,240 if JE is set high) during transmission, the MAC does not send rest of the bytes in that packet.

Values:

• 0x0(ENABLE): Jabber is enabled
• 0x1(DISABLE): Jabber is disabled

When this bit is set, the MAC allows jumbo packets of 9018 bytes (9022 bytes for VLAN tagged packets) without reporting a giant packet error in the Rx packet status.

Values:

• 0x0(DISABLE): Jumbo packet is disabled
• 0x1(ENABLE): Jumbo packet is enabled

This bit selects the Ethernet line speed. This bit, along with Bit14, selects the exact line speed. In the 10/100 Mbps-only (always 1) or 1000 Mbps-only (always 0) configurations, this bit is read-only (RO) with appropriate value. In default 10/100/1000 Mbps configurations, this bit is read-write (R/W). The mac_speed_o[1] signal reflects the value of this bit.

Values:

• 0x0(M_1000_2500M): For 1000 or 2500 Mbps operations
• 0x1(M_10_100M): For 10 or 100 Mbps operations

This bit selects the speed mode. The mac_speed_o[0] signal reflects the value of this bit.

Values:

• 0x0(M_10_1000M): 10 Mbps when PS bit is 1 and 1 Gbps when PS bit is 0
• 0x1(M_100_2500M): 100 Mbps when PS bit is 1 and 2.5 Gbps when PS bit is 0

When this bit is set, the MAC operates in the full-duplex mode in which it can transmit and receive simultaneously. This bit is RO with default value of 1'b1 in the full-duplex-only configurations.

Values:

• 0x0(HDUPLX): Half-duplex mode
• 0x1(FDUPLX): Full-duplex mode

When this bit is set, the MAC operates in the loopback mode at GMII or MII. The (G)MII Rx clock input (clk_rx_i) is required for the loopback to work properly. This is because the Tx clock is not internally looped back.

Values:

• 0x0(DISABLE): Loopback is disabled
• 0x1(ENABLE): Loopback is enabled

When this bit is set, the MAC transmitter checks the CRS signal before packet transmission in the full-duplex mode. The MAC starts the transmission only when the CRS signal is low. When this bit is reset, the MAC transmitter ignores the status of the CRS signal.

Values:

• 0x0(DISABLE): ECRSFD is disabled
• 0x1(ENABLE): ECRSFD is enabled

When this bit is set, the MAC disables the reception of packets when the gmii_txen_o is asserted in the half-duplex mode.

When this bit is reset, the MAC receives all packets given by the PHY.

This bit is not applicable in the full-duplex mode.

Values:

• 0x0(ENABLE): Enable Receive Own
• 0x1(DISABLE): Disable Receive Own

When this bit is set, the MAC transmitter ignores the (G) MII CRS signal during packet transmission in the half-duplex mode. As a result, no errors are generated because of Loss of Carrier or No Carrier during transmission.

When this bit is reset, the MAC transmitter generates errors because of Carrier Sense. The MAC can even abort the transmission.

Values:

• 0x0(ENABLE): Enable Carrier Sense During Transmission
• 0x1(DISABLE): Disable Carrier Sense During Transmission

When this bit is set, the MAC attempts only one transmission. When a collision occurs on the GMII or MII interface, the MAC ignores the current packet transmission and reports a Packet Abort with excessive collision error in the Tx packet status.

When this bit is reset, the MAC retries based on the settings of the BL field. This bit is applicable only in the half-duplex mode.

Values:

• 0x0(ENABLE): Enable Retry
• 0x1(DISABLE): Disable Retry

The back-off limit determines the random integer number (r) of slot time delays (4,096 bit times for 1000/2500 Mbps; 512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a collision. n = retransmission attempt.

The random integer takes the value in the range 0 <= r < 2^k

This bit is applicable only in the half-duplex mode.

Values:

• 0x0(MIN_N_10): k = min(n,10)
• 0x1(MIN_N_8): k = min(n,8)
• 0x2(MIN_N_4): k = min(n,4)
• 0x3(MIN_N_1): k = min(n,1)

When this bit is set, the deferral check function is enabled in the MAC. The MAC issues a Packet Abort status, along with the excessive deferral error bit set in the Tx packet status, when the Tx state machine is deferred for more than 24,288 bit times in 10 or 100 Mbps mode.

If the MAC is configured for 1000/2500 Mbps operation, the threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is ready to transmit, but it is prevented because of an active carrier sense signal (CRS) on GMII or MII.

The defer time is not cumulative. For example, if the transmitter defers for 10,000 bit times because the CRS signal is active and the CRS signal becomes inactive, the transmitter transmits and collision happens. Because of collision, the transmitter needs to back off and then defer again after back off completion. In such a scenario, the deferral timer is reset to 0, and it is restarted.

When this bit is reset, the deferral check function is disabled and the MAC defers until the CRS signal goes inactive.

This bit is applicable only in the half-duplex mode.

Values:

• 0x0(DISABLE): Deferral check function is disabled
• 0x1(ENABLE): Deferral check function is enabled

These bits control the number of preamble bytes that are added to the beginning of every Tx packet. The preamble reduction occurs only when the MAC is operating in the full-duplex mode.

Values:

• 0x0(M_7BYTES): 7 bytes of preamble
• 0x1(M_5BYTES): 5 bytes of preamble
• 0x2(M_3BYTES): 3 bytes of preamble
• 0x3(RESERVED): Reserved

When this bit is set, the Tx state machine of the MAC is enabled for transmission on the GMII or MII interface. When this bit is reset, the MAC Tx state machine is disabled after it completes the transmission of the current packet. The Tx state machine does not transmit any more packets.

Values:

• 0x0(DISABLE): Transmitter is disabled
• 0x1(ENABLE): Transmitter is enabled

When this bit is set, the Rx state machine of the MAC is enabled for receiving packets from the GMII or MII interface. When this bit is reset, the MAC Rx state machine is disabled after it completes the reception of the current packet. The Rx state machine does not receive any more packets from the GMII or MII interface.

Values:

• 0x0(DISABLE): Receiver is disabled
• 0x1(ENABLE): Receiver is enabled

When this is set then it is expected that all the incoming packets from the Line to have 4B Flexible Header in the Rx path (except for the pause and PFC packets). Similarly, in the Tx path all the packets from application are expected to have 4B Flexible header.

The position of the Flexible Header is always fixed at 12 bytes from the beginning of the packet (after MAC DA/SA).

Values:

• 0x0(DISABLE): Flexible Header is disabled
• 0x1(ENABLE): Flexible Header is enabled

When this bit is set, Packet for which Target Protocol Address does not match IPv4 address is dropped in the MTL layer.

When this bit is reset, when target Protocol Address does not match, packet is forwarded to MTL maintaining backward compatibility

Values:

• 0x0(DISABLE): mux select to drop the arp packet if target protocol address mismatches IPv4 address disabled
• 0x1(ENABLE): mux select to drop the arp packet if target protocol address mismatches IPv4 address enabled

When this bit is set, the MAC interprets EIPG field and IPG field in MAC_Configuration register together as minimum IPG greater than 96 bit times in steps of 8 bit times.

When this bit is reset, the MAC ignores EIPG field and interprets IPG field in MAC_Configuration register as minimum IPG less than or equal to 96 bit times in steps of 8 bit times.:

Values:

• 0x0(DISABLE): Extended Inter-Packet Gap is disabled
• 0x1(ENABLE): Extended Inter-Packet Gap is enabled

These bits indicate the maximum header size allowed for splitting the header data in the received packet.

Values:

• 0x0(M_64BYTES): Maximum Size for Splitting the Header Data is 64 bytes
• 0x1(M_128BYTES): Maximum Size for Splitting the Header Data is 128 bytes
• 0x2(M_256BYTES): Maximum Size for Splitting the Header Data is 256 bytes
• 0x3(M_512BYTES): Maximum Size for Splitting the Header Data is 512 bytes
• 0x4(M_1024BYTES): Maximum Size for Splitting the Header Data is 1024 bytes
• 0x5(RSVD): Reserved

When this bit is set, the received packet with Multicast/Broadcast Destination address is routed to multiple Receive DMA Channels.

Values:

• 0x0(DISABLE): Packet Duplication Control is disabled
• 0x1(ENABLE): Packet Duplication Control is enabled

When this bit is set, the MAC detects the Slow Protocol packets with unicast address of the station specified in the MAC_Address0_High and MAC_Address0_Low registers. The MAC also detects the Slow Protocol packets with the Slow Protocols multicast address (01-80-C2-00-00-02).

When this bit is reset, the MAC detects only Slow Protocol packets with the Slow Protocol multicast address specified in the IEEE 802.3-2015, Section 5.

Values:

• 0x0(DISABLE): Unicast Slow Protocol Packet Detection is disabled
• 0x1(ENABLE): Unicast Slow Protocol Packet Detection is enabled

When this bit is set, MAC processes the Slow Protocol packets (Ether Type 0x8809) and provides the Slow Protocol Sub-Type and Code fields in Rx status.

When this bit is reset, the MAC forwards all error-free Slow Protocol packets to the application. The MAC considers such packets as normal Type packets.

Values:

• 0x0(DISABLE): Slow Protocol Detection is disabled
• 0x1(ENABLE): Slow Protocol Detection is enabled

When this bit is set, the MAC receiver does not check the CRC field in the received packets. When this bit is reset, the MAC receiver always checks the CRC field in the received packets.

Values:

• 0x0(ENABLE): CRC Checking is enabled
• 0x1(DISABLE): CRC Checking is disabled

If the received packet size is greater than the value programmed in this field in units of bytes, the MAC declares the received packet as Giant packet. The value programmed in this field must be greater than or equal to 1518 bytes. Any other programmed value is considered as 1518 bytes.

For VLAN tagged packets, the MAC adds 4 bytes to the programmed value. When the Enable Double VLAN Processing option is selected, the MAC adds 8 bytes to the programmed value for double VLAN tagged packets. The value in this field is applicable when the GPSLCE bit is set in MAC_Configuration register.

When this bit is set, the MAC Receiver module passes all received packets to the application, irrespective of whether they pass the address filter or not. The result of the SA or DA filtering is updated (pass or fail) in the corresponding bit in the Rx Status Word.

When this bit is reset, the Receiver module passes only those packets to the application that passes the SA or DA address filter.

Values:

• 0x0(DISABLE): Receive All is disabled
• 0x1(ENABLE): Receive All is enabled

Drop Non-TCP/UDP over IP Packets

When this bit is set, the MAC drops the non-TCP or UDP over IP packets. The MAC forward only those packets that are processed by the Layer 4 filter. When this bit is reset, the MAC forwards all non-TCP or UDP over IP packets.

Values:

• 0x0(FWD): Forward Non-TCP/UDP over IP Packets
• 0x1(DROP): Drop Non-TCP/UDP over IP Packets

Layer 3and Layer 4 Filter Enable

When this bit is set, the MAC drops packets that do not match the enabled Layer 3 and Layer 4 filters. If Layer 3 or Layer 4 filters are not enabled for matching, this bit does not have any effect.

When this bit is reset, the MAC forwards all packets irrespective of the match status of the Layer 3 and Layer 4 fields.

Values:

• 0x0(DISABLE): Layer 3 and Layer 4 Filters are disabled
• 0x1(ENABLE): Layer 3 and Layer 4 Filters are enabled

When this bit is set, the MAC drops the VLAN tagged packets that do not match the VLAN Tag. When this bit is reset, the MAC forwards all packets irrespective of the match status of the VLAN Tag.

Values:

• 0x0(DISABLE): VLAN Tag Filter is disabled
• 0x1(ENABLE): VLAN Tag Filter is enabled

When this bit is set, the address filter passes a packet if it matches either the perfect filtering or hash filtering as set by the HMC or HUC bit.

When this bit is reset and the HUC or HMC bit is set, the packet is passed only if it matches the Hash filter.

Values:

• 0x0(DISABLE): Hash or Perfect Filter is disabled
• 0x1(ENABLE): Hash or Perfect Filter is enabled

When this bit is set, the MAC compares the SA field of the received packets with the values programmed in the enabled SA registers. If the comparison fails, the MAC drops the packet.

When this bit is reset, the MAC forwards the received packet to the application with updated SAF bit of the Rx Status depending on the SA address comparison.

Values:

• 0x0(DISABLE): SA Filtering is disabled
• 0x1(ENABLE): SA Filtering is enabled

When this bit is set, the Address Check block operates in the inverse filtering mode for SA address comparison. If the SA of a packet matches the values programmed in the SA registers, it is marked as failing the SA Address filter.

When this bit is reset, if the SA of a packet does not match the values programmed in the SA registers, it is marked as failing the SA Address filter.

Values:

• 0x0(DISABLE): SA Inverse Filtering is disabled
• 0x1(ENABLE): SA Inverse Filtering is enabled

These bits control the forwarding of all control packets (including unicast and multicast Pause packets).

Values:

• 0x0(FLTR_ALL): MAC filters all control packets from reaching the application
• 0x1(FW_XCPT_PAU): MAC forwards all control packets except Pause packets to the application even if they fail the Address filter
• 0x2(FW_ALL): MAC forwards all control packets to the application even if they fail the Address filter
• 0x3(FW_PASS): MAC forwards the control packets that pass the Address filter

When this bit is set, the AFM module blocks all the incoming broadcast packets. In addition, it overrides all other filter settings.

When this bit is reset, the AFM module passes all received broadcast packets.

Values:

• 0x0(ENABLE): Enable Broadcast Packets
• 0x1(DISABLE): Disable Broadcast Packets

When this bit is set, it indicates that all the received packets with a multicast destination address (first bit in the destination address field is "1") are passed. When this bit is reset, filtering of multicast packet depends on HMC bit.

Values:

• 0x0(DISABLE): Pass All Multicast is disabled
• 0x1(ENABLE): Pass All Multicast is enabled

DA Inverse Filtering

When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast packets. When this bit is reset, normal filtering of packets is performed.

Values:

• 0x0(DISABLE): DA Inverse Filtering is disabled
• 0x1(ENABLE): DA Inverse Filtering is enabled

Hash Multicast

When this bit is set, the MAC performs the destination address filtering of received multicast packets according to the hash table.

When this bit is reset, the MAC performs the perfect destination address filtering for multicast packets, that is, it compares the DA field with the values programmed in DA registers.

Values:

• 0x0(DISABLE): Hash Multicast is disabled
• 0x1(ENABLE): Hash Multicast is enabled

When this bit is set, the MAC performs the destination address filtering of unicast packets according to the hash table.

When this bit is reset, the MAC performs a perfect destination address filtering for unicast packets, that is, it compares the DA field with the values programmed in DA registers.

Values:

• 0x0(DISABLE): Hash Unicast is disabled
• 0x1(ENABLE): Hash Unicast is enabled

Promiscuous Mode

When this bit is set, the Address Filtering module passes all incoming packets irrespective of the destination or source address. The SA or DA Filter Fails status bits of the Rx Status Word are always cleared when PR is set.

Values:

• 0x0(DISABLE): Promiscuous Mode is disabled
• 0x1(ENABLE): Promiscuous Mode is enabled

When this bit is set and the WD bit of the MAC_Configuration register is reset, the WTO field is used as watchdog timeout for a received packet. When this bit is cleared, the watchdog timeout for a received packet is controlled by setting of WD and JE bits in MAC_Configuration register.

Values:

• 0x0(DISABLE): Programmable Watchdog is disabled
• 0x1(ENABLE): Programmable Watchdog is enabled

Watchdog Timeout

When the PWE bit is set and the WD bit of the MAC_Configuration register is reset, this field is used as watchdog timeout for a received packet. If the length of a received packet exceeds the value of this field, such packet is terminated and declared as an error packet.

Values:

• 0x0(M_2KBYTES): 2 KB
• 0x1(M_3KBYTES): 3 KB
• 0x2(M_4KBYTES): 4 KB
• 0x3(M_5KBYTES): 5 KB
• 0x4(M_6KBYTES): 6 KB
• 0x5(M_7KBYTES): 7 KB
• 0x6(M_8KBYTES): 8 KB
• 0x7(M_9KBYTES): 9 KB
• 0x8(M_10KBYTES): 10 KB
• 0x9(M_11KBYTES): 11 KB
• 0xa(M_12KBYTES): 12 KB
• 0xb(M_13KBYTES): 13 KB
• 0xc(M_14KBYTES): 14 KB
• 0xd(M_15KBYTES): 15 KB
• 0xe(M_16383BYTES): 16383 Bytes
• 0xf(RESERVED): Reserved

This field contains the first 32 Bits[0:31] of the Hash table.

This field contains the second 32Bits [63:32] of the Hash table.

This field contains the third 32Bits [95:64] of the Hash table.

This field contains the fourth 32 Bits[127:96] of the Hash table.

This field contains the fifth 32 Bits [159:128] of the Hash table.

This field contains the sixth 32 Bits[191:160] of the Hash table.

This field contains the seventh 32 Bits [223:192] of the Hash table.

This field contains the eighth 32 Bits [255:224] of the Hash table.

When this bit is set, the MAC provides the inner VLAN Tag in the Rx status. When this bit is reset, the MAC does not provide the inner VLAN Tag in Rx status.

Values:

• 0x0(DISABLE): Inner VLAN Tag in Rx status is disabled
• 0x1(ENABLE): Inner VLAN Tag in Rx status is enabled

This field indicates the stripping operation on inner VLANTag in received packet.

Values:

• 0x0(DONOT): Do not strip
• 0x1(IFPASS): Strip if VLAN filter passes
• 0x2(IFFAIL): Strip if VLAN filter fails
• 0x3(ALWAYS): Always strip

When this bit, VTHMbit and the EDVLP field are set, the MAC receiver enables VLAN Hash filtering operation on the inner VLAN Tag (if present).

When this bit is reset and VTHM bit is set, the MAC receiver enables VLAN Hash filtering operation on the outer VLAN Tag (if present).

The ERSVLM bit and DOVLTC bit determines which VLAN type is enabled for filtering.

Values:

• 0x0(DISABLE): Inner VLAN tag is disabled
• 0x1(ENABLE): Inner VLAN tag is enabled

When this bit is set, the MAC enables processing of up to two VLAN Tags on Tx and Rx (if present). When this bit is reset, the MAC enables processing of up to one VLAN Tag on Tx and Rx (if present).

Values:

• 0x0(DISABLE): Double VLAN Processing is disabled
• 0x1(ENABLE): Double VLAN Processing is enabled

VLAN Tag Hash Table Match Enable

When this bit is set, the most significant four bits of CRC of VLAN Tag are used to index the content of the MAC_VLAN_Hash_Table register. A value of 1 in the VLAN Hash Table register, corresponding to the index, indicates that the packet matched the VLAN hash table.

When the ETVbit is set, the CRC of the 12-bit VLAN Identifier (VID) is used for comparison. When the ETV bit is reset, the CRC of the 16-bit VLAN tag is used for comparison.

When this bit is reset, the VLAN Hash Match operation is not performed.

Values:

• 0x0(DISABLE): VLAN Tag Hash Table Match is disabled
• 0x1(ENABLE): VLAN Tag Hash Table Match is enabled

When this bit is set, MAC provides the outer VLAN Tag in the Rx status. When this bit is reset, the MAC does not provide the outer VLAN Tag in Rx status.

Values:

• 0x0(DISABLE): VLAN Tag in Rx status is disabled
• 0x1(ENABLE): VLAN Tag in Rx status is enabled

This field indicates the stripping operation on the outer VLAN Tag in received packet.

Values:

• 0x0(DONOT): Do not strip
• 0x1(IFPASS): Strip if VLAN filter passes
• 0x2(IFFAIL): Strip if VLAN filter fails
• 0x3(ALWAYS): Always strip

When this bit is set, the MAC VLAN Hash Filter does not check whether the VLAN Tag specified by the ERIVLT bit is of type S-VLAN or C-VLAN.

When this bit is reset, the MAC VLAN Hash Filter filters or matches the VLAN Tag specified by the ERIVLT bit only when VLAN Tag type is similar to the one specified by the ERSVLM bit.

Values:

• 0x0(ENABLE): VLAN Type Check is enabled
• 0x1(DISABLE): VLAN Type Check is disabled

Enable Receive S-VLAN Match for VLAN Hash Filtering When this bit is set, the MAC receiver enables VLAN Hash filtering or matching for S-VLAN (Type = 0x88A8) packets. When this bit is reset, the MAC receiver enables VLAN Hash filtering or matching for C-VLAN (Type = 0x8100) packets.

The ERIVLT bit determines the VLAN tag position considered for VLAN Hash filtering or matching.

Values:

• 0x0(DISABLE): Receive S-VLAN Match is disabled
• 0x1(ENABLE): Receive S-VLAN Match is enabled

When this bit is set, the MAC transmitter and receiver consider the S-VLAN packets (Type = 0x88A8) as valid VLAN tagged packets.

Values:

• 0x0(DISABLE): S-VLAN is disabled
• 0x1(ENABLE): S-VLAN is enabled

When this bit is set, this bit enables the VLAN Tag inverse matching. The packets without matching VLAN Tag are marked as matched. When reset, this bit enables the VLAN Tag perfect matching. The packets with matched VLAN Tag are marked as matched.

Values:

• 0x0(DISABLE): VLAN Tag Inverse Match is disabled
• 0x1(ENABLE): VLAN Tag Inverse Match is enabled

Enable 12-Bit VLAN Tag Comparison for VLAN Hash Filtering When this bit is set, a 12-bit VLAN identifier is used for VLAN Hash filtering instead of the complete 16-bit VLAN tag.

Bits[0:11] of VLAN tag in the received VLAN-tagged packet are used for hash-based VLAN filtering.

When this bit is reset, all 16 bits of the 15th and 16th bytes of the received VLAN packet are used for VLAN hash filtering.

Values:

• 0x0(DISABLE): 12-Bit VLAN Tag Comparison is disabled
• 0x1(ENABLE): 12-Bit VLAN Tag Comparison is enabled

This field holds the address offset of the MACVLAN Tag Filter Register which the application is trying to access.

The width of the field depends on the number of MAC VLAN Tag Registers enabled.

This bit indicates if the current register access is a read or a write.

When set, it indicate are ad operation. When reset, it indicates a write operation.

Values:

• 0x0(WRITE): Write operation
• 0x1(READ): Read operation

This bit is set along with a read or write command for initiating the indirect access to per VLAN Tag Filter register. This bit is reset when the read or write command to per VLAN Tag Filter indirect access register is complete. The next indirect register access can be initiated only after this bit is reset.

During a write operation, the bit is reset only after the data has been written into the Per VLAN Tag register.

During a read operation, the data should be read from the MAC_VLAN_Tag_Data register only after this bit is reset.

Values:

• 0x0(DISABLE): Operation Busy is disabled
• 0x1(ENABLE): Operation Busy is enabled

When this bit is set, the MAC provides the inner VLAN Tag in the Rx status. When this bit is reset, the MAC does not provide the inner VLAN Tag in Rx status.

Values:

• 0x0(DISABLE): Inner VLAN Tag in Rx status is disabled
• 0x1(ENABLE): Inner VLAN Tag in Rx status is enabled

This field indicates the stripping operation on inner VLAN Tag in received packet.

Values:

• 0x0(DONOT): Do not strip
• 0x1(IFPASS): Strip if VLAN filter passes
• 0x2(IFFAIL): Strip if VLAN filter fails
• 0x3(ALWAYS): Always strip

When this bit and the EDVLP field are set, the MAC receiver enables operation on the inner VLAN Tag (if present). When this bit is reset, the MAC receiver enables operation on the outer VLAN Tag (if present). The ERSVLM bit determines which VLAN type is enabled for filtering or matching.

Values:

• 0x0(DISABLE): Inner VLAN tag is disabled
• 0x1(ENABLE): Inner VLAN tag is enabled

Enable Double VLAN Processing

When this bit is set, the MAC enables processing of up to two VLAN Tags on Tx and Rx (if present). When this bit is reset, the MAC enables processing of up to one VLAN Tag on Tx and Rx (if present).

Values:

• 0x0(DISABLE): Double VLAN Processing is disabled
• 0x1(ENABLE): Double VLAN Processing is enabled

When this bit is set, the most significant four bits of CRC of VLAN Tag are used to index the content of the MAC_VLAN_Hash_Table register. A value of 1 in the VLAN Hash Table register, corresponding to the index, indicates that the packet matched the VLAN hash table.

When the ETVbit is set, the CRC of the 12-bit VLAN Identifier (VID) is used for comparison. When the ETV bit is reset, the CRC of the 16-bit VLAN tag is used for comparison.

When this bit is reset, the VLAN Hash Match operation is not performed.

Values:

• 0x0(DISABLE): VLAN Tag Hash Table Match is disabled
• 0x1(ENABLE): VLAN Tag Hash Table Match is enabled

Enable VLAN Tag in Rx status

When this bit is set, MAC provides the outer VLAN Tag in the Rx status. When this bit is reset, the MAC does not provide the outer VLAN Tag in Rx status.

Values:

• 0x0(DISABLE): VLAN Tag in Rx status is disabled
• 0x1(ENABLE): VLAN Tag in Rx status is enabled

This field indicates the stripping operation on the outer VLAN Tag in received packet.

Values:

• 0x0(DONOT): Do not strip
• 0x1(IFPASS): Strip if VLAN filter passes
• 0x2(IFFAIL): Strip if VLAN filter fails
• 0x3(ALWAYS): Always strip

Disable VLAN Type Check

When this bit is set, the MAC does not check whether the VLAN Tag specified by the ERIVLT bit is of type S-VLAN or C-VLAN.

When this bit is reset, the MAC filters or matches the VLAN Tag specified by the ERIVLT bit only when VLAN Tag type is similar to the one specified by the ERSVLM bit. The VLAN filter is bypassed when VLAN Type of received packet do not match the programmed VLAN Type in the VLAN filter.

Values:

• 0x0(ENABLE): VLAN Type Check is enabled
• 0x1(DISABLE): VLAN Type Check is disabled

Enable Receive S-VLAN Match

When this bit is set, the MAC receiver enables filtering or matching for S-VLAN (Type = 0x88A8) packets. When this bit is reset, the MAC receiver enables filtering or matching for C-VLAN (Type =0x8100) packets.

The ERIVLT bit determines the VLAN tag position considered for filtering or matching.

Values:

• 0x0(DISABLE): Receive S-VLAN Match is disabled
• 0x1(ENABLE): Receive S-VLAN Match is enabled

Enable S-VLAN

When this bit is set, the MAC transmitter and receiver consider the S-VLAN packets (Type = 0x88A8) as valid VLAN tagged packets.

Values:

• 0x0(DISABLE): S-VLAN is disabled
• 0x1(ENABLE): S-VLAN is enabled

When this bit is set, this bit enables the VLAN Tag inverse matching. The packets without matching VLAN Tag are marked as matched. When reset, this bit enables the VLAN Tag perfect matching. The packets with matched VLAN Tag are marked as matched.

Values:

• 0x0(DISABLE): VLAN Tag Inverse Match is disabled
• 0x1(ENABLE): VLAN Tag Inverse Match is enabled

When this bit is set, a 12-bit VLAN identifier is used for comparing and filtering instead of the complete 16-bit VLAN tag. Bits[0:11] of VLAN tag are compared with the corresponding field in the received VLAN-tagged packet.

Similarly, when enabled, only 12bits of the VLAN tag in the received packet are used for hash-based VLAN filtering.

When this bit is reset, all 16 bits of the 15th and 16th bytes of the received VLAN packet are used for comparison and VLAN hash filtering.

Values:

• 0x0(DISABLE): 12-Bit VLAN Tag Comparison is disabled
• 0x1(ENABLE): 12-Bit VLAN Tag Comparison is enabled

This field contains the 802.1Q VLAN tag to identify the VLAN packets. This VLAN tag identifier is compared to the 15th and 16th bytes of the packets being received for VLAN packets. The following list describes the bits of this field:

• Bits[15:13]: User Priority
• Bit12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI)
• Bits[0:11]: VLAN Identifier (VID) field of VLAN tag

When the ETV bit is set, only the VID is used for comparison. If this field ([0:11] if ETV is set) is all zeros, the MAC does not check the 15th and 16th bytes for VLAN tag comparison and declares all packets with Type field value of 0x8100 or 0x88a8 as VLAN packets.

The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field.

If the Routing based on VLAN Tag Filter is not necessary, this field need not be programmed.

This bit is the Enable for the DMA Channel Number value programmed in the field DMACH.

When this bit is reset, the Routing does not occur based on VLAN Filter result. The frame is routed based on DA Based DMA Channel Routing.

Values:

• 0x0(DISABLE): DMA Channel Number is disabled
• 0x1(ENABLE): DMA Channel Number is enabled

This bit is valid only when Double VLAN Tag Enable of the Filter is set.

When this bit and the EDVLP field are set, the MAC receiver enables operation on the inner VLAN Tag (if present).

When this bit is reset, the MAC receiver enables operation on the outer VLAN Tag (if present).

Values:

• 0x0(DISABLE): Inner VLAN tag comparison is disabled
• 0x1(ENABLE): Inner VLAN tag comparison is enabled

This bit is valid only when VLAN Tag Enable of the Filter is set. When this bit is set, the MAC receiver enables filtering or matching for S-VLAN (Type = 0x88A8) packets.

When this bit is reset, the MAC receiver enables filtering or matching for C-VLAN (Type = 0x8100) packets.

Values:

• 0x0(DISABLE): Receive S-VLAN Match is disabled
• 0x1(ENABLE): Receive S-VLAN Match is enabled

This bit is valid only when VLAN Tag Enable of the Filter is set. When this bit is set, the MAC does not check whether the VLAN Tag specified by the Enable Inner VLAN Tag Comparison bit is of type S-VLAN or C-VLAN.

When this bit is reset, the MAC filters or matches the VLAN Tag specified by the Enable Inner VLAN Tag Comparison bit only when VLAN Tag type is similar to the one specified by the Enable S-VLAN Match for received Frames bit.

Values:

• 0x0(ENABLE): VLAN type comparison is enabled
• 0x1(DISABLE): VLAN type comparison is disabled

This bit is valid only when VEN of the Filter is set.

When this bit is set, a 12-bit VLAN identifier is used for comparing and filtering instead of the complete 16-bit VLAN tag. Bits [0:11] of VLAN tag are compared with the corresponding field in the received VLAN-tagged packet.

Values:

• 0x0(M_16BIT): 16 bit VLAN comparison
• 0x1(M_12BIT): 12 bit VLAN comparison

This bit is used to enable or disable the VLAN Tag. When this bit is set, the MAC compares the VLAN Tag of received packet with the VLAN Tag ID.

When this bit is reset, no comparison is performed irrespective of the programming of the other fields.

Values:

• 0x0(DISABLE): VLAN Tag is disabled
• 0x1(ENABLE): VLAN Tag is enabled

This field holds the VLAN Tag value which is used by the MAC for perfect comparison. It is valid when VLAN Tag Enable is set.

This field contains the 16-bit VLAN Hash Table.

This bit indicates the status of the read/write operation of indirect access to the queue/channel specific VLAN inclusion register.

For write operation, write to a register is complete when this bit is reset. For read operation the read data is valid when the bit is reset.

The application must make sure that this bit is reset before attempting subsequent access to this register.

Values:

• 0x0(INACTIVE): Busy status not detected
• 0x1(ACTIVE): Busy status detected

Testable: untestable

This bit controls the read or write operation for indirectly accessing the queue/channel specific VLAN Inclusion register. When set indicates write operation and when reset indicates read operation.

This does not have any effect when CBTI is reset.

Values:

• 0x0(READ): Read operation of indirect access
• 0x1(WRITE): Write operation of indirect access

This field selects one of the queue/channel specific VLAN Inclusion register for read/write access.

This does not have any effect when CBTI is reset.

When this bit is set,outer VLAN tag is inserted for every packets transmitted by the MAC. The tag value is taken from the queue/channel specific VLAN tag register. The VLTI, VLP, VLC, and VLT fields of this register are ignored when this bit is set.

When this bit is set, a write operation to byte 3 of this register initiates the read/write access to the indirect register.

When reset, outer VLAN operation is based on the setting of VLTI, VLP, VLC and VLT fields of this register.

Values:

• 0x0(DISABLE): Channel based tag insertion is disabled
• 0x1(ENABLE): Channel based tag insertion is enabled

VLAN Tag Input

When this bit is set, it indicates that the VLAN tag to be inserted or replaced in Tx packet should be taken from the following:

• The mti_vlan_tag_i signal in EQOS-CORE configurations
• The control word in EQOS-MTL configurations
• The Tx descriptor in EQOS-AHB, EQOS-AXI, or EQOS-DMA configurations

Values:

• 0x0(DISABLE): VLAN Tag Input is disabled
• 0x1(ENABLE): VLAN Tag Input is enabled

When this bit is set, S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted packets. When this bit is reset, C-VLAN type (0x8100) is inserted or replaced in the 13th and 14th bytes of transmitted packets.

Values:

• 0x0(C-VLAN): C-VLAN type (0x8100) is inserted or replaced
• 0x1(S-VLAN): S-VLAN type (0x88A8) is inserted or replaced

When this bit is set, the control bits[17:16] are used for VLAN deletion, insertion, or replacement. When this bit is reset, the mti_vlan_ctrl_i control input is used and bits[17:16] are ignored.

Values:

• 0x0(DISABLE): VLAN Priority Control is disabled
• 0x1(ENABLE): VLAN Priority Control is enabled

• 2'b00: No VLAN tag deletion, insertion, or replacement
• 2'b01: VLAN tag deletion

The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag (bytes 15 and 16) of all transmitted packets with VLAN tags.

• 2'b10: VLAN tag insertion

The MAC inserts VLT in bytes 15 and 16 of the packet after inserting the Type value (0x8100 or 0x88a8) in bytes 13 and

14. This operation is performed on all transmitted packets, irrespective of whether they already have a VLAN tag.

• 2'b11: VLAN tag replacement

The MAC replaces VLT in bytes 15 and 16 of all VLAN-type transmitted packets (Bytes 13 and 14 are 0x8100 or 0x88a8).

Values:

• 0x0(NONE): No VLAN tag deletion, insertion, or replace- ment
• 0x1(DELETE): VLAN tag deletion
• 0x2(INSERT): VLAN tag insertion
• 0x3(REPLACE): VLAN tag replacement

This field contains the value of the VLAN tag to be inserted or replaced. The value must only be changed when the transmit lines are inactive or during the initialization phase.

Bits[15:13] are the User Priority field, Bit12 is the CFI/DEI field, and Bits[0:11] are the VID field in the VLAN tag.

The following list describes the bits of this field:

• Bits[15:13]: User Priority
• Bit12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI)
• Bits[0:11]: VLAN Identifier (VID) field of VLAN tag

When this bit is set, it indicates that the VLAN tag to be inserted or replaced in Tx packet should be taken from the following:

• The mti_vlan_tag_i signal in EQOS-CORE configurations
• The control word in EQOS-MTL configurations
• The Tx descriptor in EQOS-AHB, EQOS-AXI, or EQOS-DMA configurations

Values:

• 0x0(DISABLE): VLAN Tag Input is disabled
• 0x1(ENABLE): VLAN Tag Input is enabled

When this bit is set, S-VLAN type (0x88A8) is inserted or replaced in the 17th and 18th bytes of transmitted packets. When this bit is reset, C-VLAN type (0x8100) is inserted or replaced in the 17th and 18th bytes of transmitted packets.

Values:

• 0x0(C-VLAN): C-VLAN type (0x8100) is inserted
• 0x1(S-VLAN): S-VLAN type (0x88A8) is inserted

When this bit is set, the VLC field is used for VLAN deletion, insertion, or replacement. When this bit is reset, the mti_vlan_ctrl_i control input is used and the VLC field is ignored.

Values:

• 0x0(DISABLE): VLAN Priority Control is disabled
• 0x1(ENABLE): VLAN Priority Control is enabled

• 2'b00: No VLAN tag deletion, insertion, or replacement
• 2'b01: VLAN tag deletion

The MAC removes the VLAN type (bytes 17 and 18) and VLAN tag (bytes 19 and 20) of all transmitted packets with VLAN tags.

• 2'b10: VLAN tag insertion

The MAC inserts VLT in bytes 19 and 20 of the packet after inserting the Type value (0x8100 or 0x88a8) in bytes 17 and 18. This operation is performed on all transmitted packets, irrespective of whether they already have a VLAN tag.

• 2'b11: VLAN tag replacement

The MAC replaces VLT in bytes 19 and 20 of all VLAN-type transmitted packets (Bytes 17 and 18 are 0x8100 or 0x88a8).

Values:

• 0x0(NONE): No VLAN tag deletion, insertion, or replacement
• 0x1(DELETE): VLAN tag deletion
• 0x2(INSERT): VLAN tag insertion
• 0x3(REPLACE): VLAN tag replacement

This field contains the value of the VLAN tag to be inserted or replaced. The value must only be changed when the transmit lines are inactive or during the initialization phase.

Bits[15:13] are the User Priority field, Bit12 is the CFI/DEI field, and Bits[0:11] are the VID field in the VLAN tag.

The following list describes the bits of this field:

• Bits[15:13]: User Priority
• Bit12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI)
• Bits[0:11]: VLAN Identifier (VID) field of VLAN tag

Pause Time

This field holds the value to be used in the Pause Time field in the Tx control packet. If the Pause Time bits are configured to be double-synchronized to the (G)MII clock domain, consecutive writes to this register should be performed only after at least four clock cycles in the destination clock domain.

Disable Zero-Quanta Pause

When this bit is set, it disables the automatic generation of the zero-quanta Pause packets on de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i or mti_flowctrl_i).

When this bit is reset, normal operation with automatic zero-quanta Pause packet generation is enabled.

Values:

• 0x0(ENABLE): Zero-Quanta Pause packet generation is enabled
• 0x1(DISABLE): Zero-Quanta Pause packet generation is disabled

This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause packet.

The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example, if PT = 100H (256 slot times), and PLT = 001, a second Pause packet is automatically transmitted if the mti_flowctrl_i signal is asserted at 228 (256-28) slot times after the first Pause packet is transmitted.

The following list provides the threshold values for different values. The slot time is defined as the time taken to transmit 512 bits (64 bytes) on the GMII or MII interface.

This (approximate) computation is based on the packet size (6415182000901816384, or 32768) + 2 Pause Packet

Size+ IPG in Slot Times.

Values:

• 0x0(PT4): Pause Time minus 4 Slot Times (PT -4 slot times)
• 0x1(PT28): Pause Time minus 28 Slot Times (PT -28 slot times)
• 0x2(PT36): Pause Time minus 36 Slot Times (PT -36 slot times)
• 0x3(PT144): Pause Time minus 144 Slot Times (PT -144 slot times)
• 0x4(PT256): Pause Time minus 256 Slot Times (PT -256 slot times)
• 0x5(PT512): Pause Time minus 512 Slot Times (PT -512 slot times)
• 0x6(RSVD): Reserved

Full-Duplex Mode:

In the full-duplex mode, when this bit is set, the MAC enables the flow control operation to Tx Pause packets. When this bit is reset, the flow control operation in the MAC is disabled, and the MAC does not transmit any Pause packets.

Half-Duplex Mode:

In the half-duplex mode, when this bit is set, the MAC enables the back pressure operation. When this bit is reset, the back pressure feature is disabled.

Values:

• 0x0(DISABLE): Transmit Flow Control is disabled
• 0x1(ENABLE): Transmit Flow Control is enabled

This bit initiates a Pause packet in the full-duplex mode and activates the back pressure function in the half-duplex mode if the TFE bit is set.

Full-Duplex Mode:

In the full-duplex mode, this bit should be read as 1'b0 before writing to this register. To initiate a Pause packet, the application must set this bit to 1'b1. During Control packet transfer, this bit continues to be set to indicate that a packet transmission is in progress. When Pause packet transmission is complete, the MAC resets this bit to 1'b0. You should not write to this register until this bit is cleared.

Half-Duplex Mode:

When this bit is set (and TFE bit is set) in the half-duplex mode, the MAC asserts the backpressure. During backpressure, when the MAC receives a new packet, the transmitter starts sending a JAM pattern resulting in a collision. This control register bit is logically ORed with the mti_flowctrl_i input signal for the backpressure function. When the MAC is configured for the full-duplex mode, the BPA is automatically disabled.

Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect.

Values:

• 0x0(DISABLE): Flow Control Busy or Back pressure Activate is disabled
• 0x1(ENABLE): Flow Control Busy or Back pressure Activate is enabled

Testable: untestable

When this bit is set, it enables generation and reception of priority-based flow control (PFC) packets. When this bit is reset, it enables generation and reception of 802.3x Pause control packets.

Values:

• 0x0(DISABLE): Priority Based Flow Control is disabled
• 0x1(ENABLE): Priority Based Flow Control is enabled

A pause packet is processed when it has the unique multicast address specified in the IEEE 802.3. When this bit is set, the MAC can also detect Pause packets with unicast address of the station. This unicast address should be as specified in MAC_Address0_High and MAC_Address0_Low.

When this bit is reset, the MAC only detects Pause packets with unique multicast address.

Values:

• 0x0(DISABLE): Unicast Pause Packet Detect disabled
• 0x1(ENABLE): Unicast Pause Packet Detect enabled

When this bit is set and the MAC is operating in full-duplex mode, the MAC decodes the received Pause packet and disables its transmitter for a specified (Pause) time. When this bit is reset or the MAC is operating in half-duplex mode, the decode function of the Pause packet is disabled.

When PFC is enabled, flow control is enabled for PFC packets. The MAC decodes the received PFC packet and disables the Transmit queue, with matching priorities, for a duration of received Pause time.

Values:

• 0x0(DISABLE): Receive Flow Control is disabled
• 0x1(ENABLE): Receive Flow Control is enabled

This field holds the Rx queue number to which the tagged packets failing the Destination or Source Address filter (and UFFQE/MFFQE not enabled) or failing the VLAN tag filter must be routed to. This field is valid only when the VFFQE bit is set.

When this bit is set, the tagged packets which fail the Destination or Source address filter or fail the VLAN tag filter, are routed to the Rx Queue Number programmed in the VFFQ. When this bit is reset, the tagged packets which fail the Destination or Source address filter or fail the VLAN tag filter are routed based on other routing options. This bit is valid only when the RA bit of the MAC_Packet_Filter register is set.

Values:

• 0x0(DISABLE): VLAN tag Filter Fail Packets Queuing is disabled
• 0x1(ENABLE): VLAN tag Filter Fail Packets Queuing is enabled

This field holds the Rx queue number to which the Multicast packets failing the Destination or Source Address filter are routed to. This field is valid only when the MFFQE bit is set.

When this bit is set, the multicast packets which fail the Destination or Source address filter are routed to the Rx Queue Number programmed in the MFFQ.

When this bit is reset, the Multicast packets which fail the Destination or Source address filter is routed based on other routing options. This bit is valid only when the RA bit of the MAC_Packet_Filter register is set.

Values:

• 0x0(DISABLE): Multicast Address Filter Fail Packets Queuing is disabled
• 0x1(ENABLE): Multicast Address Filter Fail Packets Queuing is enabled

This field holds the Rx queue number to which the Unicast packets failing the Destination or Source Address filter are routed to. This field is valid only when the UFFQE bit is set.

Destination or Source address filter is routed to the Rx Queue Number programmed in the UFFQ. When this bit is reset, the Unicast packets which fail the Destination or Source address filter is routed based on other routing options. This bit is valid only when the RA bit of the MAC_Packet_Filter register is set.

Values:

• 0x0(DISABLE): Unicast Address Filter Fail Packets Queuing is disabled
• 0x1(ENABLE): Unicast Address Filter Fail Packets Queuing is enabled

Priorities Selected in Transmit Queue 3

Priorities Selected in Transmit Queue 2

Priorities Selected in Transmit Queue 1

This field holds the priorities assigned to Tx Queue 0 by the software. This field determines if Tx Queue 0 should be blocked from transmitting specified pause time when a PFC packet is received with priorities matching the priorities programmed in this field.

If the content of this field is not mutually exclusive to the corresponding fields of other Transmit queues, that is, same priority is mapped to multiple Tx queues, the MAC blocks all queues with matching priority, for the specified time.

This field holds the priorities assigned to Tx Queue 4 by the software. This field determines if Tx Queue 4 should be blocked from transmitting specified pause time when a PFC packet is received with priorities matching the priorities programmed in this field.

If the content of this field is not mutually exclusive to corresponding fields of other Transmit queues, that is, same priority is mapped to multiple Tx queues, the MAC blocks all queues with matching priority for specified time.

This field is similar to the RXQ0EN field.

Values:

• 0x0(DISABLE): Queue not enabled
• 0x1(EN_AV): Queue enabled for AV
• 0x2(EN_DCB_GEN): Queue enabled for DCB/Generic
• 0x3(RSVD): Reserved

This field is similar to the RXQ0EN field.

Values:

• 0x0(DISABLE): Queue not enabled
• 0x1(EN_AV): Queue enabled for AV
• 0x2(EN_DCB_GEN): Queue enabled for DCB/Generic
• 0x3(RSVD): Reserved

This field is similar to the RXQ0EN field.

Values:

• 0x0(DISABLE): Queue not enabled
• 0x1(EN_AV): Queue enabled for AV
• 0x2(EN_DCB_GEN): Queue enabled for DCB/Generic
• 0x3(RSVD): Reserved

This field is similar to the RXQ0EN field.

Values:

• 0x0(DISABLE): Queue not enabled
• 0x1(EN_AV): Queue enabled for AV
• 0x2(EN_DCB_GEN): Queue enabled for DCB/Generic
• 0x3(RSVD): Reserved

This field is similar to the RXQ0EN field.

Values:

• 0x0(DISABLE): Queue not enabled
• 0x1(EN_AV): Queue enabled for AV
• 0x2(EN_DCB_GEN): Queue enabled for DCB/Generic
• 0x3(RSVD): Reserved

This field is similar to the RXQ0EN field.

Values:

• 0x0(DISABLE): Queue not enabled
• 0x1(EN_AV): Queue enabled for AV
• 0x2(EN_DCB_GEN): Queue enabled for DCB/Generic
• 0x3(RSVD): Reserved

This field is similar to the RXQ0EN field.

Values:

• 0x0(DISABLE): Queue not enabled
• 0x1(EN_AV): Queue enabled for AV
• 0x2(EN_DCB_GEN): Queue enabled for DCB/Generic
• 0x3(RSVD): Reserved

This field indicates whether Rx Queue 0 is enabled for AV or DCB.

Values:

• 0x0(DISABLE): Queue not enabled
• 0x1(EN_AV): Queue enabled for AV
• 0x2(EN_DCB_GEN): Queue enabled for DCB/Generic
• 0x3(RSVD): Reserved

When this bit is set, it enables Type Field based Rx Queuing where the Type field of received packet is compared with programmed TYP field in MAC_TMRQ_Regs(#i) and if a match occurs the packet is routed to the corresponding TMRQ field.

• 1: Priority of MCBCQ is reduced and the received packet is first routed to PTPQ, AVCPQ, DCBCPQ depending on packet type.
• 0: Received Multicast/Broadcast packet is routed to MCBCQ.

Values:

• 0x0(DISABLE): Overriding MCBCQ priority disabled
• 0x1(ENABLE): Overriding MCBCQ priority enabled

This field holds the Rx queue number to which the residual preemption frames must be forwarded. Preemption frames that are tagged and pass the SA/DA/VLAN filtering are routed based on PSRQ and all other frames are treated as residual frames and is routed to the queue number mentioned in this field. The Queue-0 is used as a default queue for express frames, so this field cannot be programmed to a value 0.

• 2'b00: VLAN Tagged PTPoE packets are routed as generic VLAN Tagged packet (based on PSRQ for only non-AV enabled Rx Queues).
• 2'b01: VLAN Tagged PTPoE packets are routed to Rx Queue specified by PTPQ field (That Rx Queue can be enabled for AV or non-AV traffic).
• 2'b10: VLAN Tagged PTPoE packets are routed to only AV enabled Rx Queues based on PSRQ.
• 2'b11: Reserved

If DWC_EQOS_AV_ENABLE is not selected in the configuration, the following programmable options are allowed.

• 1'b0: VLAN Tagged PTPoE packets are routed as generic VLAN Tagged packet (based on PSRQ for DCB/Generic enabled Rx Queues).
• 1'b1: VLAN Tagged PTPoE packets are routed to Rx Queues specified by PTPQ field.

When set, the MAC routes the received Tagged AV Control packets to the Rx queue specified by AVCPQ field. When reset, the MAC routes the received Tagged AV Control packets based on the tag priority matching the PSRQ fields in MAC_RxQ_Ctrl2 and MAC_RxQ_Ctrl3 registers.

Values:

• 0x0(DISABLE): Tagged AV Control Packets Queuing is disabled
• 0x1(ENABLE): Tagged AV Control Packets Queuing is enabled

This bit specifies that Multicast or Broadcast packets routing to the Rx Queue is enabled and the Multicast or Broadcast packets must be routed to Rx Queue specified in MCBCQ field.

Values:

• 0x0(DISABLE): Multicast and Broadcast Queue is disabled
• 0x1(ENABLE): Multicast and Broadcast Queue is enabled

This field specifies the Rx Queue onto which Multicast or Broadcast Packets are routed. Any Rx Queue enabled for Generic/DCB/AV traffic can be used to route the Multicast or Broadcast Packets.

Values:

• 0x0(QUEUE0): Receive Queue 0
• 0x1(QUEUE1): Receive Queue 1
• 0x2(QUEUE2): Receive Queue 2
• 0x3(QUEUE3): Receive Queue 3
• 0x4(QUEUE4): Receive Queue 4
• 0x5(QUEUE5): Receive Queue 5
• 0x6(QUEUE6): Receive Queue 6
• 0x7(QUEUE7): Receive Queue 7

This field indicates the Rx Queue to which Untagged Packets are to be routed. Any Rx Queue enabled for Generic/DCB/AV traffic can be used to route the Untagged Packets.

Values:

• 0x0(QUEUE0): Receive Queue 0
• 0x1(QUEUE1): Receive Queue 1
• 0x2(QUEUE2): Receive Queue 2
• 0x3(QUEUE3): Receive Queue 3
• 0x4(QUEUE4): Receive Queue 4
• 0x5(QUEUE5): Receive Queue 5
• 0x6(QUEUE6): Receive Queue 6
• 0x7(QUEUE7): Receive Queue 7

This field specifies the Rx queue on which the received DCB control packets are routed. The DCB data packets are routed based on the PSRQ field of the Transmit Flow Control Register of corresponding queue.

Values:

• 0x0(QUEUE0): Receive Queue 0
• 0x1(QUEUE1): Receive Queue 1
• 0x2(QUEUE2): Receive Queue 2
• 0x3(QUEUE3): Receive Queue 3
• 0x4(QUEUE4): Receive Queue 4
• 0x5(QUEUE5): Receive Queue 5
• 0x6(QUEUE6): Receive Queue 6
• 0x7(QUEUE7): Receive Queue 7

This field specifies the Rx queue on which the PTP packets sent over the Ethernet payload (not over IPv4 or IPv6) are routed. When the AV8021ASMEN bit of MAC_Time stamp_Control register is set, only untagged PTP over Ethernet packets are routed on an Rx Queue. If the bit is not set, then based on programming of TPQC field, both tagged and untagged PTPoE packets can be routed to this Rx Queue.

Values:

• 0x0(QUEUE0): Receive Queue 0
• 0x1(QUEUE1): Receive Queue 1
• 0x2(QUEUE2): Receive Queue 2
• 0x3(QUEUE3): Receive Queue 3
• 0x4(QUEUE4): Receive Queue 4
• 0x5(QUEUE5): Receive Queue 5
• 0x6(QUEUE6): Receive Queue 6
• 0x7(QUEUE7): Receive Queue 7

This field specifies the Receive queue on which the received AV tagged and untagged control packets are routed. The AV tagged (when TACPQE bit is set) and untagged control packets are routed to Receive queue specified by this field.

Values:

• 0x0(QUEUE0): Receive Queue 0
• 0x1(QUEUE1): Receive Queue 1
• 0x2(QUEUE2): Receive Queue 2
• 0x3(QUEUE3): Receive Queue 3
• 0x4(QUEUE4): Receive Queue 4
• 0x5(QUEUE5): Receive Queue 5
• 0x6(QUEUE6): Receive Queue 6
• 0x7(QUEUE7): Receive Queue 7

This field decides the priorities assigned to Rx Queue 3. All packets with priorities that match the values set in this field are routed to Rx Queue 3. For example, if PSRQ3[6, 3] are set, packets with USP field equal to 3 or 6 are routed to Rx Queue 3.

The software must ensure that the content of this field is mutually exclusive to the PSRQ fields for other queues, that is, the same priority is not mapped to multiple Rx queues. When the DCB feature is selected, this field also determines the priorities to be included in the PFC packet sent to remote station when Rx Queue 3 crosses the flow control threshold settings.

This field decides the priorities assigned to Rx Queue 2. All packets with priorities that match the values set in this field are routed to Rx Queue 2. For example, if PSRQ2[1, 0] are set, packets with USP field equal to 1 or 0 are routed to Rx Queue 2.

The software must ensure that the content of this field is mutually exclusive to the PSRQ fields for other queues, that is, the same priority is not mapped to multiple Rx queues. When the DCB feature is selected, this field also determines the priorities to be included in the PFC packet sent to remote station when Rx Queue 2 crosses the flow control threshold settings.

This field decides the priorities assigned to Rx Queue 1. All packets with priorities that match the values set in this field are routed to Rx Queue 1. For example, if PSRQ1[4] is set, packets with USP field equal to 4 are routed to Rx Queue 1. The software must ensure that the content of this field is mutually exclusive to the PSRQ fields for other queues, that is, the same priority is not mapped to multiple Rx queues. When the DCB feature is selected, this field also determines the priorities to be included in the PFC packet sent to remote station when Rx Queue 1 crosses the flow control threshold settings.

This field decides the priorities assigned to Rx Queue 0. All packets with priorities that match the values set in this field are routed to Rx Queue 0. For example, if PSRQ0[5] is set, packets with USP field equal to 5 are routed to Rx Queue 0. The software must ensure that the content of this field is mutually exclusive to the PSRQ fields for other queues, that is, the same priority is not mapped to multiple Rx queues. When the DCB feature is selected, this field also determines the priorities to be included in the PFC packet sent to remote station when Rx Queue 0 crosses the flow control threshold settings.

This field decides the priorities assigned to Rx Queue 7. All packets with priorities that match the values set in this field are routed to Rx Queue 7. For example, if PSRQ7[7, 4] are set, packets with USP field equal to 7 or 4 are routed to Rx Queue 7. The software must ensure that the content of this field is mutually exclusive to the PSRQ fields for other queues, that is, the same priority is not mapped to multiple Rx queues. When the DCB feature is selected, this field also determines the priorities to be included in the PFC packet sent to remote station when Rx Queue 7 crosses the flow control threshold settings.

This field decides the priorities assigned to Rx Queue 6. All packets with priorities that match the values set in this field are routed to Rx Queue 6. For example, if PSRQ6[5] are set, packets with USP field equal to 5 are routed to Rx Queue 6. The software must ensure that the content of this field is mutually exclusive to the PSRQ fields for other queues, that is, the same priority is not mapped to multiple Rx queues. When the DCB feature is selected, this field also determines the priorities to be included in the PFC packet sent to remote station when Rx Queue 6 crosses the flow control threshold settings.

This field decides the priorities assigned to Rx Queue 5. All packets with priorities that match the values set in this field are routed to Rx Queue 5. For example, if PSRQ5[6] is set, packets with USP field equal to 6 are routed to Rx Queue 5. The software must ensure that the content of this field is mutually exclusive to the PSRQ fields for other queues, that is, the same priority is not mapped to multiple Rx queues. When the DCB feature is selected, this field also determines the priorities to be included in the PFC packet sent to remote station when Rx Queue 5 crosses the flow control threshold settings.

This field decides the priorities assigned to Rx Queue 4. All packets with priorities that match the values set in this field are routed to Rx Queue 4. For example, if PSRQ4[4:7] is set, packets with USP field equal to 7, 6, 5, or 4 are routed to Rx Queue 4. The software must ensure that the content of this field is mutually exclusive to the PSRQ fields for other queues, that is, the same priority is not mapped to multiple Rx queues. When the DCB feature is selected, this field also determines the priorities to be included in the PFC packet sent to remote station when Rx Queue 4 crosses the flow control threshold settings.

This bit is set high when an interrupt is generated in the MMC FPE Receive Interrupt Register. This bit is cleared when all bits in this interrupt register are cleared. This bit is valid only when you select the Enable MAC Management Counters (MMC) option along with FPE support.

Values:

• 0x0(INACTIVE): MMC FPE Receive Interrupt status not active
• 0x1(ACTIVE): MMC FPE Receive Interrupt status active

MMC FPE Transmit Interrupt Status

This bit is set high when an interrupt is generated in the MMC FPE Transmit Interrupt Register. This bit is cleared when all bits in this interrupt register are cleared. This bit is valid only when you select the Enable MAC Management Counters (MMC) option along with FPE support.

Values:

• 0x0(INACTIVE): MMC FPE Transmit Interrupt status not active
• 0x1(ACTIVE): MMC FPE Transmit Interrupt status active

MDIO Interrupt Status

This bit indicates an interrupt event after the completion of MDIO operation. To reset this bit, the application has to read this bit/Write 1 to this bit when RCWE bit of MAC_CSR_SW_Ctrl register is set.

Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MDIO Interrupt status not active
• 0x1(ACTIVE): MDIO Interrupt status active

Frame Preemption Interrupt Status

This bit indicates an interrupt event during the operation of Frame Preemption (Bits[19:16] of MAC_FPE_CTRL_STS register is set). To reset this bit, the application must clear the event in MAC_FPE_CTRL_STS that has caused the Interrupt.

Values:

• 0x0(INACTIVE): Frame Preemption Interrupt status not active
• 0x1(ACTIVE): Frame Preemption Interrupt status active

When the GPIO feature is enabled, this bit is set when any active event (LL or LH) occurs on the GPIS field of the MAC_GPIO_Status register and the corresponding GPIE bit is enabled in the MAC_GPIO_Control register. This bit is cleared on reading lane 0 (GPIS) of the MAC_GPIO_Status register.

Values:

• 0x0(INACTIVE): GPI Interrupt status not active
• 0x1(ACTIVE): GPI Interrupt status active

This bit indicates the status of received packets. This bit is set when the RWT bit is set in the MAC_Rx_Tx_Status register. This bit is cleared when the corresponding interrupt source bit is read (or corresponding interrupt source bit is written to 1 when RCWE bit of MAC_CSR_SW_Ctrl register is set) in the MAC_Rx_Tx_Status register.

Values:

• 0x0(INACTIVE): Receive Interrupt status not active
• 0x1(ACTIVE): Receive Interrupt status active

This bit indicates the status of transmitted packets. This bit is set when any of the following bits is set in the MAC_Rx_Tx_Status register:

• Excessive Collision (EXCOL)
• Late Collision (LCOL)
• Excessive Deferral (EXDEF)
• Loss of Carrier (LCARR)
• No Carrier (NCARR)
• Jabber Timeout (TJT)

This bit is cleared when the corresponding interrupt source bit is read (or corresponding interrupt source bit is written to 1 when RCWE bit of MAC_CSR_SW_Ctrl register is set) in the MAC_Rx_Tx_Status register.

Values:

• 0x0(INACTIVE): Transmit Interrupt status not active
• 0x1(ACTIVE): Transmit Interrupt status active

Time stamp Interrupt Status

If the Time stamp feature is enabled, this bit is set when any of the following conditions is true:

• The system time value is equal to or exceeds the value specified in the Target Time High and Low registers.
• There is an overflow in the Seconds register.
• The Target Time Error occurred, that is,programmed target time already elapsed.

If the Auxiliary Snapshot feature is enabled, this bit is set when the auxiliary snapshot trigger is asserted.

In configurations other than EQOS_CORE, when drop transmit status is enabled in MTL, this bit is set when the captured transmit time stamp is updated in the MAC_Tx_Timestamp_Status_Nanoseconds and Mac_TxTimestamp_Status_Seconds registers. When PTP offload feature is enabled, this bit is set when the captured transmit time stamp is updated in the MAC_Tx_Timestamp_Status_Nanoseconds and MAC_Tx_Timestamp_Status_Seconds registers, for PTO generated Delay Request and Pdelay request packets.

This bit is cleared when the corresponding interrupt source bit is read (or corresponding interrupt source bit is written to 1 when RCWE bit of MAC_CSR_SW_Ctrl register is set) in the MAC_Timestamp_Status register.

Values:

• 0x0(INACTIVE): Time stamp Interrupt status not active
• 0x1(ACTIVE): Time stamp Interrupt status active

This bit is set high when an interrupt is generated in the MMC Receive Checksum Offload Interrupt Register. This bit is cleared when all bits in this interrupt register are cleared.

This bit is valid only when you select the Enable MAC Management Counters (MMC) and Enable Receive TCP/IP Checksum Check options.

Values:

• 0x0(INACTIVE): MMC Receive Checksum Offload Interrupt status not active
• 0x1(ACTIVE): MMC Receive Checksum Offload Interrupt status active

This bit is set high when an interrupt is generated in the MMC Transmit Interrupt Register. This bit is cleared when all bits in this interrupt register are cleared.

This bit is valid only when you select the Enable MAC Management Counters (MMC) option.

Values:

• 0x0(INACTIVE): MMC Transmit Interrupt status not active
• 0x1(ACTIVE): MMC Transmit Interrupt status active

This bit is set high when an interrupt is generated in the MMC Receive Interrupt Register. This bit is cleared when all bits in this interrupt register are cleared.

This bit is valid only when you select the Enable MAC Management Counters (MMC) option.

Values:

• 0x0(INACTIVE): MMC Receive Interrupt status not active
• 0x1(ACTIVE): MMC Receive Interrupt status active

MMC Interrupt Status

This bit is set high when Bit 11, Bit 10, or Bit 9 is set high. This bit is cleared only when all these bits are low. This bit is valid only when you select the Enable MAC Management Counters (MMC) option.

Values:

• 0x0(INACTIVE): MMC Interrupt status not active
• 0x1(ACTIVE): MMC Interrupt status active

When the Energy Efficient Ethernet feature is enabled, this bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver. This bit is cleared when the corresponding interrupt source bit of MAC_LPI_Control_Status register is read (or corresponding interrupt source bit of MAC_LPI_Control_Status register is written to 1 when RCWE bit of MAC_CSR_SW_Ctrl register is set).

Values:

• 0x0(INACTIVE): LPI Interrupt status not active
• 0x1(ACTIVE): LPI Interrupt status active

PMT Interrupt Status

This bit is set when a Magic packet or Wake-on-LAN packet is received in the power-down mode (RWKPRCVD and MGKPRCVD bits in MAC_PMT_Control_Status register). This bit is cleared when corresponding interrupt source bit are cleared because of a Read operation to the MAC_PMT_Control_Status register (or corresponding interrupt source bit of MAC_PMT_Control_Status register is written to 1 when RCWE bit of MAC_CSR_SW_Ctrl register is set).

This bit is valid only when you select the Enable Power Management option.

Values:

• 0x0(INACTIVE): PMT Interrupt status not active
• 0x1(ACTIVE): PMT Interrupt status active

This bit is set when rising edge is detected on the phy_intr_i input. This bit is cleared when this register is read (or this bit is written to 1 when RCWE bit of MAC_CSR_SW_Ctrl register is set).

Values:

• 0x0(INACTIVE): PHY Interrupt not detected
• 0x1(ACTIVE): PHY Interrupt detected

This bit is set when auto-negotiation is completed in the TBI, RTBI, or SGMII PHY interface (see ANC bit in the MAC_AN_Status register). This bit is cleared when the MAC_AN_Status register is read (or ANC bit of MAC_AN_Status register is written to 1 when RCWE bit of MAC_CSR_SW_Ctrl register is set).

This bit is valid only when you select the optional TBI, RTBI, or SGMII PHY interface.

Values:

• 0x0(INACTIVE): PCS Auto-Negotiation has not Completed
• 0x1(ACTIVE): PCS Auto-Negotiation Completed

This bit is set because of any change in Link Status in the TBI, RTBI, or SGMII PHY interface (See LS bit in MAC_AN_Status register). This bit is cleared when the MAC_AN_Status register is read (or LS bit of MAC_AN_Status register is written to 1 when RCWE bit of MAC_CSR_SW_Ctrl register is set). This bit is valid only when you select the optional TBI, RTBI, or SGMII PHY interface.

Values:

• 0x0(INACTIVE): PCS Link Status has not Changed
• 0x1(ACTIVE): PCS Link Status Changed

Testable: Untestable

This bit is set because of any change in value of the Link Status of RGMII or SMII interface (LNKSTS bit in MAC_PHYIF_Control_Status register). This bit is cleared when the MAC_PHYIF_Control_Status register is read (or LNKSTS bit of MAC_PHYIF_Control_Status register is written to 1 when RCWE bit of MAC_CSR_SW_Ctrl register is set). This bit is valid only when you select the optional RGMII or SMII PHY interface.

Values:

• 0x0(INACTIVE): RGMII or SMII Interrupt Status is not active
• 0x1(ACTIVE): RGMII or SMII Interrupt Status is active

Testable: untestable

When this bit is set, it enables the assertion of the interrupt when MDIOIS field is set in the MAC_Interrupt_Status register.

Values:

• 0x0(DISABLE): MDIO Interrupt is disabled
• 0x1(ENABLE): MDIO Interrupt is enabled

When this bit is set, it enables the assertion of the interrupt when FPEIS field is set in the MAC_Interrupt_Status register.

Values:

• 0x0(DISABLE): Frame Preemption Interrupt is disabled
• 0x1(ENABLE): Frame Preemption Interrupt is enabled

Receive Status Interrupt Enable

When this bit is set, it enables the assertion of the interrupt signal because of the setting of RXSTSIS bit in the MAC_Interrupt_Status register.

Values:

• 0x0(DISABLE): Receive Status Interrupt is disabled
• 0x1(ENABLE): Receive Status Interrupt is enabled

When this bit is set, it enables the assertion of the interrupt signal because of the setting of TXSTSIS bit in the MAC_Interrupt_Status register.

Values:

• 0x0(DISABLE): Time stamp Status Interrupt is disabled
• 0x1(ENABLE): Time stamp Status Interrupt is enabled

When this bit is set, it enables the assertion of the interrupt signal because of the setting of TSIS bit in MAC_Interrupt_Status register.

Values:

• 0x0(DISABLE): Time stamp Interrupt is disabled
• 0x1(ENABLE): Time stamp Interrupt is enabled

When this bit is set, it enables the assertion of the interrupt signal because of the setting of LPIIS bit in MAC_Interrupt_Status register.

Values:

• 0x0(DISABLE): LPI Interrupt is disabled
• 0x1(ENABLE): LPI Interrupt is enabled

When this bit is set, it enables the assertion of the interrupt signal because of the setting of PMTIS bit in MAC_Interrupt_Status register.

Values:

• 0x0(DISABLE): PMT Interrupt is disabled
• 0x1(ENABLE): PMT Interrupt is enabled

When this bit is set, it enables the assertion of the interrupt signal because of the setting of PHYIS bit in MAC_Interrupt_Status register.

Values:

• 0x0(DISABLE): PHY Interrupt is disabled
• 0x1(ENABLE): PHY Interrupt is enabled

When this bit is set, it enables the assertion of the interrupt signal because of the setting of the PCSANCIS bit in MAC_Interrupt_Status register.

Values:

• 0x0(DISABLE): PCS AN Completion Interrupt is disabled
• 0x1(ENABLE): PCS AN Completion Interrupt is enabled

When this bit is set, it enables the assertion of the interrupt signal because of the setting of the PCSLCHGIS bit in MAC_Interrupt_Status register.

Values:

• 0x0(DISABLE): PCS Link Status Interrupt is disabled
• 0x1(ENABLE): PCS Link Status Interrupt is enabled

When this bit is set, it enables the assertion of the interrupt signal because of the setting of RGSMIIIS bit in MAC_Interrupt_Status register.

Values:

• 0x0(DISABLE): RGMII or SMII Interrupt is disabled
• 0x1(ENABLE): RGMII or SMII Interrupt is enabled

This bit is set when a packet with length greater than 2,048 bytes is received (10, 240 bytes when Jumbo Packet mode is enabled) and the WD bit is reset in the MAC_Configuration register. This bit is set when a packet with length greater than 16,383 bytes is received and the WD bit is set in the MAC_Configuration register.

Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): No receive watchdog timeout
• 0x1(ACTIVE): Receive watchdog timed out

When the DTXSTS bit is set in the MTL_Operation_Mode register, this bit indicates that the transmission aborted after 16 successive collisions while attempting to transmit the current packet. If the DR bit is set in the MAC_Configuration register, this bit is set after the first collision and the packet transmission is aborted.

Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): No collision
• 0x1(ACTIVE): Excessive collision is sensed

When the DTXSTS bit is set in the MTL_Operation_Mode register, this bit indicates that the packet transmission aborted because a collision occurred after the collision window (64 bytes including Preamble in MII mode; 512 bytes including Preamble and Carrier Extension in GMII mode).

This bit is not valid if the Underflow error occurs.

Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): No collision
• 0x1(ACTIVE): Late collision is sensed

When the DTXSTS bit is set in the MTL_Operation_Mode register and the DC bit is set in the MAC_Configuration register, this bit indicates that the transmission ended because of excessive deferral of over 24,288 bit times (155,680 in 1000/2500 Mbps mode or when Jumbo packet is enabled).

Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): No Excessive deferral
• 0x1(ACTIVE): Excessive deferral

When the DTXSTS bit is set in the MTL_Operation_Mode register, this bit indicates that the loss of carrier occurred during packet transmission, that is, the phy_crs_i signal was inactive for one or more transmission clock periods during packet transmission. This bit is valid only for packets transmitted without collision.

Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): Carrier is present
• 0x1(ACTIVE): Loss of carrier

When the DTXSTS bit is set in the MTL_Operation_Mode register, this bit indicates that the carrier signal from the PHY is not present at the end of preamble transmission.

Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): Carrier is present
• 0x1(ACTIVE): No carrier

This bit indicates that the Transmit Jabber Timer expired which happens when the packet size exceeds 2,048 bytes (10,240 bytes when the Jumbo packet is enabled) and JD bit is reset in the MAC_Configuration register. This bit is set when the packet size exceeds 16,383 bytes and the JD bit is set in the MAC_Configuration register.

Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): No Transmit Jabber Timeout
• 0x1(ACTIVE): Transmit Jabber Timeout occurred

Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect.

Values:

• 0x0(DISABLE): Remote Wake-Up Packet Filter Register Pointer is not Reset
• 0x1(ENABLE): Remote Wake-Up Packet Filter Register Pointer is Reset

Testable: Untestable

This field gives the current value (0 to 7, 15, or 31 when 4, 8, or 16 Remote Wake-up Packet Filters are selected) of the Remote Wake-up Packet Filter register pointer. When the value of this pointer is equal to maximum for the selected number of Remote Wake-up Packet Filters, the contents of the Remote Wake-up Packet Filter Register are transferred to the clk_rx_i domain when a Write occurs to that register.

Testable: Untestable

Remote Wake-up Packet Forwarding Enable

When this bit is set along with RWKPKTEN, the MAC receiver drops all received frames until it receives the expected

Wake-up frame. All frames after that event including the received wake-up frame are forwarded to application. This bit is then self-cleared on receiving the wake-up packet. The application can also clear this bit before the expected wake-up frame is received. In such cases, the MAC reverts to the default behavior where packets received are forwarded to the application. This bit must only be set when RWKPKTEN is set high and PWRDWN is set low. The setting of this bit has no effect when PWRDWN is set high.

Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect.

Values:

• 0x0(DISABLE): Remote Wake-up Packet Forwarding is disabled
• 0x1(ENABLE): Remote Wake-up Packet Forwarding is enabled

When this bit is set, any unicast packet filtered by the MAC (DAF) address recognition is detected as a remote wake-up packet.

Values:

• 0x0(DISABLE): Global unicast is disabled
• 0x1(ENABLE): Global unicast is enabled

When this bit is set, it indicates that the power management event is generated because of the reception of a remote wake-up packet. This bit is cleared when this register is read. Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): Remote wake-up packet is received
• 0x1(ACTIVE): Remote wake-up packet is received

When this bit is set, it indicates that the power management event is generated because of the reception of a magic packet. This bit is cleared when this register is read.

Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): No Magic packet is received
• 0x1(ACTIVE): Magic packet is received

When this bit is set, a power management event is generated when the MAC receives a remote wake-up packet.

Values:

• 0x0(DISABLE): Remote wake-up packet is disabled
• 0x1(ENABLE): Remote wake-up packet is enabled

When this bit is set, a power management event is generated when the MAC receives a magic packet.

Values:

• 0x0(DISABLE): Magic Packet is disabled
• 0x1(ENABLE): Magic Packet is enabled

When this bit is set, the MAC receiver drops all received packets until it receives the expected magic packet or remote wake-up packet. This bit is then self-cleared and the

power-down mode is disabled. The software can clear this bit before the expected magic packet or remote wake-up packet is received. The packets received by the MAC after this bit is cleared are forwarded to the application. This bit must only be set when the Magic Packet Enable, Global Unicast, or Remote Wake-Up Packet Enable bit is set high.

Therefore, the software cannot clear this bit.

Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect.

Values:

• 0x0(DISABLE): Power down is disabled
• 0x1(ENABLE): Power down is enabled

This field contains the various controls of RWK Packet filter.

Testable: Untestable

When this bit is set, the MACasserts sbd_tx_clk_gating_ctrl_o signal high after it enters Tx LPI mode to indicate that the Tx clock to MAC can be stopped. When this bit is reset, the MAC does not assert sbd_tx_clk_gating_ctrl_o signal high after it enters Tx LPI mode. If RGMII Interface is selected, the Tx clock is required for transmitting the LPI pattern. The Tx Clock cannot be gated and so the LPITCSE bit cannot be programmed.

Values:

• 0x0(DISABLE): LPI Tx Clock Stop is disabled
• 0x1(ENABLE): LPI Tx Clock Stop is enabled

This bit controls the automatic entry of the MAC Transmitter into and exit out of the LPI state. When LPIATE, LPITXA and LPIEN bits are set, the MAC Transmitter enters LPI state only when the complete MAC TX data path is IDLE for a period indicated by the MAC_LPI_Entry_Timer register. After entering LPI state, if the data path becomes non-IDLE (due to a new packet being accepted for transmission), the Transmitter exits LPI state but does not clear LPIEN bit. This enables the re-entry into LPI state when it is IDLE again. When LPIATE is 0, the LPI Auto timer is disabled and MAC Transmitter enters LPI state based on the settings of LPITXA and LPIEN bit descriptions.

Values:

• 0x0(DISABLE): LPI Timer is disabled
• 0x1(ENABLE): LPI Timer is enabled

This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the Transmit side. This bit is not functional in the EQOS-CORE configurations in which the Tx clock gating is done during the LPI mode.

If the LPITXA and LPIEN bits are set to 1, the MAC enters the LPI mode only after all outstanding packets (in the IP) and pending packets (in the application interface) have been transmitted. The MAC comes out of the LPI mode when the application sends any packet for transmission or the application issues a Tx FIFO Flush command. In addition, the MAC automatically clears the LPIEN bit when it exits the LPI state. If Tx FIFO Flush is set in the FTQ bit of MTL_TxQ0_Operation_Mode register, when the MAC is in the LPI mode, it exits the LPI mode.

When this bit is0, the LPIEN bit directly controls behavior of the MAC when it is entering or coming out of the LPI mode.

Values:

• 0x0(DISABLE): LPI Tx Automate is disabled
• 0x1(ENABLE): LPI Tx Automate is enabled

This bit enables the link status received on the RGMII, SGMII, or SMII Receive paths to be used for activating the LPI LS TIMER.

When this bit is set, the MAC uses the link-status bits of the MAC_PHYIF_Control_Status register and the PLS bit for the LPI LS Timer trigger. When this bit is reset, the MAC ignores the link-status bits of the MAC_PHYIF_Control_Status register and takes only the PLS bit.

Values:

• 0x0(DISABLE): PHY Link Status is disabled
• 0x1(ENABLE): PHY Link Status is enabled

This bit indicates the link status of the PHY. The MAC Transmitter asserts the LPI pattern only when the link status is up (OKAY) at least for the time indicated by the LPI LS TIMER. When this bit is set, the link is considered to be okay (UP) and when this bit is reset, the link is considered to be down.

Values:

• 0x0(DISABLE): link is down
• 0x1(ENABLE): link is okay (UP)

When this bit is set, it instructs the MAC Transmitter to enter the LPI state. When this bit is reset, it instructs the MAC to exit the LPI state and resume normal transmission.

This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state because of the arrival of a new packet for transmission.

Values:

• 0x0(DISABLE): LPI state is disabled
• 0x1(ENABLE): LPI state is enabled

When this bit is set, it indicates that the MAC is receiving the LPI pattern on the GMII or MII interface.

Values:

• 0x0(INACTIVE): Receive LPI state not detected
• 0x1(ACTIVE): Receive LPI state detected

When this bit is set, it indicates that the MAC is transmitting the LPI pattern on the GMII or MII interface.

Values:

• 0x0(INACTIVE): Transmit LPI state not detected
• 0x1(ACTIVE): Transmit LPI state detected

When this bit is set, it indicates that the MAC Receiver has stopped receiving the LPI pattern on the GMII or MII interface, exited the LPI state, and resumed the normal reception. This bit is cleared by a read into this register (or this bit is written to 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set).

Values:

• 0x0(INACTIVE): Receive LPI exit not detected
• 0x1(ACTIVE): Receive LPI exit detected

When this bit is set, it indicates that the MAC Receiver has received an LPI pattern and entered the LPI state. This bit is cleared by a read into this register (or this bit is written to 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set).

Values:

• 0x0(INACTIVE): Receive LPI entry not detected
• 0x1(ACTIVE): Receive LPI entry detected

When this bit is set, it indicates that the MAC transmitter exited the LPI state after the application cleared the LPIEN bit and the LPI TW Timer has expired. This bit is cleared by a read into this register (or this bit is written to 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set).

Values:

• 0x0(INACTIVE): Transmit LPI exit not detected
• 0x1(ACTIVE): Transmit LPI exit detected

When this bit is set, it indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. This bit is cleared by a read into this register (or this bit is written to 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set).

Values:

• 0x0(INACTIVE): Transmit LPI entry not detected
• 0x1(ACTIVE): Transmit LPI entry detected

This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. The MAC does not transmit the LPI pattern even when the LPIEN bit is set unless the LPI LS Timer reaches the programmed terminal count. The default value of the LPI LS Timer is 1000 (1 sec) as defined in the IEEE standard.

This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal transmission.

The TLPIEX status bit is set after the expiry of this timer.

This field specifies the time in microseconds the MAC waits to enter LPI mode, after it has transmitted all the frames. This field is valid and used only when LPITE and LPITXA are set to 1.

Bits [2:0] are read-only so that the granularity of this timer is in steps of 8 micro-seconds.

The application must program this counter so that the number of clock cycles of CSR clock is 1us. (Subtract 1 from the value before programming). For example if the CSR clock is 100MHz then this field needs to be programmed to value 100 - 1 = 99 (which is 0x63). This is required to generate the 1US events that are used to update some of the EEE related counters.

When this bit is set, the SGMII RAL block operates in the speed configured in the Speed and Port Select bits of the MAC_Configuration register. This is useful when the SGMII interface is used in a direct MAC to MAC connection (without a PHY) and any MAC must reconfigure the speed.

When this bit is reset, the SGMII RAL block operates according to the link speed status received on SGMII (from the PHY).

Values:

• 0x0(DISABLE): SGMII RAL Control is disabled
• 0x1(ENABLE): SGMII RAL Control is enabled

When this bit is set, the PHY locks its PLL to the 125 MHz reference clock. This bit controls the pcs_lck_ref_o signal on the TBI, RTBI, or SGMII interface.

Values:

• 0x0(DISABLE): Lock to Reference is disabled
• 0x1(ENABLE): Lock to Reference is enabled

When this bit is set, the PHY is enabled for comma detection and word resynchronization. When this bit is reset, the comma detection and word resynchronization is done internally by DWC_ether_qos PCS block. This bit controls the pcs_en_cdet_o signal on the TBI, RTBI, or SGMII interface.

Values:

• 0x0(DISABLE): Comma detect is disabled
• 0x1(ENABLE): Comma detect is enabled

When this bit is set, it enables the PHY to loopback the Transmit data into the Receive path. The pcs_ewrap_o signal is asserted high when this bit is set.

Values:

• 0x0(DISABLE): External Loopback is disabled
• 0x1(ENABLE): External Loopback is enabled

Auto-Negotiation Enable

When this bit is set, it enables the MAC to perform

auto-negotiation with the link partner. When this is reset, the auto-negotiation is disabled.

Values:

• 0x0(DISABLE): Auto-Negotiation is disabled
• 0x1(ENABLE): Auto-Negotiation is enabled

When this bit is set, auto-negotiation is restarted if Bit 12 (ANE) is set. This bit is self-clearing after auto-negotiation starts. This bit should be cleared for normal operation.

Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect.

Values:

• 0x0(DISABLE): Do not Restart Auto-Negotiation
• 0x1(ENABLE): Restart Auto-Negotiation

Testable: Untestable

This bit is tied to high if the TBI or RTBI interface is selected while configuring the IP, indicating that the MAC supports extended status information in the MAC_TBI_Extended_Status register. This bit is tied to low if the SGMII interface is selected and the TBI or RTBI interface is not selected while configuring the IP, indicating that MAC_TBI_Extended_Status register is not present.

• 1: TBI or RTBI
• 0: SGMIIwithout TBI or

Values:

• 0x0(INACTIVE): No Extended status
• 0x1(ACTIVE): Extended status

Auto-Negotiation Complete

When this bit is set, it indicates that the auto-negotiation process is complete. This bit is cleared when auto-negotiation is again initiated.

Values:

• 0x0(INACTIVE): Auto-Negotiation is not complete
• 0x1(ACTIVE): Auto-Negotiation is complete

This bit is always high because the MAC supports auto-negotiation.

Values:

• 0x0(INACTIVE): MAC does not posses Auto-Negotiation Ability
• 0x1(ACTIVE): MAC posses Auto-Negotiation Ability

Link Status

When this bit is set, it indicates that the link is up between the MAC and the TBI, RTBI, or SGMII interface. When this bit is reset, it indicates that the link is down between the MAC and the TBI, RTBI, or SGMII interface.

Values:

• 0x0(INACTIVE): Link is down
• 0x1(ACTIVE): Link is up

Testable: Untestable

This bit is always low because the MAC does not support the next page.

Values:

• 0x0(INACTIVE): MAC does not support the next page

Remote Fault Encoding

These bits provide a remote fault encoding, indicating to a link partner that a fault or error condition has occurred. The encoding of these bits is defined in IEEE 802.3z, Section 37.2.1.5.

These bits provide an encoding for the Pause bits, indicating that the MAC is capable of configuring the Pause function as defined in IEEE 802.3x. The encoding of these bits is defined in IEEE 802.3z, Section 37.2.1.4.

Half-Duplex

When set high, this bit indicates that the MAC supports the half-duplex mode. This bit is always low (and RO) when the MAC is configured for the full-duplex-only mode.

Values:

• 0x0(DISABLE): Full-duplex only mode
• 0x1(ENABLE): Supports Half-duplex mode

When set high, this bit indicates that the MAC supports the full-duplex mode.

Values:

• 0x0(DISABLE): Does not support Full-duplex mode
• 0x1(ENABLE): Supports full-duplex mode

When this bit is set, it indicates that more next page information is available. When this bit is reset, it indicates that the next page exchange is not desired.

Values:

• 0x0(INACTIVE): Next page support is not available
• 0x1(ACTIVE): Next page support is available

When this bit is set, the auto-negotiation function uses this bit to indicate that the link partner has successfully received the base page of the MAC. When this bit is reset, it indicates that the link partner did not successfully receive the base page of the MAC.

Values:

• 0x0(INACTIVE): link partner did not successfully receive the base page
• 0x1(ACTIVE): Acknowledge - link partner did not success- fully receive the base page

Remote Fault Encoding

These bits provide a remote fault encoding, indicating a fault or error condition of the link partner. The encoding of these bits is defined in IEEE 802.3z, Section 37.2.1.5.

These bits provide an encoding for the Pause bits. These bits indicate that the link partner is capable of configuring the Pause function as defined in the IEEE 802.3x. The encoding of these bits is defined in IEEE 802.3z, Section 37.2.1.4.

When this bit is set, it indicates that the link partner can operate in the half-duplex mode. When this bit is reset, it indicates that the link partner cannot operate in the half-duplex mode.

Values:

• 0x0(INACTIVE): Full-duplex only mode
• 0x1(ACTIVE): Supports Half-duplex mode

When this bit is set, it indicates that the link partner has the ability to operate in the full-duplex mode. When this bit is reset, it indicates that the link partner does not have the ability to operate in the full-duplex mode.

Values:

• 0x0(INACTIVE): Does not support Full-duplex mode
• 0x1(ACTIVE): Supports full-duplex mode

This bit is always low because the MAC does not support the next page function.

Values:

• 0x0(INACTIVE): Next page support not available

When this bit is set, it indicates that the MAC has received a new page. This bit is cleared when read.

• 0x0(INACTIVE): Next page not received
• 0x1(ACTIVE): Next page received

When this bit is set, the MAC is able to perform the full-duplex and 1000BASE-X operations.

Values:

• 0x0(INACTIVE): 1000BASE-X Full-Duplex Incapable
• 0x1(ACTIVE): 1000BASE-X Full-Duplex Capable

When this bit is set, the MAC is able to perform the half-duplex and 1000BASE-X operations. This bit is always low when the MAC is configured for the full-duplex-only operation while configuring the IP.

Values:

• 0x0(INACTIVE): 1000BASE-X Half-Duplex Incapable
• 0x1(ACTIVE): 1000BASE-X Half-Duplex Capable

This bit indicates whether the SMII PHY detected false carrier (1'b1).

Values:

• 0x0(INACTIVE): No False carrier
• 0x1(ACTIVE): False carrier detected

Testable: Untestable

This bit indicates the jabber timeout error (1'b1) in the received packet.

Values:

• 0x0(INACTIVE): No jabber timeout error
• 0x1(ACTIVE): Jabber timeout error

Testable: Untestable

This bit indicates whether the linkis up (1'b1) or down (1'b0).

Values:

• 0x0(INACTIVE): Link down
• 0x1(ACTIVE): Link up

Testable: Untestable

This bit indicates the current speed of the link. Bit 2 is reserved when the MAC is configured for the SMII PHY interface.

Values:

• 0x0(M_2500K): 2.5 MHz
• 0x1(M_25M): 25 MHz
• 0x2(M_125M): 125 MHz
• 0x3(RSVD): Reserved

Testable: Untestable

This bit indicates the current mode of operation of the link.

Values:

• 0x0(HDUPLX): Half-duplex mode
• 0x1(FDUPLX): Full-duplex mode

Testable: Untestable

When this bit is set, the first bit of the SMII Rx data is sampled one cycle after the SMII SYNC signal. When reset, the first bit of the SMII Rx data is sampled along with the SMII SYNC signal.

Values:

• 0x0(DISABLE): Disable Delay SMII Rx Data Sampling with respect to the SMII SYNC Signal
• 0x1(ENABLE): Enable Delay SMII Rx Data Sampling with respect to the SMII SYNC Signal

SMII Force Transmit Error

When set, this bit indicates to the PHY to force a transmit error in the SMII packet being transmitted.

Values:

• 0x0(DISABLE): SMII force transmit error is disabled
• 0x1(ENABLE): SMII force transmit error is enabled

This bit indicates whether the link is up or down during transmission of configuration in the RGMII, SGMII, or SMII interface.

Values:

• 0x0(LINKDOWN): Link down
• 0x1(LINKUP): Link up

When set, this bit enables the transmission of duplex mode, link speed, and link up or down information to the PHY in the RGMII, SMII, or SGMII port. When this bit is reset, no such information is driven to the PHY.

Values:

• 0x0(DISABLE): Disable Transmit Configuration in RGMII, SGMII, or SMII
• 0x1(ENABLE): Enable Transmit Configuration in RGMII, SGMII, or SMII

MAC Transmit Packet Controller Status

This field indicates the state of the MAC Transmit Packet Controller module.

Values:

• 0x0(IDLE): Idle state
• 0x1(WAITING): Waiting for one of the following: Status of the previous packet OR IPG or back off period to be over
• 0x2(GEN_TX_PAU): Generating and transmitting a Pause control packet (in full-duplex mode)
• 0x3(TRNSFR): Transferring input packet for transmission

MACGMII or MII Transmit Protocol Engine Status

When this bit is set, it indicates that the MAC GMII or MII transmit protocol engine is actively transmitting data, and it is not in the Idle state.

Values:

• 0x0(INACTIVE): MAC GMII or MII Transmit Protocol Engine Status not detected
• 0x1(ACTIVE): MAC GMII or MII Transmit Protocol Engine Status detected

MAC Receive Packet Controller FIFO Status

When this bit is set, this field indicates the active state of the small FIFO Read and Write controllers of the MAC Receive Packet Controller module.

MACGMII or MII Receive Protocol Engine Status

When this bit is set, it indicates that the MAC GMII or MII receive protocol engine is actively receiving data, and it is not in the Idle state.

Values:

• 0x0(INACTIVE): MAC GMII or MII Receive Protocol Engine Status not detected
• 0x1(ACTIVE): MAC GMII or MII Receive Protocol Engine Status detected

Active PHY Selected

When you have multiple PHY interfaces in your configuration, this field indicates the sampled value of phy_intf_sel_i during reset de-assertion.

Values:

• 0x0(GMII_MII): GMII or MII
• 0x1(RGMII): RGMII
• 0x2(SGMII): SGMII
• 0x3(TBI): TBI
• 0x4(RMII): RMII
• 0x5(RTBI): RTBI
• 0x6(SMII): SMII
• 0x7(REVMIII): RevMII

Source Address orVLAN Insertion Enable

This bit is set to 1 when the Enable SA and VLAN Insertion on Tx option is selected

Values:

• 0x0(INACTIVE): Source Address or VLAN Insertion Enable option is not selected
• 0x1(ACTIVE): Source Address or VLAN Insertion Enable option is selected

This bit indicates the source of the Time stamp system time: This bit is set to 1 when the Enable IEEE 1588 Time stamp Support option is selected

Values:

• 0x0(INTRNL): Internal
• 0x1(EXTRNL): External
• 0x2(BOTH): Both
• 0x3(RSVD): Reserved

This bit is set to 1 when the Enable Additional 64 MAC Address Registers (64-127) option is selected

Values:

• 0x0(INACTIVE): MAC Addresses 64-127 Select option is not selected
• 0x1(ACTIVE): MAC Addresses 64-127 Select option is selected

MAC Addresses 32-63 Selected

This bit is set to 1 when the Enable Additional 32 MAC Address Registers (32-63) option is selected

Values:

• 0x0(INACTIVE): MAC Addresses 32-63 Select option is not selected
• 0x1(ACTIVE): MAC Addresses 32-63 Select option is selected

This bit is set to 1 when the non-zero value is selected for Enable Additional 1-31 MAC Address Registers option

This bit is set to 1 when the Enable Receive TCP/IP Checksum Check option is selected

Values:

• 0x0(INACTIVE): Receive Checksum Offload Enable option is not selected
• 0x1(ACTIVE): Receive Checksum Offload Enable option is selected

This bit is set to 1 when the Enable Transmit TCP/IP Checksum Insertion option is selected

Values:

• 0x0(INACTIVE): Transmit Checksum Offload Enable option is not selected
• 0x1(ACTIVE): Transmit Checksum Offload Enable option is selected

This bit is set to 1 when the Enable Energy Efficient Ethernet (EEE) option is selected

Values:

• 0x0(INACTIVE): Energy Efficient Ethernet Enable option is not selected
• 0x1(ACTIVE): Energy Efficient Ethernet Enable option is selected

This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected

Values:

• 0x0(INACTIVE): IEEE 1588-2008 Timestamp Enabled option is not selected
• 0x1(ACTIVE): IEEE 1588-2008 Timestamp Enabled option is selected

This bit is set to 1 when the Enable IPv4 ARP Offload option is selected

Values:

• 0x0(INACTIVE): ARP Offload Enable option is not selected
• 0x1(ACTIVE): ARP Offload Enable option is selected

This bit is set to 1 when the Enable MAC Management Counters (MMC) option is selected

Values:

• 0x0(INACTIVE): RMON Module Enable option is not selected
• 0x1(ACTIVE): RMON Module Enable option is selected

This bit is set to 1 when the Enable Magic Packet Detection option is selected

Values:

• 0x0(INACTIVE): PMT Magic Packet Enable option is not selected
• 0x1(ACTIVE): PMT Magic Packet Enable option is selected

This bit is set to 1 when the Enable Remote Wake-Up Packet Detection option is selected

Values:

• 0x0(INACTIVE): PMT Remote Wake-up Packet Enable option is not selected
• 0x1(ACTIVE): PMT Remote Wake-up Packet Enable option is selected

This bit is set to 1 when the Enable Station Management (MDIO Interface) option is selected

Values:

• 0x0(INACTIVE): SMA (MDIO) Interface not selected
• 0x1(ACTIVE): SMA (MDIO) Interface selected

This bit is set to 1 when the Enable VLAN Hash Table Based Filtering option is selected

Values:

• 0x0(INACTIVE): VLAN Hash Filter not selected
• 0x1(ACTIVE): VLAN Hash Filter selected

PCS Registers (TBI, SGMII, or RTBI PHY interface)

This bit is set to 1 when the TBI, SGMII, or RTBI PHY interface option is selected

Values:

• 0x0(INACTIVE): No PCS Registers (TBI, SGMII, or RTBI PHY interface)
• 0x1(ACTIVE): PCS Registers (TBI, SGMII, or RTBI PHY interface)

This bit is set to 1 when the half-duplex mode is selected

Values:

• 0x0(INACTIVE): No Half-duplex support
• 0x1(ACTIVE): Half-duplex support

This bit is set to 1 when 1000 Mbps is selected as the Mode of Operation

Values:

• 0x0(INACTIVE): No 1000 Mbps support
• 0x1(ACTIVE): 1000 Mbps support

This bit is set to 1 when 10/100 Mbps is selected as the Mode of Operation

Values:

• 0x0(INACTIVE): No 10 or 100 Mbps support
• 0x1(ACTIVE): 10 or 100 Mbps support

This field indicates the total number ofL3 or L4 filters:

Values:

• 0x0(NOFILT): No L3 or L4 Filter
• 0x1(M_1FILT): 1 L3 or L4 Filter
• 0x2(M_2FILT): 2 L3 or L4 Filters
• 0x3(M_3FILT): 3 L3 or L4 Filters
• 0x4(M_4FILT): 4 L3 or L4 Filters
• 0x5(M_5FILT): 5 L3 or L4 Filters
• 0x6(M_6FILT): 6 L3 or L4 Filters
• 0x7(M_7FILT): 7 L3 or L4 Filters
• 0x8(M_8FILT): 8 L3 or L4 Filters

This field indicates the size of the hash table:

Values:

• 0x0(NO_HT): No hash table
• 0x1(M_64): 64
• 0x2(M_128): 128
• 0x3(M_256): 256

This bit is set to 1 when the Enable One step time stamp for PTP over UDP/IP feature is selected.

Values:

• 0x0(INACTIVE): One Step for PTP over UDP/IP Feature is not selected
• 0x1(ACTIVE): One Step for PTP over UDP/IP Feature is selected

This bit is set to 1 when the Enable Audio Video Bridging option on Rx Side Only is selected.

Values:

• 0x0(INACTIVE): Rx Side Only AV Feature is not selected
• 0x1(ACTIVE): Rx Side Only AV Feature is selected

This bit is set to 1 when the Enable Audio Video Bridging option is selected.

Values:

• 0x0(INACTIVE): AV Feature is not selected
• 0x1(ACTIVE): AV Feature is selected

This bit is set to 1 when the Debug Mode Enable option is selected

Values:

• 0x0(INACTIVE): DMA Debug Registers option is not selected
• 0x1(ACTIVE): DMA Debug Registers option is selected

This bit is set to 1 when the Enable TCP Segmentation Offloading for TCP/IP Packets option is selected

Values:

• 0x0(INACTIVE): TCP Segmentation Offload Feature is not selected
• 0x1(ACTIVE): TCP Segmentation Offload Feature is selected

Split Header Feature Enable

This bit is set to 1 when the Enable Split Header Structure option is selected

Values:

• 0x0(INACTIVE): Split Header Feature is not selected
• 0x1(ACTIVE): Split Header Feature is selected

DCB Feature Enable

This bit is set to 1 when the Enable Data Center Bridging option is selected

Values:

• 0x0(INACTIVE): DCB Feature is not selected
• 0x1(ACTIVE): DCB Feature is selected

Address Width.

This field indicates the configured address width:

Values:

• 0x0(M_32): 32
• 0x1(M_40): 40
• 0x2(M_48): 48
• 0x3(RSVD): Reserved

IEEE1588 High Word Register Enable

This bit is set to 1 when the Add IEEE 1588 Higher Word Register option is selected

Values:

• 0x0(INACTIVE): IEEE 1588 High Word Register option is not selected
• 0x1(ACTIVE): IEEE 1588 High Word Register option is selected

PTP Offload Enable

This bit is set to 1 when the Enable PTP Time stamp Offload Feature is selected.

Values:

• 0x0(INACTIVE): PTP Offload feature is not selected
• 0x1(ACTIVE): PTP Offload feature is selected

One-Step Time-stamping Enable

This bit is set to 1 when the Enable One-Step Time-stamp Feature is selected.

Values:

• 0x0(INACTIVE): One-Step Time-stamping feature is not selected
• 0x1(ACTIVE): One-Step Time-stamping feature is selected

Value After Reset: ((DWC_EQOS_OST_EN)?\"1\":\"0\")

This field contains the configured value of MTL Tx FIFO in bytes expressed as Log to base 2 minus 7, that is, Log2(TXFIFO_SIZE) -7.

Values:

• 0x0(M_128B): 128 bytes
• 0x1(M_256B): 256 bytes
• 0x2(M_512B): 512 bytes
• 0x3(M_1024B): 1024 bytes
• 0x4(M_2048B): 2048 bytes
• 0x5(M_4096B): 4096 bytes
• 0x6(M_8192B): 8192 bytes
• 0x7(M_16384B): 16384 bytes
• 0x8(M_32KB): 32 KB
• 0x9(M_64KB): 64 KB
• 0xa(M_128KB): 128 KB
• 0xb(RSVD): Reserved

This bit is set to 1 when the Use single port RAM Feature is selected.

Values:

• 0x0(INACTIVE): Single Port RAM feature is not selected
• 0x1(ACTIVE): Single Port RAM feature is selected

MTL Receive FIFO Size

This field contains the configured value of MTL Rx FIFO in bytes expressed as Log to base 2 minus 7, that is, Log2(RXFIFO_SIZE) -7:

Values:

• 0x1(M_256B): 256 bytes
• 0x2(M_512B): 512 bytes
• 0x3(M_1024B): 1024 bytes
• 0x4(M_2048B): 2048 bytes
• 0x5(M_4096B): 4096 bytes
• 0x6(M_8192B): 8192 bytes
• 0x7(M_16384B): 16384 bytes
• 0x8(M_32KB): 32 KB
• 0x9(M_64KB): 64 KB
• 0xa(M_128KB): 128 KB
• 0xb(M_256KB): 256 KB
• 0xc(RSVD): Reserved

Number of Auxiliary Snapshot Inputs

This field indicates the number of auxiliary snapshot inputs:

Values:

• 0x0(NO_AUXI): No auxiliary input
• 0x1(M_1_AUXI): 1 auxiliary input
• 0x2(M_2_AUXI): 2 auxiliary input
• 0x3(M_3_AUXI): 3 auxiliary input
• 0x4(M_4_AUXI): 4 auxiliary input
• 0x5(RSVD): Reserved

Number of PPS Outputs

This field indicates the number of PPS outputs:

Values:

• 0x0(NO_PPSO): No PPS output
• 0x1(M_1_PPSO): 1 PPS output
• 0x2(M_2_PPSO): 2 PPS output
• 0x3(M_3_PPSO): 3 PPS output
• 0x4(M_4_PPSO): 4 PPS output
• 0x5(RSVD): Reserved

Tx DMA Descriptor Cache Size in terms of 16 bytes descriptors:

00 -Cache Not configured 01 - 4 16 bytes descriptor

1. -8 16 bytes descriptor
2. -16 16 bytes descriptor

Number of DMA Transmit Channels

This field indicates the number of DMA Transmit channels:

Values:

• 0x0(M_1TXCH): 1 MTL Tx Channel
• 0x1(M_2TXCH): 2 MTL Tx Channels
• 0x2(M_3TXCH): 3 MTL Tx Channels
• 0x3(M_4TXCH): 4 MTL Tx Channels
• 0x4(M_5TXCH): 5 MTL Tx Channels
• 0x5(M_6TXCH): 6 MTL Tx Channels
• 0x6(M_7TXCH): 7 MTL Tx Channels
• 0x7(M_8TXCH): 8 MTL Tx Channels
• 0x0(NO_DCACHE): Desc Cache not configured
• 0x1(M_1TDCSZ): 4
• 0x2(M_2TDCSZ): 8
• 0x3(M_3TDCSZ): 16

Rx DMA Descriptor Cache Size in terms of 16 bytes descriptors:

00 -Cache Not configured 01 - 4 16 bytes descriptor

1. -8 16 bytes descriptor
2. -16 16 bytes descriptor

Number of DMA Receive Channels

This field indicates the number of DMA Receive channels:

Values:

• 0x0(M_1RXCH): 1 MTL Rx Channel
• 0x1(M_2RXCH): 2 MTL Rx Channels
• 0x2(M_3RXCH): 3 MTL Rx Channels
• 0x3(M_4RXCH): 4 MTL Rx Channels
• 0x4(M_5RXCH): 5 MTL Rx Channels
• 0x5(M_6RXCH): 6 MTL Rx Channels
• 0x6(M_7RXCH): 7 MTL Rx Channels
• 0x7(M_8RXCH): 8 MTL Rx Channels
• 0x0(NO_DCACHE): Desc Cache not configured

0x1(M_1RDCSZ): 4

0x2(M_2RDCSZ): 8

0x3(M_3RDCSZ): 16

Number of MTL Transmit Queues

This field indicates the number of MTL Transmit queues:

Values:

• 0x0(M_1TXQ): 1 MTL Tx Queue
• 0x1(M_2TXQ): 2 MTL Tx Queues
• 0x2(M_3TXQ): 3 MTL Tx Queues
• 0x3(M_4TXQ): 4 MTL Tx Queues
• 0x4(M_5TXQ): 5 MTL Tx Queues
• 0x5(M_6TXQ): 6 MTL Tx Queues
• 0x6(M_7TXQ): 7 MTL Tx Queues
• 0x7(M_8TXQ): 8 MTL Tx Queues

Number of MTL Receive Queues

This field indicates the number of MTL Receive queues:

Values:

• 0x0(M_1RXQ): 1 MTL Rx Queue
• 0x1(M_2RXQ): 2 MTL Rx Queues
• 0x2(M_3RXQ): 3 MTL Rx Queues
• 0x3(M_4RXQ): 4 MTL Rx Queues
• 0x4(M_5RXQ): 5 MTL Rx Queues
• 0x5(M_6RXQ): 6 MTL Rx Queues
• 0x6(M_7RXQ): 7 MTL Rx Queues
• 0x7(M_8RXQ): 8 MTL Rx Queues

Automotive Safety Package

Following are the encoding for the different Safety features

Values:

• 0x0(NONE): No Safety features selected
• 0x1(ECC_ONLY): Only "ECC protection for external memory" feature is selected
• 0x2(AS_NPPE): All the Automotive Safety features are selected without the "Parity Port Enable for external interface" feature
• 0x3(AS_PPE): All the Automotive Safety features are selected with the "Parity Port Enable for external interface" feature

Time Based Scheduling Enable

This bit is set to 1 when the Time Based Scheduling feature is selected.

Values:

• 0x0(INACTIVE): Time Based Scheduling Enable feature is not selected
• 0x1(ACTIVE): Time Based Scheduling Enable feature is selected

This bit is set to 1 when the Enable Frame preemption feature is selected.

Values:

• 0x0(INACTIVE): Frame Preemption Enable feature is not selected
• 0x1(ACTIVE): Frame Preemption Enable feature is selected

This field indicates the width of the Configured Time Interval Field

Values:

• 0x0(NOWIDTH): Width not configured
• 0x1(WIDTH16): 16
• 0x2(WIDTH20): 20
• 0x3(WIDTH24): 24

This field indicates the depth of Gate Control list expressed as Log2(DWC_EQOS_EST_DEP)-5

Values:

• 0x0(NODEPTH): No Depth configured
• 0x1(DEPTH64): 64
• 0x2(DEPTH128): 128
• 0x3(DEPTH256): 256
• 0x4(DEPTH512): 512
• 0x5(DEPTH1024): 1024
• 0x6(RSVD): Reserved

This bit is set to 1 when the Enable Enhancements to Scheduling Traffic feature is selected.

Values:

• 0x0(INACTIVE): Enable Enhancements to Scheduling Traffic feature is not selected
• 0x1(ACTIVE): Enable Enhancements to Scheduling Traffic feature is selected

This field indicates the Max Number of Parser Entries supported by Flexible Receive Parser.

Values:

• 0x0(M_64ENTR): 64 Entries
• 0x1(M_128ENTR): 128 Entries
• 0x2(M_256ENTR): 256 Entries
• 0x3(RSVD): Reserved

This field indicates the supported Max Number of bytes of the packet data to be Parsed by Flexible Receive Parser.

Values:

• 0x0(M_64BYTES): 64 Bytes
• 0x1(M_128BYTES): 128 Bytes
• 0x2(M_256BYTES): 256 Bytes
• 0x3(RSVD): Reserved

This bit is set to 1 when the Enable Flexible Programmable Receive Parser option is selected.

Values:

• 0x0(INACTIVE): Flexible Receive Parser feature is not selected
• 0x1(ACTIVE): Flexible Receive Parser feature is selected

This bit is set to 1 when the Broadcast/Multicast Packet Duplication feature is selected.

Values:

• 0x0(INACTIVE): Broadcast/Multicast Packet Duplication feature is not selected
• 0x1(ACTIVE): Broadcast/Multicast Packet Duplication feature is selected

This bit is set to 1 when the Enable Double VLAN Processing Feature is selected.

Values:

• 0x0(INACTIVE): Double VLAN option is not selected
• 0x1(ACTIVE): Double VLAN option is selected

This bit is set to 1 when the Enable Queue/Channel based VLAN tag insertion on Tx Feature is selected.

Values:

• 0x0(INACTIVE): Enable Queue/Channel based VLAN tag insertion on Tx feature is not selected
• 0x1(ACTIVE): Enable Queue/Channel based VLAN tag insertion on Tx feature is selected

Number of Extended VLAN Tag Filters Enabled

This field indicates the Number of Extended VLAN Tag Filters selected:

Values:

• 0x0(NO_ERVLAN): No Extended Rx VLAN Filters
• 0x1(M_4_ERVLAN): 4 Extended Rx VLAN Filters
• 0x2(M_8_ERVLAN): 8 Extended Rx VLAN Filters
• 0x3(M_16_ERVLAN): 16 Extended Rx VLAN Filters
• 0x4(M_24_ERVLAN): 24 Extended Rx VLAN Filters
• 0x5(M_32_ERVLAN): 32 Extended Rx VLAN Filters
• 0x6(RSVD): Reserved

Values:

• 0x0(INACTIVE): Descriptor Cache data path Parity checker Error Status not detected
• 0x1(ACTIVE): Descriptor Cache data path Parity checker Error Status detected

Testable: Untestable

MTL RWC Data Path Parity checker Error Status

This filed when set indicates that, parity error is detected on the MTL RWC data interface (or at PC12 as shown in Receive data path parity protection diagram).

Values:

• 0x0(INACTIVE): MTL RWC data path Parity checker Error Status not detected
• 0x1(ACTIVE): MTL RWC data path Parity checker Error Status detected

Testable: Untestable

MAC TFC Data Path Parity Checker Error Status

This filed when set indicates that, parity error is detected on the MAC TFC data interface (or at PC11 as shown in Transmit data path parity protection diagram).

Values:

• 0x0(INACTIVE): MAC TFC data path Parity checker Error Status not detected
• 0x1(ACTIVE): MAC TFC data path Parity checker Error Status detected

Testable: Untestable

MACTBU data path Parity checker Error Status

This filed when set indicates that, parity error is detected on the MAC TBU data interface (or at PC10 as shown in Transmit data path parity protection diagram).

Values:

• 0x0(INACTIVE): MAC TBU data path Parity checker Error Status not detected
• 0x1(ACTIVE): MAC TBU data path Parity checker Error Status detected

Testable: Untestable

This field when set indicates one of the FSMs State registers has a parity error detected.

Values:

• 0x0(INACTIVE): FSM State Parity Error Status not detected
• 0x1(ACTIVE): FSM State Parity Error Status detected

Testable: Untestable

This field when set indicates that an Application/CSR Timeout has occurred on the AXIslave interface.

Values:

• 0x0(INACTIVE): Slave Read/Write Timeout Error Status not detected
• 0x1(ACTIVE): Slave Read/Write Timeout Error Status detected

Testable: Untestable

This field when set indicates that an Application/CSR Timeout has occurred on the master (AXI/AHB/ARI/ATI) interface.

Values:

• 0x0(INACTIVE): Master Read/Write Timeout Error Status not detected
• 0x1(ACTIVE): Master Read/Write Timeout Error Status detected

Testable: Untestable

REVMDC FSM Timeout Error Status

This field when set indicates that one of the Rev Mdc FSM Timeout has occurred.

Values:

• 0x0(INACTIVE): REV MDC FSM Timeout Error Status not detected
• 0x1(ACTIVE): REV MDC FSM Timeout Error Status detected

Testable: Untestable

This field when set indicates that one of the Rx125 FSM Timeout has occurred.

Values:

• 0x0(INACTIVE): Rx125 FSM Timeout Error Status not detected
• 0x1(ACTIVE): Rx125 FSM Timeout Error Status detected

Testable: Untestable

This field when set indicates that one of the Tx125 FSM Timeout has occurred.

Values:

• 0x0(INACTIVE): Tx125 FSM Timeout Error Status not detected
• 0x1(ACTIVE): Tx125 FSM Timeout Error Status detected

Testable: Untestable

This field when set indicates that one of the PTP FSM Timeout has occurred.

Values:

• 0x0(INACTIVE): PTP FSM Timeout Error Status not detected
• 0x1(ACTIVE): PTP FSM Timeout Error Status detected

Testable: Untestable

This field when set indicates that one of the APP FSM Timeout has occurred.

Values:

• 0x0(INACTIVE): APP FSM Timeout Error Status not detected
• 0x1(ACTIVE): APP FSM Timeout Error Status detected

Testable: Untestable

This field when set indicates that one of the CSR FSM Timeout has occurred.

Values:

• 0x0(INACTIVE): CSR FSM Timeout Error Status not detected
• 0x1(ACTIVE): CSR FSM Timeout Error Status detected

Testable: Untestable

This field when set indicates that one of the Rx FSM Timeout has occurred.

Values:

• 0x0(INACTIVE): Rx FSM Timeout Error Status not detected
• 0x1(ACTIVE): Rx FSM Timeout Error Status detected

Testable: Untestable

This field when set indicates that one of the Tx FSM Timeout has occurred.

Values:

• 0x0(INACTIVE): Tx FSM Timeout Error Status not detected
• 0x1(ACTIVE): Tx FSM Timeout Error Status detected

Testable: Untestable

This bit when set indicates that parity error is detected at the AXI Slave read data interface on "rdata_s_o" or at PC9 checker.

Values:

• 0x0(INACTIVE): AXI Slave Read data path Parity checker Error Status not detected
• 0x1(ACTIVE): AXI Slave Read data path Parity checker Error Status detected

Testable: Untestable

This bit when set indicates that parity error is detected at the CSR write data interface on mci_wdata_i (or at PC8 checker as shown in AXI slave Interface Data path parity protection diagram).

When EPSI bit of MTL_DPP_Control register is set and if any parity mismatch is detected on the input slave parity ports (or at PC7 checker in the AXI slave Interface Data path parity protection diagram) sets this bit to one.

Values:

• 0x0(INACTIVE): CSR Write data path Parity checker Error Status not detected
• 0x1(ACTIVE): CSR Write data path Parity checker Error Status detected

Testable: Untestable

• In MTL configuration (DWC_EQOS_SYS=1), parity checker (PC6 as shown in Receive Data path Parity protection diagram) at ARI interface.
• In DMA configuration (DWC_EQOS_SYS=2), parity checker (PC6 as shown in Receive Data path Parity protection diagram) at DMA application interface.
• In AHB configuration (DWC_EQOS_SYS=3), parity checker (PC6 as shown in Receive Data path Parity protection diagram) at AHB master interface.
• In AXI configuration (DWC_EQOS_SYS=4), parity checker (PC6 as shown in Receive Data path Parity protection diagram) at AXI master interface.

Values:

• 0x0(INACTIVE): Application Receive interface data path Parity Error Status not detected
• 0x1(ACTIVE): Application Receive interface data path Parity Error Status detected

Testable: Untestable

MTL TX Status data path Parity checker Error Status

This filed when set indicates that, parity error is detected on the MTL TX Status data on an interface (or at PC5 as shown in Transmit data path parity protection diagram).

Values:

• 0x0(INACTIVE): MTL TX Status data path Parity checker Error Status not detected
• 0x1(ACTIVE): MTL TX Status data path Parity checker Error Status detected

Testable: Untestable

This bit when set indicates that a parity error is detected at the MTL transmit write controller parity checker (or at PC4 as shown in Transmit data path parity protection diagram).

Values:

• 0x0(INACTIVE): MTL data path Parity checker Error Status not detected
• 0x1(ACTIVE): MTL data path Parity checker Error Status detected

Testable: Untestable

This bit when set indicates that a parity error is detected at the DMA Read descriptor parity checker (or at PC3 as shown in Transmit data path parity protection diagram).

Values:

• 0x0(INACTIVE): Read Descriptor Parity checker Error Status not detected
• 0x1(ACTIVE): Read Descriptor Parity checker Error Status detected

Testable: Untestable

This bit when set indicates that a parity error is detected at the DMA TSO parity checker (or at PC2 as shown in Transmit data path parity protection diagram).

Values:

• 0x0(INACTIVE): TSO data path Parity checker Error Status not detected
• 0x1(ACTIVE): TSO data path Parity checker Error Status detected

Testable: Untestable

This bit when set indicates that a parity error is detected on the AXI/AHB Master read data parity checker.

This bit when set indicates that a parity error is detected on the interface port parity checker. Following are the checkers located based on the system configuration,

• In MTL configuration (DWC_EQOS_SYS=1), parity checker at ATI interface.
• In DMA configuration (DWC_EQOS_SYS=2), parity checker (PC1 as shown in Transmit data path parity protection diagram) at DMA application interface.
• In AHB configuration (DWC_EQOS_SYS=3), parity checker (PC1 as shown in Transmit data path parity protection diagram) at AHB master interface.
• In AXI configuration (DWC_EQOS_SYS=4), parity checker (PC1 as shown in Transmit data path parity protection diagram) at AXI master interface.

Values:

• 0x0(INACTIVE): Application Transmit Interface Parity checker Error Status not detected
• 0x1(ACTIVE): Application Transmit Interface Parity checker Error Status detected

Testable: Untestable

This field holds the CSR address for which parity error is detected on the CSR write data. This field holds the first address for which parity error is detected on the write data and is cleared on read.

This field when set indicates that large mode tic generation is used for RevMII MDC domain, else normal mode tic generation is used.

Values:

• 0x0(DISABLE): Normal mode tic generation is used for REVMII MDC domain
• 0x1(ENABLE): Large mode tic generation is used for REVMII MDC domain

This field when set indicates that large mode tic generation is used for Rx125 domain, else normal mode tic generation is used.

Values:

• 0x0(DISABLE): Normal mode tic generation is used for Rx125 domain
• 0x1(ENABLE): Large mode tic generation is used for Rx125 domain

Tx125 Large/Normal Mode Select

This field when set indicates that large mode tic generation is used for Tx125 domain, else normal mode tic generation is used.

Values:

• 0x0(DISABLE): Normal mode tic generation is used for Tx125 domain
• 0x1(ENABLE): Large mode tic generation is used for Tx125 domain

This field when set indicates that large mode tic generation is used for PTP domain, else normal mode tic generation is used.

Values:

• 0x0(DISABLE): Normal mode tic generation is used for PTP domain
• 0x1(ENABLE): Large mode tic generation is used for PTP domain

Values:

• 0x0(DISABLE): normal mode tic generation is used for APP domain
• 0x1(ENABLE): large mode tic generation is used for APP domain

Values:

• 0x0(DISABLE): normal mode tic generation is used for CSR domain
• 0x1(ENABLE): large mode tic generation is used for CSR domain

This field when set indicates that large mode tic generation is used for Rx domain, else normal mode tic generation is used.

Values:

• 0x0(DISABLE): normal mode tic generation is used for Rx domain
• 0x1(ENABLE): large mode tic generation is used for Rx domain

Tx Large/Normal Mode SelectThis field when set indicates that large mode tic generation is used for Tx domain, else normal mode tic generation is used.

Values:

• 0x0(DISABLE): normal mode tic generation is used for Tx domain
• 0x1(ENABLE): large mode tic generation is used for Tx domain

This field when set indicates that Error Injection for REVMII MDC FSM Parity is enabled.

Values:

• 0x0(DISABLE): REV MDC FSM Parity Error Injection is disabled
• 0x1(ENABLE): REV MDC FSM Parity Error Injection is enabled

This field when set indicates that Error Injection for RX125 FSM Parity is enabled.

Values:

• 0x0(DISABLE): Rx125 FSM Parity Error Injection is disabled
• 0x1(ENABLE): Rx125 FSM Parity Error Injection is enabled

This field when set indicates that Error Injection for TX125 FSM Parity is enabled.

Values:

• 0x0(DISABLE): Tx125 FSM Parity Error Injection is disabled
• 0x1(ENABLE): Tx125 FSM Parity Error Injection is enabled

This field when set indicates that Error Injection for PTP FSM Parity is enabled.

Values:

• 0x0(DISABLE): PTP FSM Parity Error Injection is disabled
• 0x1(ENABLE): PTP FSM Parity Error Injection is enabled

This field when set indicates that Error Injection for APP FSM Parity is enabled.

Values:

• 0x0(DISABLE): APP FSM Parity Error Injection is disabled
• 0x1(ENABLE): APP FSM Parity Error Injection is enabled

This field when set indicates that Error Injection for CSR Parity is enabled.

Values:

• 0x0(DISABLE): CSR FSM Parity Error Injection is disabled
• 0x1(ENABLE): CSR FSM Parity Error Injection is enabled

This field when set indicates that Error Injection for RX FSM Parity is enabled.

Values:

• 0x0(DISABLE): Rx FSM Parity Error Injection is disabled
• 0x1(ENABLE): Rx FSM Parity Error Injection is enabled

This field when set indicates that Error Injection for TX FSM Parity is enabled.

Values:

• 0x0(DISABLE): Tx FSM Parity Error Injection is disabled
• 0x1(ENABLE): Tx FSM Parity Error Injection is enabled

This field when set indicates that Error Injection for REVMII MDC FSM timeout is enabled.

Values:

• 0x0(DISABLE): REV MDC FSM Timeout Error Injection is disabled
• 0x1(ENABLE): REV MDC FSM Timeout Error Injection is enabled

This field when set indicates that Error Injection for RX125 FSM timeout is enabled.

Values:

• 0x0(DISABLE): Rx125 FSM Timeout Error Injection is disabled
• 0x1(ENABLE): Rx125 FSM Timeout Error Injection is enabled

This field when set indicates that Error Injection for TX125 FSM timeout is enabled.

Values:

• 0x0(DISABLE): Tx125 FSM Timeout Error Injection is disabled
• 0x1(ENABLE): Tx125 FSM Timeout Error Injection is enabled

This field when set indicates that Error Injection for PTP FSM timeout is enabled.

Values:

• 0x0(DISABLE): PTP FSM Timeout Error Injection is disabled
• 0x1(ENABLE): PTP FSM Timeout Error Injection is enabled

This field when set indicates that Error Injection for APP FSM timeout is enabled.

Values:

• 0x0(DISABLE): APP FSM Timeout Error Injection is disabled
• 0x1(ENABLE): APP FSM Timeout Error Injection is enabled

This field when set indicates that Error Injection for CSR timeout is enabled.

Values:

• 0x0(DISABLE): CSR FSM Timeout Error Injection is disabled
• 0x1(ENABLE): CSR FSM Timeout Error Injection is enabled

This field when set indicates that Error Injection for RX FSM timeout is enabled.

Values:

• 0x0(DISABLE): Rx FSM Timeout Error Injection is disabled
• 0x1(ENABLE): Rx FSM Timeout Error Injection is enabled

This field when set indicates that Error Injection for TX FSM timeout is enabled.

Values:

• 0x0(DISABLE): Tx FSM Timeout Error Injection is disabled
• 0x1(ENABLE): Tx FSM Timeout Error Injection is enabled

Values:

• 0x0(DISABLE): FSM Parity feature is disabled
• 0x1(ENABLE): FSM Parity feature is enabled

Values:

• 0x0(DISABLE): FSM timeout feature is disabled
• 0x1(ENABLE): FSM timeout feature is enabled

Value After Reset: 0x0

Exists: Always

This field provides the mode value to be used for large mode FSM and other interface time outs. The timeout duration is based on the mode value.

Values:

• 0x0(DISABLE): Timer disabled
• 0x1(M_1MICRO_SEC): 1us
• 0x2(M_4MILLI_SEC): 1.024ms (~4ms)
• 0x3(M_16MILLI_SEC): 16.384ms (~16ms)
• 0x4(M_64MILLI_SEC): 65.536ms (~64ms)
• 0x5(M_256MILLI_SEC): 262.144ms (~256ms)
• 0x6(M_1SEC): 1.048sec (~1sec)
• 0x7(M_4SEC): 4.194sec (~4sec)
• 0x8(M_16SEC): 16.777sec (~16sec)
• 0x9(M_32SEC): 33.554sec (~32sec)
• 0xa(M_64SEC): 67.108sec (~64sec)
• 0xb(RSVD): Reserved

This field provides the value to be used for normal mode FSM and other interface time outs. The timeout duration is based on the mode value.

Values:

• 0x0(DISABLE): Timer disabled
• 0x1(M_1MICRO_SEC): 1us
• 0x2(M_4MILLI_SEC): 1.024ms (~4ms)
• 0x3(M_16MILLI_SEC): 16.384ms (~16ms)
• 0x4(M_64MILLI_SEC): 65.536ms (~64ms)
• 0x5(M_256MILLI_SEC): 262.144ms (~256ms)
• 0x6(M_1SEC): 1.048sec (~1sec)
• 0x7(M_4SEC): 4.194sec (~4sec)
• 0x8(M_16SEC): 16.777sec (~16sec)
• 0x9(M_32SEC): 33.554sec (~32sec)
• 0xa(M_64SEC): 67.108sec (~64sec)
• 0xb(RSVD): Reserved

CSR Clocks for 1us Tic

This field indicates the number of CSR clocks required to generate 1us tic.

When this bit is set, the SMA suppresses the 32-bit preamble and transmits MDIO frames with only 1 preamble bit. When this bit is 0, the MDIO frame always has 32 bits of preamble as defined in the IEEE specifications.

Values:

• 0x0(DISABLE): Preamble Suppression disabled
• 0x1(ENABLE): Preamble Suppression enabled

When this bit is set and the NTC has value greater than 0, then the MAC informs the completion of a read or write command at the end of frame transfer (before the trailing clocks are transmitted). The software can thus initiate the next command which is executed immediately irrespective of the number trailing clocks generated for the previous frame. When this bit is reset, then the read/write command completion (GB is cleared) only after the trailing clocks are generated. In this mode, it is ensured that the NTC is always generated after each frame. This bit must not be set when NTC=0.

Values:

• 0x0(DISABLE): Back to Back transactions disabled
• 0x1(ENABLE): Back to Back transactions enabled

This field indicates which Clause 22 PHY devices (out of 32 devices) the MAC is accessing. For RevMII, this field gives the PHY Address of the RevMII module. This field indicates which Clause 45 capable PHYs (out of 32 PHYs) the MAC is accessing.

Testable: Untestable

These bits select the PHY register in selected Clause 22 PHY device. For RevMII, these bits select the CSR register in the RevMII Registers set. These bits select the Device (MMD) in selected Clause 45 capable PHY.

This field controls the number of trailing clock cycles generated on gmii_mdc_o (MDC) after the end of transmission of MDIO frame. The valid values can be from 0 to 7.

Programming the value to 3'h3 indicates that there are additional three clock cycles on the MDC line after the end of MDIO frame transfer.

The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design:

• 0000:CSR clock = 60-100 MHz; MDC clock = CSR clock/42
• 0001: CSRclock = 100-150 MHz; MDC clock = CSR clock/62
• 0010:CSR clock = 20-35 MHz; MDC clock = CSR clock/16
• 0011:CSR clock = 35-60 MHz; MDC clock = CSR clock/26
• 0100: CSRclock = 150-250 MHz; MDC clock = CSR clock/102
• 0101: CSRclock = 250-300 MHz; MDC clock = CSR clock/124
• 0110: CSRclock = 300-500 MHz; MDC clock = CSR clock/204
• 0111: CSRclock = 500-800 MHz; MDC clock = CSR clock/324

The suggested range of CSR clock frequency applicable for each value (when Bit 11 = 0) ensures that the MDC clock is approximately between 1.0 MHz to 2.5 MHz frequency range. When Bit 11 is set, you can achieve a higher frequency of the MDC clock than the frequency limit of 2.5 MHz (specified in the IEEE 802.3) and program a clock divider of lower value. For example, when CSR clock is of 100 MHz frequency and you program these bits as 1010, the resultant MDC clock is of 12.5 MHz which is beyond the range specified in IEEE 802.3.

Program the following values only if the interfacing chips support faster MDC clocks:

• 1000:CSR clock/4
• 1001:CSR clock/6
• 1010:CSR clock/8
• 1011:CSR clock/10
• 1100:CSR clock/12
• 1101:CSR clock/14
• 1110:CSR clock/16
• 1111:CSR clock/18

These bits are not used for accessing RevMII. These bits are read-only if the RevMII interface is selected as single PHY interface.

When this bit is set, the SMA does not send the address packets before read, write, or post-read increment address packets. This bit is valid only when C45E is set.

Values:

• 0x0(DISABLE): Skip Address Packet is disabled
• 0x1(ENABLE): Skip Address Packet is enabled

This bit is higher bit of the operation command to the PHY or RevMII, GOC_1 and GOC_O is encoded as follows:

• 00: Reserved
• 01: Write
• 10: Post Read Increment Address for Clause 45 PHY
• 11: Read

When Clause22 PHY or RevMII is enabled, only Write and Read commands are valid.

Values:

• 0x0(DISABLE): GMII Operation Command 1 is disabled
• 0x1(ENABLE): GMII Operation Command 1 is enabled

This is the lower bit of the operation command to the PHY or RevMII. When in SMA mode (MDIO master) this bit along with GOC_1 determines the operation to be performed to the PHY.

When only RevMII is selected in configuration this bit is read-only and tied to 1.

Values:

• 0x0(DISABLE): GMII Operation Command 0 is disabled
• 0x1(ENABLE): GMII Operation Command 0 is enabled

When this bit is set, Clause 45 capable PHY is connected to MDIO. When this bit is reset, Clause 22 capable PHY is connected to MDIO.

Values:

• 0x0(DISABLE): Clause 45 PHY is disabled
• 0x1(ENABLE): Clause 45 PHY is enabled

The application sets this bit to instruct the SMA to initiate a Read or Write access to the MDIO slave. The MAC clears this bit after the MDIO frame transfer is completed. Hence the software must not write or change any of the fields in MAC_MDIO_Address and MAC_MDIO_Data registers as long as this bit is set.

For write transfers, the application must first write 16-bit data inthe GDl field (and also RA field when C45E is set) in MAC_MDIO_Data register before setting this bit. When C45E is set, it should also write into the RA field of MAC_MDIO_Data register before initiating a read transfer.

When aread transfer is completed (GB=0), the data read from the PHY register is valid in the GD field of the MAC_MDIO_Data register.

Values:

• 0x0(DISABLE): GMII Busy is disabled
• 0x1(ENABLE): GMII Busy is enabled

This field is valid only when C45E is set. It contains the Register Address in the PHY to which the MDIO frame is intended for.

This field contains the 16-bit data value read from the PHYor RevMII after a Management Read operation or the 16-bit data value to be written to the PHY or RevMII before a Management Write operation.

When this bit is set, it indicates that the corresponding GPIS bit in MAC_GPIO_Status register is of latched-low (LL) type. When this bit is reset, it indicates that the corresponding GPIS is of latched-high (LH) type.

The number of bits available in this field depends on the GP Input Signal Width option. Other bits are not used (reserved and always reset).

When this bit is set and the programmed event (LL or LH) occurs on the corresponding GPIS bit of MAC_GPIO_Status register, the GPIIS bit of DMA_Interrupt_Status register is set and an interrupt is generated on the mci_intr_o or sbd_intr_o signal. The GPIIS bit is cleared when the application reads the Bits[7:0] of MAC_GPIO_Status register.

When this bit is reset, the GPIIS bit is not set when any event occurs on the corresponding GPIS bits.

When this bit is set, it directly drives the gpo_o output ports. When this bit is reset, it does not directly drive the gpo_o output ports.

The number of bits available in this field depends on the GP Input Signal Width option. Other bits are not used (reserved and always reset).

This field gives the status of the signals connected to the gpi_i port. This field is of the following types based on the setting of the corresponding GPIT field of MAC_GPIO_Control register:

• Latched-low (LL): This field is cleared when the corresponding gpi_i input becomes low. This field remains low until the application reads this field after which this field reflects the current value of gpi_i input.
• Latched-high (LH): This field is set when the corresponding gpi_i input becomes high. This field remains high until the application reads this field after which this field reflects the current value of gpi_i input.

The number of bits available in this field depends on the GP Input Signal Width option. Other bits are not used (reserved and always reset).

This field contains the IPv4 Destination Address of the MAC. This address is used for perfect match with the Protocol Address of Target field in the received ARP packet.

This field is available only when the Enable IPv4 ARP Offload option is selected.

When this bit is set, the MAC responds with Slave Error for accesses to reserved registers in CSR space.

When this bit is reset, the MAC responds with Okay response to any register accessed from CSR space.

Values:

• 0x0(DISABLE): Slave Error Response is disabled
• 0x1(ENABLE): Slave Error Response is enabled

When this bit is set, the access mode of some register fields changes to Clear on Write 1, the application needs to set that respective bit to 1 to clear it.

When this bit is reset, the access mode of these register fields remain as Clear on Read.

Values:

• 0x0(DISABLE): Register Clear on Write 1 is disabled
• 0x1(ENABLE): Register Clear on Write 1 is enabled

Transmitted Respond Frame

Set when a Respond mPacket is transmitted (triggered by setting SRSP field). An interrupt can be generated for this event if FPEIE bit of MAC_Interrupt_Enable is set.

Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): Not transmitted Respond Frame
• 0x1(ACTIVE): transmitted Respond Frame

Transmitted Verify Frame

Set when a Verify mPacket is transmitted (triggered by setting SVER field). An interrupt can be generated for this event if FPEIE bit of MAC_Interrupt_Enable is set.

Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): Not transmitted Verify Frame
• 0x1(ACTIVE): Transmitted Verify Frame

Set when a Respond mPacket is received. An interrupt can be generated for this event if FPEIE bit of MAC_Interrupt_Enable is set.

Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): Not received Respond Frame
• 0x1(ACTIVE): Received Respond Frame

Set when a Verify mPacket is received. An interrupt can be generated for this event if FPEIE bit of MAC_Interrupt_Enable is set.

Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): Not received Verify Frame
• 0x1(ACTIVE): Received Verify Frame

This field is reserved for Synopsys Internal use, and must always be set to "0" unless instructed by Synopsys.

Setting to "1"might cause unexpected behavior in the IP.

When set indicates hardware to send a Respond mPacket. Reset by hardware after sending the Respond mPacket.

Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect.

Values:

• 0x0(DISABLE): Send Respond mPacket is disabled
• 0x1(ENABLE): Send Respond mPacket is enabled

When set indicates hardware to send a verify mPacket. Reset by hardware after sending the Verify mPacket.

Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect.

Values:

• 0x0(DISABLE): Send Verify mPacket is disabled
• 0x1(ENABLE): Send Verify mPacket is enabled

When set Frame Preemption Tx functionality is enabled.

Values:

• 0x0(DISABLE): Tx Frame Preemption is disabled
• 0x1(ENABLE): Tx Frame Preemption is enabled

• When this bit is set to 1, and the received packet is an AV Type packet, the header is split at SAVO bytes from the beginning of Length/Type field of the packet, for L2 Split.
• When this bit is set to 0,header is split at SPLOFST bytes from the beginning of Length/Type field of the frame, for L2 Split.

When SAVE bit is set to 1, and the received packet is an AV Type packet, these bits indicate the value of the offset from the beginning of Length/Type field at which header should be split, when appropriate SPLM is selected. The reset value of this field is 2 bytes, indicating a split at L2 header. Value is in terms of bytes.

These bits indicate the mode of splitting the incoming Rx packets. They are

• 0x0(L3L4): Split at L3/L4 header
• 0x1(L2OFST): Split at L2 header with an offset. Always Split at SPLOFST bytes from the beginning of Length/Type field of the Frame
• 0x2(COMBN): Combination mode: Split similar to SPLM=00 for IP packets that are untagged or tagged and VLAN stripped
• 0x3(RSVD): Reserved

These bits indicate the value of offset from the beginning of Length/Type field at which header split should take place when the appropriate SPLM is selected. The reset value of this field is 2 bytes indicating a split at L2 header. Value is in terms of bytes.

These bits indicate the value of the 32-bit binary rollover equivalent time of the PTP System Time in ns

This field holds the init value or the update value for the presentation time. When used for update, this field holds the 32-bit value in ns, that should be added to the Current Presentation Time Counter value. Init happens when TSINIT is set, and update happens when the TSUPDT bit is set (TSINIT and TSINIT defined in MAC_Timestamp_Control register).

When ADDSUB field of MAC_System_Time_Nanoseconds_Update is set, this value is directly used for subtraction

This bit is always set to 1.

Values:

• 0x0(DISABLE): INVALID: This bit must be always set to 1
• 0x1(ENABLE): This bit is always set to 1

If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address0 content is routed.

This field contains the one-hot representation of one or more DMA Channel numbers to which an Rx packet whose DA matches the MAC Address0 content is routed.

This field contains the upper 16bits [47:32] of the first 6-byte MAC address. The MAC uses this field for filtering the received packets and inserting the MAC address in the Transmit Flow Control (Pause) Packets.

This field contains the lower 32 bits of the first 6-byte MAC address. The MAC uses this field for filtering the received packets and inserting the MAC address in the Transmit Flow Control (Pause) Packets.

When set, the MAC updates all related MMC Counters for Broadcast packets that are dropped because of the setting of the DBF bit of MAC_Packet_Filter register.

When reset, the MMC Counters are not updated for dropped Broadcast packets.

Values:

• 0x0(DISABLE): Update MMC Counters for Dropped Broadcast Packets is disabled
• 0x1(ENABLE): Update MMC Counters for Dropped Broad- cast Packets is enabled

When this bit is low and the CNTPRST bit is set, all MMC counters get preset to almost-half value. All octet counters get preset to 0x7FFF_F800 (Half 2KBytes) and all packet-counters get preset to0x7FFF_FFF0 (Half 16). When this bit is high and the CNTPRST bit is set, all MMC counters get preset to almost-full value. All octet counters get preset to 0xFFFF_F800 (Full 2KBytes) and all packet-counters gets preset to 0xFFFF_FFF0 (Full 16).

For 16-bit counters, the almost-half preset values are 0x7800 and 0x7FF0 for the respective octet and packet counters.

Similarly, the almost-full preset values for the 16-bit counters are 0xF800 and 0xFFF0.

Values:

• 0x0(DISABLE): Full-Half Preset is disabled
• 0x1(ENABLE): Full-Half Preset is enabled

When this bit is set, all counters are initialized or preset to almost full or almost half according to the CNTPRSTLVL bit. This bit is cleared automatically after 1 clock cycle.

This bit, along with the CNTPRSTLVL bit, is useful for debugging and testing the assertion of interrupts because of MMC counter becoming half-full or full.

Access restriction applies. Self-cleared. Setting 0 clears. Setting 1 sets.

Values:

• 0x0(DISABLE): Counters Preset is disabled
• 0x1(ENABLE): Counters Preset is enabled

When this bit is set, it freezes all MMC counters to their current value.

Until this bit is reset to 0, no MMC counter is updated because of any transmitted or received packet. If any MMC counter is read with the Reset on Read bit set, then that counter is also cleared in this mode.

Values:

• 0x0(DISABLE): MMC Counter Freeze is disabled
• 0x1(ENABLE): MMC Counter Freeze is enabled

When this bit is set, the MMC counters are reset to zero after Read (self-clearing after reset). The counters are cleared when the least significant byte lane (Bits[7:0]) is read.

Values:

• 0x0(DISABLE): Reset on Read is disabled
• 0x1(ENABLE): Reset on Read is enabled

When this bit is set, the counter does not roll over to zero after reaching the maximum value.

Values:

• 0x0(DISABLE): Counter Stop Rollover is disabled
• 0x1(ENABLE): Counter Stop Rollover is enabled

When this bit is set, all counters are reset. This bit is cleared automatically after 1 clock cycle.

Access restriction applies. Self-cleared. Setting 0 clears. Setting 1 sets.

Values:

• 0x0(DISABLE): Counters are not reset
• 0x1(ENABLE): All counters are reset

This bit is set when the Rx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Receive LPI transition Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Receive LPI transition Counter Interrupt Status detected

This bit is set when the Rx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Receive LPI microsecond Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Receive LPI microsecond Counter Interrupt Status detected

This bit is set when the rxctrlpackets_g counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Receive Control Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Receive Control Packet Counter Interrupt Status detected

This bit is set when the rxrcverror counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Receive Error Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Receive Error Packet Counter Inter- rupt Status detected

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Receive Watchdog Error Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Receive Watchdog Error Packet Counter Interrupt Status detected

This bit is set when the rxvlanpackets_gb counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Receive VLAN Good Bad Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Receive VLAN Good Bad Packet Counter Interrupt Status detected

MMC Receive FIFO Overflow Packet Counter Interrupt Status This bit is set when the rxfifo overflow counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Receive FIFO Overflow Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Receive FIFO Overflow Packet Counter Interrupt Status detected

This bit is set when the rxpause packets counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Receive Pause Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Receive Pause Packet Counter Interrupt Status detected

This bit is set when the rx out of range type counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Receive Out Of Range Error Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Receive Out Of Range Error Packet Counter Interrupt Status detected

This bit is set when the rx length error counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Receive Length Error Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Receive Length Error Packet Counter Interrupt Status detected

This bit is set when the rx unicastpackets_g counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Receive Unicast Good Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Receive Unicast Good Packet Counter Interrupt Status detected

This bit is set when the rx1024 to maxoctets_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status detected

This bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status detected

This bit is set when the rx256to511 octets_gb counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status detected

This bit is set when the rx128to 255octets_gb counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status detected

This bit is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status detected

MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status

This bit is set when the rx64octets_gb counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status detected

Counter Interrupt Status This bit is set when the rxoversize_g counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Receive Oversize Good Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Receive Oversize Good Packet Counter Interrupt Status detected

This bit is set when the rxundersize_g counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Receive Undersize Good Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Receive Undersize Good Packet Counter Interrupt Status detected

MMC Receive Jabber Error Packet Counter Interrupt Status This bit is set when the rxjabbererror counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Receive Jabber Error Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Receive Jabber Error Packet Counter Interrupt Status detected

MMC Receive Runt Packet Counter Interrupt Status

This bit is set when the rxrunterror counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Receive Runt Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Receive Runt Packet Counter Interrupt Status detected

MMC Receive Alignment Error Packet Counter Interrupt Status This bit is set when the rxalignmenterror counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Receive Alignment Error Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Receive Alignment Error Packet Counter Interrupt Status detected

MMC Receive CRC Error Packet Counter Interrupt Status This bit is set when the rxcrcerror counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Receive CRC Error Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Receive CRC Error Packet Counter Interrupt Status detected

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Receive Multicast Good Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Receive Multicast Good Packet Counter Interrupt Status detected

This bit is set when the rxbroadcastpackets_g counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Receive Broadcast Good Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Receive Broadcast Good Packet Counter Interrupt Status detected

This bit is set when the rxoctetcount_g counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Receive Good Octet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Receive Good Octet Counter Interrupt Status detected

This bit is set when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Receive Good Bad Octet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Receive Good Bad Octet Counter Interrupt Status detected

This bit is set when the rxpacketcount_gb counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Receive Good Bad Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Receive Good Bad Packet Counter Interrupt Status detected

This bit is set when the Tx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Transmit LPI transition Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Transmit LPI transition Counter Inter- rupt Status detected

This bit is set when the Tx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Transmit LPI microsecond Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Transmit LPI microsecond Counter Interrupt Status detected

This bit is set when the txoversize_g counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Transmit Oversize Good Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Transmit Oversize Good Packet Counter Interrupt Status detected

This bit is set when the txvlanpackets_g counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Transmit VLAN Good Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Transmit VLAN Good Packet Counter Interrupt Status detected

This bit is set when the txpausepacketserror counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Transmit Pause Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Transmit Pause Packet Counter Interrupt Status detected

This bit is set when the txexcessdef counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Transmit Excessive Deferral Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Transmit Excessive Deferral Packet Counter Interrupt Status detected

This bit is set when the txpacketcount_g counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Transmit Good Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Transmit Good Packet Counter Interrupt Status detected

This bit is set when the txoctetcount_g counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Transmit Good Octet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Transmit Good Octet Counter Interrupt Status detected

This bit is set when the txcarriererror counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Transmit Carrier Error Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Transmit Carrier Error Packet Counter Interrupt Status detected

This bit is set when the txexesscol counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Transmit Excessive Collision Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Transmit Excessive Collision Packet Counter Interrupt Status detected

This bit is set when the txlatecol counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Transmit Late Collision Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Transmit Late Collision Packet Counter Interrupt Status detected

This bit is set when the txdeferred counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Transmit Deferred Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Transmit Deferred Packet Counter Interrupt Status detected

This bit is set when the txmulticol_g counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Transmit Multiple Collision Good Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Transmit Multiple Collision Good Packet Counter Interrupt Status detected

This bit is set when the txsinglecol_g counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Transmit Single Collision Good Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Transmit Single Collision Good Packet Counter Interrupt Status detected

This bit is set when the txunderflowerror counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Transmit Underflow Error Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Transmit Underflow Error Packet Counter Interrupt Status detected

This bit is set when the txbroadcastpackets_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status detected

The bit is set when the txmulticastpackets_gb counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Transmit Multicast Good Bad Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Transmit Multicast Good Bad Packet Counter Interrupt Status detected

This bit is set when the txunicastpackets_gb counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Transmit Unicast Good Bad Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Transmit Unicast Good Bad Packet Counter Interrupt Status detected

This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status detected

This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status detected

This bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status detected

This bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status detected

MMC Transmit 65to 127 Octet Good Bad Packet Counter Interrupt Status

This bit is set when the tx65to127octets_gb counter reaches half the maximum value, and also when it reaches the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status detected

MMC Transmit 64Octet Good Bad Packet Counter Interrupt Status

This bit is set when the tx64octets_gb counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status detected

This bit is set when the txmulticastpackets_g counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Transmit Multicast Good Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Transmit Multicast Good Packet Counter Interrupt Status detected

This bit is set when the txbroadcastpackets_g counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Transmit Broadcast Good Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Transmit Broadcast Good Packet Counter Interrupt Status detected

This bit is set when the txpacketcount_gb counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Transmit Good Bad Packet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Transmit Good Bad Packet Counter Interrupt Status detected

This bit is set when the txoctetcount_gb counter reaches half of the maximum value or the maximum value.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): MMC Transmit Good Bad Octet Counter Interrupt Status not detected
• 0x1(ACTIVE): MMC Transmit Good Bad Octet Counter Interrupt Status detected

MMC Receive LPI transition counter interrupt Mask Setting this bit masks the interrupt when the

Rx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value.

Values:

• 0x0(DISABLE): MMC Receive LPI transition counter interrupt Mask is disabled
• 0x1(ENABLE): MMC Receive LPI transition counter interrupt Mask is enabled

Setting this bit masks the interrupt when the Rx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value.

Values:

• 0x0(DISABLE): MMC Receive LPI microsecond counter interrupt Mask is disabled
• 0x1(ENABLE): MMC Receive LPI microsecond counter interrupt Mask is enabled

Setting this bit masks the interrupt when the rxctrlpackets_g counter reaches half of the maximum value or the maximum value.

Values:

• 0x0(DISABLE): MMC Receive Control Packet Counter Interrupt Mask is disabled
• 0x1(ENABLE): MMC Receive Control Packet Counter Interrupt Mask is enabled

Setting this bit masks the interrupt when the rxrcverror counter reaches half of the maximum value or the maximum value.

Values:

• 0x0(DISABLE): MMC Receive Error Packet Counter Interrupt Mask is disabled
• 0x1(ENABLE): MMC Receive Error Packet Counter Interrupt Mask is enabled

Setting this bit masks the interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value.

Values:

• 0x0(DISABLE): MMC Receive Watchdog Error Packet Counter Interrupt Mask is disabled
• 0x1(ENABLE): MMC Receive Watchdog Error Packet Counter Interrupt Mask is enabled

Setting this bit masks the interrupt when the rxvlanpackets_gb counter reaches half of the maximum value or the maximum value.

Values:

• 0x0(DISABLE): MMC Receive VLAN Good Bad Packet Counter Interrupt Mask is disabled
• 0x1(ENABLE): MMC Receive VLAN Good Bad Packet Counter Interrupt Mask is enabled

Setting this bit masks the interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value.

Values:

• 0x0(DISABLE): MMC Receive FIFO Overflow Packet Counter Interrupt Mask is disabled
• 0x1(ENABLE): MMC Receive FIFO Overflow Packet Counter Interrupt Mask is enabled

Setting this bit masks the interrupt when the rxpausepackets counter reaches half of the maximum value or the maximum value.

Values:

• 0x0(DISABLE): MMC Receive Pause Packet Counter Interrupt Mask is disabled
• 0x1(ENABLE): MMC Receive Pause Packet Counter Interrupt Mask is enabled

Setting this bit masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the maximum value.

Values:

• 0x0(DISABLE): MMC Receive Out Of Range Error Packet Counter Interrupt Mask is disabled
• 0x1(ENABLE): MMC Receive Out Of Range Error Packet Counter Interrupt Mask is enabled

Setting this bit masks the interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value.

Values:

• 0x0(DISABLE): MMC Receive Length Error Packet Counter Interrupt Mask is disabled
• 0x1(ENABLE): MMC Receive Length Error Packet Counter Interrupt Mask is enabled

Setting this bit masks the interrupt when the rxunicastpackets_g counter reaches half of the maximum value or the maximum value.

Values:

• 0x0(DISABLE): MMC Receive Unicast Good Packet Counter Interrupt Mask is disabled
• 0x1(ENABLE): MMC Receive Unicast Good Packet Counter Interrupt Mask is enabled

Setting this bit masks the interrupt when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value.

Values:

• 0x0(DISABLE): MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is disabled
• 0x1(ENABLE): MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is enabled

Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value.

Values:

• 0x0(DISABLE): MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is disabled
• 0x1(ENABLE): MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is enabled

Setting this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value.

Values:

• 0x0(DISABLE): MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is disabled
• 0x1(ENABLE): MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is enabled

Setting this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value.

Values:

• 0x0(DISABLE): MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is disabled
• 0x1(ENABLE): MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is enabled

Setting this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value.

Values:

• 0x0(DISABLE): MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is disabled
• 0x1(ENABLE): MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is enabled

Setting this bit masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the maximum value.

Values:

• 0x0(DISABLE): MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask is disabled
• 0x1(ENABLE): MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask is enabled

Setting this bit masks the interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum value.

Values:

• 0x0(DISABLE): MMC Receive Oversize Good Packet Counter Interrupt Mask is disabled
• 0x1(ENABLE): MMC Receive Oversize Good Packet Counter Interrupt Mask is enabled

Setting this bit masks the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum value.

Values:

• 0x0(DISABLE): MMC Receive Undersize Good Packet Counter Interrupt Mask is disabled
• 0x1(ENABLE): MMC Receive Undersize Good Packet Counter Interrupt Mask is enabled

Setting this bit masks the interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value.

Values:

• 0x0(DISABLE): MMC Receive Jabber Error Packet Counter Interrupt Mask is disabled
• 0x1(ENABLE): MMC Receive Jabber Error Packet Counter Interrupt Mask is enabled

Setting this bit masks the interrupt when the rxrunterror counter reaches half of the maximum value or the maximum value.

Values:

• 0x0(DISABLE): MMC Receive Runt Packet Counter Interrupt Mask is disabled
• 0x1(ENABLE): MMC Receive Runt Packet Counter Interrupt Mask is enabled

Setting this bit masks the interrupt when the rxalignmenterror counter reaches half of the maximum value or the maximum value.

Values:

• 0x0(DISABLE): MMC Receive Alignment Error Packet Counter Interrupt Mask is disabled
• 0x1(ENABLE): MMC Receive Alignment Error Packet Counter Interrupt Mask is enabled

Setting this bit masks the interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value.

Values:

• 0x0(DISABLE): MMC Receive CRC Error Packet Counter Interrupt Mask is disabled
• 0x1(ENABLE): MMC Receive CRC Error Packet Counter Interrupt Mask is enabled

Setting this bit masks the interrupt when the rxmulticastpackets_g counter reaches half of the maximum value or the maximum value.

Values:

• 0x0(DISABLE): MMC Receive Multicast Good Packet Counter Interrupt Mask is disabled
• 0x1(ENABLE): MMC Receive Multicast Good Packet Counter Interrupt Mask is enabled

Setting this bit masks the interrupt when the rxbroadcastpackets_g counter reaches half of the maximum value or the maximum value.

Values:

• 0x0(DISABLE): MMC Receive Broadcast Good Packet Counter Interrupt Mask is disabled
• 0x1(ENABLE): MMC Receive Broadcast Good Packet Counter Interrupt Mask is enabled

Setting this bit masks the interrupt when the rxoctetcount_g counter reaches half of the maximum value or the maximum value.

Values:

• 0x0(DISABLE): MMC Receive Good Octet Counter Interrupt Mask is disabled
• 0x1(ENABLE): MMC Receive Good Octet Counter Interrupt Mask is enabled

Setting this bit masks the interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value.

Values:

• 0x0(DISABLE): MMC Receive Good Bad Octet Counter Interrupt Mask is disabled
• 0x1(ENABLE): MMC Receive Good Bad Octet Counter Interrupt Mask is enabled

Setting this bit masks the interrupt when the rxpacketcount_gb counter reaches half of the maximum value or the maximum value.

Values:

• 0x0(DISABLE): MMC Receive Good Bad Packet Counter Interrupt Mask is disabled
• 0x1(ENABLE): MMC Receive Good Bad Packet Counter Interrupt Mask is enabled

Setting this bit masks the interrupt when the Tx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value.

Values:

• 0x0(DISABLE): MMC Transmit LPI transition counter interrupt Mask is disabled
• 0x1(ENABLE): MMC Transmit LPI transition counter interrupt Mask is enabled

Setting this bit masks the interrupt when the Tx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value.

Values:

• 0x0(DISABLE): MMC Transmit LPI microsecond counter interrupt Mask is disabled
• 0x1(ENABLE): MMC Transmit LPI microsecond counter interrupt Mask is enabled

Setting this bit masks the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum value.

Values:

• 0x0(DISABLE): MMC Transmit Oversize Good Packet Counter Interrupt Mask is disabled
• 0x1(ENABLE): MMC Transmit Oversize Good Packet Counter Interrupt Mask is enabled

Setting this bit masks the interrupt when the txvlanpackets_g counter reaches half of the maximum value or the maximum value.

Values:

• 0x0(DISABLE): MMC Transmit VLAN Good Packet Counter Interrupt Mask is disabled
• 0x1(ENABLE): MMC Transmit VLAN Good Packet Counter Interrupt Mask is enabled

Setting this bit masks the interrupt when the txpausepackets counter reaches half of the maximum value or the maximum value.

Values:

• 0x0(DISABLE): MMC Transmit Pause Packet Counter Interrupt Mask is disabled
• 0x1(ENABLE): MMC Transmit Pause Packet Counter Interrupt Mask is enabled

Setting this bit masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum value.

Values:

• 0x0(DISABLE): MMC Transmit Excessive Deferral Packet Counter Interrupt Mask is disabled
• 0x1(ENABLE): MMC Transmit Excessive Deferral Packet Counter Interrupt Mask is enabled

Setting this bit masks the interrupt when the txpacketcount_g counter reaches half of the maximum value or the maximum value.

Values:

• 0x0(DISABLE): MMC Transmit Good Packet Counter Interrupt Mask is disabled
• 0x1(ENABLE): MMC Transmit Good Packet Counter Interrupt Mask is enabled

Setting this bit masks the interrupt when the txoctetcount_g counter reaches half of the maximum value or the maximum value.

Values:

• 0x0(DISABLE): MMC Transmit Good Octet Counter Interrupt Mask is disabled
• 0x1(ENABLE): MMC Transmit Good Octet Counter Interrupt Mask is enabled