EQOS_MTL0 Registers

Reserved.

Transmit Queue Size

This field indicates the size of the allocated Transmit queues in blocks of 256 bytes. The TQS field is read-write only if the number of Tx Queues more than one, the reset value is 0x0 and indicates size of 256 bytes. This means that value of 0x0 = 256 bytes, 0x1 = 512 bytes and so on. So, program TQS [5:0]=6'b001111 to allocate queue size of 4096 (4K) bytes. In general, the size of the Queue = (TQS+1)*256 bytes.

When the number of Tx Queues is one, the field is read-only and the configured TX FIFO size in blocks of 256 bytes is reflected in the reset value.

The width of this field depends on the Tx memory size selected in your configuration. For example, if the memory size is 2048, the width of this field is 3 bits:

LOG2(2048/256) =LOG2(8) = 3 bits

Reserved.

Transmit Threshold Control

These bits control the threshold level of the MTL Tx Queue. The transmission starts when the packet size within the MTL Tx Queue is larger than the threshold. In addition, full packets with length less than the threshold are also transmitted. These bits are used only when the TSF bit is reset.

Values:

0x0(M_32BYTES): 32

0x1(M_64BYTES): 64

0x2(M_96BYTES): 96

0x3(M_128BYTES): 128

0x4(M_192BYTES): 192

0x5(M_256BYTES): 256

0x6(M_384BYTES): 384

0x7(M_512BYTES): 512

Transmit Queue Enable

This field is used to enable/disable the transmit queue 0.

• 2'b00: Not enabled
• 2'b01: Reserved
• 2'b10: Enabled
• 2'b11: Reserved

This field is Read Only in Single Queue configurations and Read Write in Multiple Queue configurations.

Note:In multiple Tx queues configuration, all the queues are disabled by default. Enable the Tx queue by programming this field.

Values:

• 0x0(DISABLE): Not enabled
• 0x1(EN_IF_AV): Enable in AV mode (Reserved in non-AV)
• 0x2(ENABLE): Enabled
• 0x3(RSVD2): Reserved

Transmit Store and Forward

When this bit is set,the transmission starts when a full packet resides in the MTL Tx queue. When this bit is set, the TTC values specified in Bits[6:4] of this register are ignored. This bit should be changed only when the transmission is stopped.

Values:

• 0x0(DISABLE): Transmit Store and Forward is disabled
• 0x1(ENABLE): Transmit Store and Forward is enabled

Flush Transmit Queue

When this bit is set, the Tx queue controller logic is reset to its default values. Therefore, all the data in the Tx queue is lost or flushed. This bit is internally reset when the flushing operation is complete. Until this bit is reset, you should not write to the MTL_TxQ1_Operation_Mode register. The data which is already accepted by the MAC transmitter is not flushed. It is scheduled for transmission and results in underflow and runt packet transmission.

Note:The flush operation is complete only when the Tx queue is empty and the application has accepted the pending Tx Status of all transmitted packets. To complete this flush operation, the PHY Tx clock (clk_tx_i) should be active.

Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect.

Values:

• 0x0(DISABLE): Flush Transmit Queue is disabled
• 0x1(ENABLE): Flush Transmit Queue is enabled

Reserved.

Overflow Bit for Underflow Packet Counter

This bit is set every time the Tx queue Underflow Packet Counter field overflows, that is, it has crossed the maximum count. In such a scenario, the overflow packet counter is reset to all-zeros and this bit indicates that the rollover happened. Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): Overflow not detected for Underflow Packet Counter
• 0x1(ACTIVE): Overflow detected for Underflow Packet Counter

Underflow Packet Counter

This field indicates the number of packets aborted by the controller because of Tx Queue Underflow. This counter is incremented each time the MAC aborts outgoing packet because of underflow. The counter is cleared when this register is read with mci_be_i[0] at 1'b1.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Reserved.

Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue.

When the DTXSTS bit of MTL_Operation_Mode register is set to 1, this field does not reflect the number of status words in Tx Status FIFO.

Reserved.

Number of Packets in the Transmit Queue

This field indicates the current number of packets in the Tx Queue.

When the DTXSTS bit of MTL_Operation_Mode register is set to 1, this field does not reflect the number of packets in the Transmit queue.

Reserved.

MTL Tx Status FIFO Full Status

When high, this bit indicates that the MTL Tx Status FIFO is full. Therefore, the MTL cannot accept any more packets for transmission.

Values:

• 0x0(INACTIVE): MTL Tx Status FIFO Full status is not detected
• 0x1(ACTIVE): MTL Tx Status FIFO Full status is detected

MTL Tx Queue Not Empty Status

When this bit is high, it indicates that the MTL Tx Queue is not empty and some data is left for transmission.

Values:

• 0x0(INACTIVE): MTL Tx Queue Not Empty status is not detected
• 0x1(ACTIVE): MTL Tx Queue Not Empty status is detected

MTL Tx Queue Write Controller Status

When high, this bit indicates that the MTL Tx Queue Write Controller is active, and it is transferring the data to the Tx Queue.

Values:

• 0x0(INACTIVE): MTL Tx Queue Write Controller status is not detected
• 0x1(ACTIVE): MTL Tx Queue Write Controller status is detected

MTL Tx Queue Read Controller Status

This field indicates the state of the Tx Queue Read Controller:

Values:

• 0x0(IDLE): Idle state
• 0x1(READ): Read state (transferring data to the MAC transmitter)
• 0x2(WAIT): Waiting for pending Tx Status from the MAC transmitter
• 0x3(FLUSH): Flushing the Tx queue because of the Packet Abort request from the MAC

Transmit Queue in Pause

When this bit is high and the Rx flow control is enabled, it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following:

• Reception of the PFC packet for the priorities assigned to the Tx Queue when PFC is enabled
• Reception of802.3x Pause packet when PFC is disabled

Values:

• 0x0(INACTIVE): Transmit Queue in Pause status is not detected
• 0x1(ACTIVE): Transmit Queue in Pause status is detected

Reserved.

Average Bits per Slot

This field contains the average transmitted bits per slot. When the DCB operation is enabled for Queue 0, this field is computed over every 10 million bit times slot (4 ms in 2500 Mbps; 10 ms in 1000 Mbps; 100 ms in 100 Mbps). The maximum value is 0x989680.

Reserved.

Quantum or Weights

When the DCB operation is enabled with DWRR algorithm for Queue 0 traffic, this field contains the quantum value in bytes to be added to credit during every queue scanning cycle. The maximum value is 0x1312D0 bytes.

When DCB operation is enabled with WFQ algorithm for Queue 0 traffic, this field contains the weight for this queue. The maximum value is 0x3FFF where weight of 0 indicates 100% bandwidth. Bits[20:14] must be written to zero. The higher the programmed weights lesser the bandwidth allocated for the particular Transmit Queue. This is because the weights are used to compute the packet finish time (weights * packet_size). Lesser the finish time, higher the probability of the packet getting scheduled first and using more bandwidth.

When DCB operation or generic queuing operation is enabled with WRR algorithm for Queue 0 traffic, this field contains the weight for this queue. The maximum value is 0x64.

Bits [20:7] must be written to zero.

Reserved.

Receive Queue Overflow Interrupt Enable

When this bit is set, the Receive Queue Overflow interrupt is enabled. When this bit is reset, the Receive Queue Overflow interrupt is disabled.

Values:

• 0x0(DISABLE): Receive Queue Overflow Interrupt is disabled
• 0x1(ENABLE): Receive Queue Overflow Interrupt is enabled

Reserved.

Receive Queue Overflow Interrupt Status

This bit indicates that the Receive Queue had an overflow while receiving the packet. If a partial packet is transferred to the application, the overflow status is set in RDES3[21]. This bit is cleared when the application writes 1 to this bit.

Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.

Values:

• 0x0(INACTIVE): Receive Queue Overflow Interrupt Status not detected
• 0x1(ACTIVE): Receive Queue Overflow Interrupt Status detected

Reserved.

Average Bits Per Slot Interrupt Enable

When this bit is set,the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated.

When this bit is cleared, the interrupt is not asserted for such an event.

Values:

• 0x0(DISABLE): Average Bits Per Slot Interrupt is disabled
• 0x1(ENABLE): Average Bits Per Slot Interrupt is enabled

Transmit Queue Underflow Interrupt Enable

When this bit is set, the Transmit Queue Underflow interrupt is enabled. When this bit is reset, the Transmit Queue Underflow interrupt is disabled.

Values:

• 0x0(DISABLE): Transmit Queue Underflow Interrupt Status is disabled
• 0x1(ENABLE): Transmit Queue Underflow Interrupt Status is enabled

Reserved.

Average Bits Per Slot Interrupt Status

When set, this bit indicates that the MAC has updated the ABS value. This bit is cleared when the application writes 1 to this bit.

Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.

Values:

• 0x0(INACTIVE): Average Bits Per Slot Interrupt Status not detected
• 0x1(ACTIVE): Average Bits Per Slot Interrupt Status detected

Transmit Queue Underflow Interrupt Status

This bit indicates that the Transmit Queue had an underflow while transmitting the packet. Transmission is suspended and an Underflow Error TDES3[2] is set. This bit is cleared when the application writes 1 to this bit.

Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.

Values:

• 0x0(INACTIVE): Transmit Queue Underflow Interrupt Status not detected
• 0x1(ACTIVE): Transmit Queue Underflow Interrupt Status detected

Reserved.

Receive Queue Size

This field indicates the size of the allocated Receive queues in blocks of 256 bytes. The RQS field is read-write only if the number of Rx Queues more than one, the reset value is 0x0 and indicates size of 256 bytes. This means that value of 0x0 = 256 bytes, 0x1 = 512 bytes and so on. So, program RQS [5:0]=6'b001111 to allocate queue size of 4096 (4K) bytes. In general, the size of the Queue = (RQS+1)*256 bytes.

When the number of Rx Queues is one, the field is read-only and the configured RX FIFO size in blocks of 256 bytes is reflected in the reset value.

The width of this field depends on the Rx memory size selected in your configuration. For example, if the memory size is 2048, the width of this field is 3 bits:

LOG2(2048/256) =LOG2(8) = 3 bits

Reserved.

Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes)

These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation:

• 0: Full minus 1KB, that is, FULL 1 KB
• 1: Full minus 1.5 KB,that is, FULL 1.5 KB
• 2: Full minus 2KB, that is, FULL 2 KB
• 3: Full minus 2.5 KB,that is, FULL 2.5 KB
• ...
• 62: Full minus 32 KB,that is, FULL 32 KB
• 63: Full minus 32.5 KB,that is, FULL 32.5 KB

The de-assertion is effective only after flow control is asserted. Note: The value must be programmed in such a way to make sure that the threshold is a positive number.

When the EHFC is set high, these values are applicable only when the Rx queue size determined by the RQS field of this register, is equal to or greater than 4 KB.

For a given queue size, the values ranges between 0 and the encoding for FULL minus (QSIZE - 0.5 KB) and all other values are illegal. Here the term FULL and QSIZE refers to the queue size determined by the RQS field of this register.

The width of this field depends on RX FIFO size selected during the configuration. Remaining bits are reserved and read only.

Reserved.

Threshold for Activating Flow Control (in half-duplex and full-duplex

These bits control the threshold (fill-level of Rx queue) at which the flow control is activated.

Enable Hardware Flow Control

When this bit is set, the flow control signal operation, based on the fill-level of Rx queue, is enabled. When reset, the flow control operation is disabled.

Values:

• 0x0(DISABLE): Hardware Flow Control is disabled
• 0x1(ENABLE): Hardware Flow Control is enabled

Disable Dropping of TCP/IP Checksum Error Packets

When this bit is set, the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine. Such packets have errors only in the encapsulated payload. There are no errors (including FCS error) in the Ethernet packet received by the MAC.

When this bit is reset,all error packets are dropped if the FEP bit is reset.

Values:

• 0x0(ENABLE): Dropping of TCP/IP Checksum Error Packets is enabled
• 0x1(DISABLE): Dropping of TCP/IP Checksum Error Packets is disabled

Receive Queue Store and Forward

When this bit is set, the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it, ignoring the RTC field of this register. When this bit is reset, the Rx queue operates in the Threshold (cut-through) mode, subject to the threshold specified by the RTC field of this register.

Values:

• 0x0(DISABLE): Receive Queue Store and Forward is disabled
• 0x1(ENABLE): Receive Queue Store and Forward is enabled

Forward Error Packets

When this bit is reset, the Rx queue drops packets with error status (CRC error, GMII_ER, watchdog timeout, or overflow). However, if the start byte (write) pointer of a packet is already transferred to the read controller side (in Threshold mode), the packet is not dropped.

When this bit is set,all packets except the runt error packets are forwarded to the application or DMA. If the RSF bit is set and the Rx queue overflows when a partial packet is written, the packet is dropped irrespective of the setting of this bit.

However, if the RSF bit is reset and the Rx queue overflows when a partial packet is written, a partial packet might be forwarded to the application or DMA.

Values:

• 0x0(DISABLE): Forward Error Packets is disabled
• 0x1(ENABLE): Forward Error Packets is enabled

Forward Undersized Good Packets

When this bit is set, the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes), including pad-bytes and CRC. When this bit is reset, the Rx queue drops all packets of less than 64 bytes, unless a packet is already transferred because of the lower value of Rx Threshold, for example, RTC = 01.

Values:

• 0x0(DISABLE): Forward Undersized Good Packets is disabled
• 0x1(ENABLE): Forward Undersized Good Packets is enabled

Reserved.

Receive Queue Threshold Control

These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold. In addition, full packets with length less than the threshold are automatically transferred.

This field is valid only when the RSF bit is zero. This field is ignored when the RSF bit is set to 1.

Values:

0x0(M_64BYTE): 64

0x1(M_32BYTE): 32

0x2(M_96BYTE): 96

0x3(M_128BYTE): 128

Reserved.

Missed Packet Counter Overflow Bit

When set, this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): Missed Packet Counter overflow not detected
• 0x1(ACTIVE): Missed Packet Counter overflow detected

Missed Packet Counter

This field indicates the number ofpackets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue. This counter is incremented each time the application issues ari_pkt_flush_i[] for this queue. This counter is reset when this register is read with mci_be_i[0] at 1b1.

In EQOS-DMA, EQOS-AXI, and EQOS-AHB configurations, This counter is incremented by 1 when the DMA discards the packet because of buffer unavailability.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Reserved.

Overflow Counter Overflow Bit

When set, this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Values:

• 0x0(INACTIVE): Overflow Counter overflow not detected
• 0x1(ACTIVE): Overflow Counter overflow detected

Overflow Packet Counter

This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow. This counter is incremented each time the DWC_ether_qos discards an incoming packet because of overflow. This counter is reset when this register is read with mci_be_i[0] at 1'b1.

Access restriction applies. Clears on read. Self-set to 1 on internal event.

Reserved.

Number of Packets in Receive Queue

This field indicates the current number of packets in the Rx Queue. The theoretical maximum value for this fields 256KB/16B = 16K Packets, that is, Max_Queue_Size/Min_Packet_Size.

Reserved.

MTL Rx Queue Fill-Level Status

This field gives the status of the fill-level of the Rx Queue:

Values:

• 0x0(EMPTY): Rx Queue empty
• 0x1(BLW_THR): Rx Queue fill-level below flow-control deactivate threshold
• 0x2(ABV_THR): Rx Queue fill-level above flow-control activate threshold
• 0x3(FULL): Rx Queue full

Reserved.

MTL Rx Queue Read Controller State

This field gives the state of the Rx queue Read controller:

Values:

• 0x0(IDLE): Idle state
• 0x1(READ_DATA): Reading packet data
• 0x2(READ_STS): Reading packet status (or timestamp)
• 0x3(FLUSH): Flushing the packet data and status

MTL Rx Queue Write Controller Active Status

When high, this bit indicates that the MTL Rx queue Write controller is active, and it is transferring a received packet to the Rx Queue.

Values:

• 0x0(INACTIVE): MTL Rx Queue Write Controller Active Status not detected
• 0x1(ACTIVE): MTL Rx Queue Write Controller Active Status detected

Reserved.

Receive Queue Packet Arbitration

When this bit is set, the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue.

When this bit is reset, the DWC_ether_qos drives the packet data to the ARI interface such that the following amount of data of currently-selected queue is transmitted before switching to other queue:

• PBL amount of data (indicated by ari_qN_pbl_i[]) or
• Complete data of a packet

The status and the timestamp are not a part of the PBL data. Therefore, the DWC_ether_qos drives the complete status (including timestamp status) during first PBL request for the packet (in store-and-forward mode) or the last PBL request for the packet (in Threshold mode).

Values:

• 0x0(DISABLE): Receive Queue Packet Arbitration is disabled
• 0x1(ENABLE): Receive Queue Packet Arbitration is enabled

Receive Queue Weight

This field indicates the weight assigned to the Rx Queue 0. This field needs to be programmed with one value less than the required weight, that is, reset value of 0 indicates weight of 1, value of 1 indicates weight of 2, and so on. The weight is used as the number of continuous PBL or packets requests (depending on the RXQ_FRM_ARBIT) allocated to the queue in one arbitration cycle.

Note:The change in value of RXQ_WEGT takes effect only after the completion of current service round or when there is change from RAA=SP to RAA=WSP algorithm. This approach is taken so that there is smooth transition. For the RXQ_WEGT value to take effect at the start, the MTL_RxQ(#i)_Control registers must be programmed before the MTL_Operation_Mode register.