EQOS_MTL Registers (Edit Done)

• 1: Enables Programmable Rx Parser
• 0: Disables Programmable Rx Parser

When the Rx parser is disabled when parsing is in progress, the Rx parser is disabled only after the current packet parsing complete.

When the Rx parser is enabled, the parser gets activated for the next packet.

Values:

• 0x0(DISABLE): Flexible Rx parser is disabled
• 0x1(ENABLE): Flexible Rx parser is enabled

When this bit is set to 0, packets encountering software programming errors (NPE/NVE/frame offset overflow errors) or incomplete parsing are forwarded to application with the corresponding Rx Parser status.

When this bit is set to 1, backward compatibility is maintained where all the specified packets are dropped (when RA is not set)

Values:

• 0x0(DISABLE): Flexible Rx parser, packet drop in case software error is disabled
• 0x1(ENABLE): Flexible Rx parser, packet drop in case software error is enabled

When this bit is set, all counters are reset. This bit is cleared automatically after 1 clock cycle.

If this bit is set along with CNT_PRESET bit, CNT_PRESET has precedence.

Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect.

Values:

• 0x0(DISABLE): Counters are not reset
• 0x1(ENABLE): All counters are reset

When this bit is set:

• MTL_TxQ[0-7]_Underflow register is initialized/preset to 12'h7F0.
• Missed Packet and Overflow Packet counters inMTL_RxQ[0-7]_Missed_Packet_Overflow_Cnt register is initialized/preset to 12'h7F0.

Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect.

Values:

• 0x0(DISABLE): Counters Preset is disabled
• 0x1(ENABLE): Counters Preset is enabled

This field indicates the algorithm for Tx scheduling:

Values:

• 0x0(WRR): WRR algorithm
• 0x1(WFQ): WFQ algorithm when DCB feature is selected. Otherwise, Reserved
• 0x2(DWRR): DWRR algorithm when DCB feature is selected. Otherwise, Reserved
• 0x3(SP): Strict priority algorithm

This field is used to select the arbitration algorithm for the Rx side.

• 0: Strict priority (SP). Queue 0 has the lowest priority and the last queue has the highest priority.
• 1:Weighted Strict Priority (WSP)

Values:

• 0x0(SP): Strict priority (SP)
• 0x1(WSP): Weighted Strict Priority (WSP)

• 1: Tx packet status received from the MAC is dropped in the MTL
• 0: Tx packet status received from the MAC is forwarded to the application

Values:

• 0x0(DISABLE): Drop Transmit Status is disabled
• 0x1(ENABLE): Drop Transmit Status is enabled

Reserved.

When EIEE or EIAEE bit of this register is set, the following are the errors inserted based on the value encoded in this field.

Values:

• 0x0(M_1BIT): Insert 1 bit error
• 0x1(M_2BIT): insert 2 bit errors

• 1: Enables the ECC address error injection feature
• 0: Disables the ECC address error injection feature

Values:

• 0x0(DISABLE): Disables the ECC address error injection
• 0x1(ENABLE): Enables the ECC address error injection

• 1: Enables the ECC error injection feature
• 0: Disables the ECC error injection feature

Values:

• 0x0(DISABLE): ECC Inject Error for Tx, Rx, TSO and DCACHE memories is disabled
• 0x1(ENABLE): ECC Inject Error for Tx, Rx, TSO and DCACHE memories is enabled

When this bit is set, an interrupt is generated when Transmit status is available in slave mode.

Values:

• 0x0(DISABLE): Transmit Packet Available Interrupt Status is disabled
• 0x1(ENABLE): Transmit Packet Available Interrupt Status is enabled

When this bit is set, an interrupt is generated when EOP of the received packet is written to the Rx FIFO.

Values:

• 0x0(DISABLE): Receive Packet Available Interrupt Status is disabled
• 0x1(ENABLE): Receive Packet Available Interrupt Status is enabled

This field indicates the FIFO selected for debug access.

Values:

• 0x0(TXFIFO): Tx FIFO
• 0x1(TXSTSFIFO): Tx Status FIFO (only read access when SLVMOD is set)/ DC Memory FIFO read-write access when DBGMOD is set
• 0x2(TSOFIFO): TSO FIFO (cannot be accessed when SLVMOD is set)
• 0x3(RXFIFO): Rx FIFO

When this bit is set, it enables the Write operation on selected FIFO when FIFO Debug Access is enabled.

This bit must not be written to 1 when FIFO Debug Access is not enabled, that is FDBGEN bit is 0.

Access restriction applies. Self-cleared. Setting 0 clears. Setting 1 sets.

Values:

• 0x0(DISABLE): FIFO Write is disabled
• 0x1(ENABLE): FIFO Write is enabled

When this bit is set, it enables the Read operation on selected FIFO when FIFO Debug Access is enabled.

This bit must not be written to 1 when FIFO Debug Access is not enabled, that is FDBGEN bit is 0.

Access restriction applies. Self-cleared. Setting 0 clears. Setting 1 sets.

Values:

• 0x0(DISABLE): FIFO Read is disabled
• 0x1(ENABLE): FIFO Read is enabled

When this bit is set,the pointers of the currently-selected FIFO are reset when FIFO Debug Access is enabled.

This bit must not be written to 1 when FIFO Debug Access is not enabled, that is FDBGEN bit is 0.

Access restriction applies. Self-cleared. Setting 0 clears. Setting 1 sets.

Values:

• 0x0(DISABLE): Reset Pointers of Selected FIFO is disabled
• 0x1(ENABLE): Reset Pointers of Selected FIFO is enabled

When this bit is set, the pointers of all FIFOs are reset when FIFO Debug Access is enabled.

This bit must not be written to 1 when FIFO Debug Access is not enabled, that is FDBGEN bit is 0.

Access restriction applies. Self-cleared. Setting 0 clears. Setting 1 sets.

Values:

• 0x0(DISABLE): Reset All Pointers is disabled
• 0x1(ENABLE): Reset All Pointers is enabled

This field is used to write the control information to the Tx FIFO or Rx FIFO.

• Tx FIFO:
  • 00: Packet Data
  • 01:Control Word
  • 10:SOP Data
  • 11:EOP Data
• Rx FIFO:
  • 00: Packet Data
  • 01: Normal Status
  • 10: Last Status
  • 11: EOP

Values:

• 0x0(PKT_DATA): Packet Data
• 0x1(CW_NS): Control Word/Normal Status
• 0x2(SOP_LS): SOP Data/Last Status
• 0x3(EOP): EOP Data/EOP

This field indicates the number of data bytes valid in the data register during Write operation. This is valid only when PKTSTATE is 2'b10 (EOP) and Tx FIFO or Rx FIFO is selected.

Values:

• 0x0(B0_VAL): Byte 0 valid
• 0x1(B01_VAL): Byte 0 and Byte 1 are valid
• 0x2(B012_VAL): Byte 0, Byte 1, and Byte 2 are valid
• 0x3(B0123_VAL): All four bytes are valid

• 1: Indicates that the current access to the FIFO is read, write, and debug access. In this mode, the following access types are allowed:
  • Read and Write access to Tx FIFO, TSO FIFO, DCACHE FIFO and Rx FIFO
  • Read access is allowed to Tx Status FIFO.
• 0: Indicates that the current access to the FIFO is slave access bypassing the DMA. In this mode, the following accesses are allowed:
  • Write access to the Tx FIFO
  • Read access to the Rx FIFO and Tx Status FIFO

Values:

• 0x0(DISABLE): Debug Mode Access to FIFO is disabled
• 0x1(ENABLE): Debug Mode Access to FIFO is enabled

FIFO Debug Access Enabled

• 1: Indicates that the debug mode access to the FIFO is enabled.
• 0: Indicates that the FIFO can be accessed only through a master interface.

Values:

• 0x0(DISABLE): FIFO Debug Access is disabled
• 0x1(ENABLE): FIFO Debug Access is enabled

• Slave Access Mode: This field indicates the space avail- able in the selected FIFO.
• Debug Access Mode: This field contains the Write or Read pointer value of the selected FIFO during Write or Read operation, respectively.
• Reset: In single Tx Queue configurations, (DWC_EQOS_TXFIFO_SIZE/(DWC_EQOS_DATAW- IDTH/8)), Otherwise 0000H

When set, this bit indicates that the Slave mode Tx packet is transmitted, and the status is available in Tx Status FIFO. This bit is reset when 1 is written to this bit.

Values:

• 0x0(INACTIVE): Transmit Status Available Interrupt Status not detected
• 0x1(ACTIVE): Transmit Status Available Interrupt Status detected

When set, this bit indicates that MAC layer has written the EOP of the received packet to the Rx FIFO. This bit is reset when 1 is written to this bit.

Values:

• 0x0(INACTIVE): Receive Packet Available Interrupt Status not detected
• 0x1(ACTIVE): Receive Packet Available Interrupt Status detected

This field indicates the number of data bytes valid in the data register during Read operation. This is valid only when PKTSTATE is 2'b10 (EOP) and Tx FIFO or Rx FIFO is selected.

Values:

• 0x0(B0_VAL): Byte 0 valid
• 0x1(B01_VAL): Byte 0 and Byte 1 are valid
• 0x2(B012_VAL): Byte 0, Byte 1, and Byte 2 are valid
• 0x3(B0123_VAL): All four bytes are valid

This field is used to get the control or status information of the selected FIFO.

• Tx FIFO:
  • 00: Packet Data
  • 01:Control Word
  • 10:SOP Data
  • 11:EOP Data
• Rx FIFO:
  • 00: Packet Data
  • 01:Normal Status
  • 10: Last Status
  • 11: EOP

This field is applicable only for Tx FIFO and Rx FIFO during Read operation.

Values:

• 0x0(PKT_DATA): Packet Data
• 0x1(CW_NS): Control Word/Normal Status
• 0x2(SOP_LS): SOP Data/Last Status
• 0x3(EOP): EOP Data/EOP

When set, this bit indicates that a FIFO operation is in progress in the MAC and content of the following fields is not valid:

• All other fields of this register
• All fields of the MTL_FIFO_Debug_Data register

Values:

• 0x0(INACTIVE): FIFO Busy not detected
• 0x1(ACTIVE): FIFO Busy detected

During debug or slave access write operation, this field contains the data to be written to the Tx FIFO, Rx FIFO, or TSO FIFO. During debug or slave access read operation, this field contains the data read from the Tx FIFO, Rx FIFO, TSO FIFO, or Tx Status FIFO.

This bit indicates that there is an interrupt from Rx Parser Block. To reset this bit, the application must read the MTL_ Rxp_Interrupt_Status register to get the exact cause of the interrupt and clear its source.

Values:

• 0x0(INACTIVE): MTL Rx Parser Interrupt status not detected
• 0x1(ACTIVE): MTL Rx Parser Interrupt status detected

This bit indicates an interrupt event during the operation of 802.1Qbv. To reset this bit, the application must clear the error/event that has caused the Interrupt.

Values:

• 0x0(INACTIVE): EST (TAS- 802.1Qbv) Interrupt status not detected
• 0x1(ACTIVE): EST (TAS- 802.1Qbv) Interrupt status detected

This bit indicates an interrupt event during the slave access. To reset this bit, the application must read the FIFO Debug Access Status register to get the exact cause of the interrupt and clear its source.

Values:

• 0x0(INACTIVE): Debug Interrupt status not detected
• 0x1(ACTIVE): Debug Interrupt status detected

This bit indicates an interrupt event in the MAC. To reset this bit, the application must read the corresponding register in the MAC to get the exact cause of the interrupt and clear its source.

Values:

• 0x0(INACTIVE): MAC Interrupt status not detected
• 0x1(ACTIVE): MAC Interrupt status detected

This bit indicates that there is an interrupt from Queue 7. To reset this bit, the application must read the MTL_Q7_Interrupt_Control_Status Status register to get the exact cause of the interrupt and clear its source.

Values:

• 0x0(INACTIVE): Queue 7 Interrupt status not detected
• 0x1(ACTIVE): Queue 7 Interrupt status detected

This bit indicates that there is an interrupt from Queue 6. To reset this bit, the application must read the MTL_Q6_Interrupt_Control_Status register to get the exact cause of the interrupt and clear its source.

Values:

• 0x0(INACTIVE): Queue 6 Interrupt status not detected
• 0x1(ACTIVE): Queue 6 Interrupt status detected

This bit indicates that there is an interrupt from Queue 5. To reset this bit, the application must read the MTL_Q5_Interrupt_Control_Status register to get the exact cause of the interrupt and clear its source.

Values:

• 0x0(INACTIVE): Queue 5 Interrupt status not detected
• 0x1(ACTIVE): Queue 5 Interrupt status detected

This bit indicates that there is an interrupt from Queue 4. To reset this bit, the application must read the MTL_Q4_Interrupt_Control_Status register to get the exact cause of the interrupt and clear its source.

Values:

• 0x0(INACTIVE): Queue 4 Interrupt status not detected
• 0x1(ACTIVE): Queue 4 Interrupt status detected

This bit indicates that there is an interrupt from Queue 3. To reset this bit, the application must read the MTL_Q3_Interrupt_Control_Status register to get the exact cause of the interrupt and clear its source.

Values:

• 0x0(INACTIVE): Queue 3 Interrupt status not detected
• 0x1(ACTIVE): Queue 3 Interrupt status detected

This bit indicates that there is an interrupt from Queue 2. To reset this bit, the application must read the MTL_Q2_Interrupt_Control_Status register to get the exact cause of the interrupt and clear its source.

Values:

• 0x0(INACTIVE): Queue 2 Interrupt status not detected
• 0x1(ACTIVE): Queue 2 Interrupt status detected

This bit indicates that there is an interrupt from Queue 1. To reset this bit, the application must read the MTL_Q1_Interrupt_Control_Status register to get the exact cause of the interrupt and clear its source.

Values:

• 0x0(INACTIVE): Queue 1 Interrupt status not detected
• 0x1(ACTIVE): Queue 1 Interrupt status detected

This bit indicates that there is an interrupt from Queue 0. To reset this bit, the application must read Queue 0 Interrupt Control and Status register to get the exact cause of the interrupt and clear its source.

Values:

• 0x0(INACTIVE): Queue 0 Interrupt status not detected
• 0x1(ACTIVE): Queue 0 Interrupt status detected

When set, this bit indicates that the packets received in Queue 3 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the Ethernet DA address.

When reset, this bit indicates that the packets received in Queue 3 are routed to the DMA Channel programmed in the Q3MDMACH field (Bits[26:24]).

Values:

• 0x0(DISABLE): Queue 3 disabled for DA-based DMA Channel Selection
• 0x1(ENABLE): Queue 3 enabled for DA-based DMA Channel Selection

This field controls the routing of the received packet in Queue 3 to the DMA channel:

• 000:DMA Channel 0
• 001:DMA Channel 1
• 010:DMA Channel 2
• 011:DMA Channel 3
• 100:DMA Channel 4
• 101:DMA Channel 5
• 110:DMA Channel 6
• 111:DMA Channel 7

This field is valid when the Q3DDMACH field is reset.

When set, this bit indicates that the packets received in Queue 2 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the Ethernet DA address.

When reset, this bit indicates that the packets received in Queue 2 are routed to the DMA Channel programmed in the Q2MDMACH field (Bits[18:16]).

Values:

• 0x0(DISABLE): Queue 2 disabled for DA-based DMA Channel Selection
• 0x1(ENABLE): Queue 2 enabled for DA-based DMA Channel Selection

This field controls the routing of the received packet in Queue 2 to the DMA channel:

• 000:DMA Channel 0
• 001:DMA Channel 1
• 010:DMA Channel 2
• 011:DMA Channel 3
• 100:DMA Channel 4
• 101:DMA Channel 5
• 110:DMA Channel 6
• 111:DMA Channel 7

This field is valid when the Q2DDMACH field is reset.

When set, this bit indicates that the packets received in Queue 1 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the Ethernet DA address.

When reset, this bit indicates that the packets received in Queue 1 are routed to the DMA Channel programmed in the Q1MDMACH field (Bits[10:8]).

Values:

• 0x0(DISABLE): Queue 1 disabled for DA-based DMA Channel Selection
• 0x1(ENABLE): Queue 1 enabled for DA-based DMA Channel Selection

This field controls the routing of the received packet in Queue 1 to the DMA channel:

• 000:DMA Channel 0
• 001:DMA Channel 1
• 010:DMA Channel 2
• 011:DMA Channel 3
• 100:DMA Channel 4
• 101:DMA Channel 5
• 110:DMA Channel 6
• 111:DMA Channel 7

This field is valid when the Q1DDMACH field is reset. The width of this field depends on the number of RX DMA channels and not all the values might be valid in some configurations. For example, if the number of RX DMA channels selected is2, only 000 and 001 are valid, the other bits are reserved.

When set, this bit indicates that the packets received in Queue 0 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the Ethernet DA address.

When reset, this bit indicates that the packets received in Queue 0 are routed to the DMA Channel programmed in the Q0MDMACH field.

Values:

• 0x0(DISABLE): Queue 0 disabled for DA-based DMA Channel Selection
• 0x1(ENABLE): Queue 0 enabled for DA-based DMA Channel Selection

This field controls the routing of the packet received in Queue 0 to the DMA channel:

• 000: DMA Channel 0
• 001: DMA Channel 1
• 010: DMA Channel 2
• 011: DMA Channel 3
• 100: DMA Channel 4
• 101: DMA Channel 5
• 110: DMA Channel 6
• 111: DMA Channel 7

This field is valid when the Q0DDMACH field is reset. The width of this field depends on the number of RX DMA channels and not all the values might be valid in some configurations. For example, if the number of RX DMA channels selected is 2, only 000 and 001 are valid, the other bits are reserved.

When set, this bit indicates that the packets received in Queue 7 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the Ethernet DA address.

When reset, this bit indicates that the packets received in Queue 7 are routed to the DMA Channel programmed in the Q7MDMACH field.

Values:

• 0x0(DISABLE): Queue 5 disabled for DA-based DMA Channel Selection
• 0x1(ENABLE): Queue 5 enabled for DA-based DMA Channel Selection

This field controls the routing of the packet received in Queue 7 to the DMA channel:

• 000:DMA Channel 0
• 001:DMA Channel 1
• 010:DMA Channel 2
• 011:DMA Channel 3
• 100:DMA Channel 4
• 101:DMA Channel 5
• 110:DMA Channel 6
• 111:DMA Channel 7

This field is valid when the Q7DDMACH field is reset. The width of this field depends on the number of RX DMA channels and not all the values might be valid in some configurations. For example, if the number of RX DMA channels selected is 2, only 000 and 001 are valid, the other bits are reserved.

When set, this bit indicates that the packets received in Queue 6 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the Ethernet DA address.

When reset, this bit indicates that the packets received in Queue 6 are routed to the DMA Channel programmed in the Q6MDMACH field.

Values:

• 0x0(DISABLE): Queue 6 disabled for DA-based DMA Channel Selection
• 0x1(ENABLE): Queue 6 enabled for DA-based DMA Channel Selection

This field controls the routing of the packet received in Queue 6 to the DMA channel:

• 000:DMA Channel 0
• 001:DMA Channel 1
• 010:DMA Channel 2
• 011:DMA Channel 3
• 100:DMA Channel 4
• 101:DMA Channel 5
• 110:DMA Channel 6
• 111:DMA Channel 7

This field is valid when the Q6DDMACH field is reset. The width of this field depends on the number of RX DMA channels and not all the values might be valid in some configurations. For example, if the number of RX DMA

channels selected is2, only 000 and 001 are valid, the other bits are reserved.

When set, this bit indicates that the packets received in Queue 5 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the Ethernet DA address.

When reset, this bit indicates that the packets received in Queue 5 are routed to the DMA Channel programmed in the Q5MDMACH field.

Values:

• 0x0(DISABLE): Queue 5 disabled for DA-based DMA Channel Selection
• 0x1(ENABLE): Queue 5 enabled for DA-based DMA Channel Selection

This field controls the routing of the packets received in Queue 5 to the DMA channel:

• 000: DMA Channel 0
• 001: DMA Channel 1
• 010: DMA Channel 2
• 011: DMA Channel 3
• 100: DMA Channel 4
• 101: DMA Channel 5
• 110: DMA Channel 6
• 111: DMA Channel 7

This field is valid when the Q5DDMACH field is reset. The width of this field depends on the number of RX DMA channels and not all the values might be valid in some configurations. For example, if the number of RX DMA channels selected is2, only 000 and 001 are valid, the other bits are reserved.

When set, this bit indicates that the packets received in Queue 4 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the Ethernet DA address.

When reset, this bit indicates that the packets received in Queue 4 are routed to the DMA Channel programmed in the Q4MDMACH field.

Values:

• 0x0(DISABLE): Queue 4 disabled for DA-based DMA Channel Selection
• 0x1(ENABLE): Queue 4 enabled for DA-based DMA Channel Selection

This field controls the routing of the packet received in Queue 4 to the DMA channel:

• 000: DMA Channel 0
• 001: DMA Channel 1
• 010: DMA Channel 2
• 011: DMA Channel 3
• 100: DMA Channel 4
• 101: DMA Channel 5
• 110: DMA Channel 6
• 111: DMA Channel 7

This field is valid when the Q4DDMACH field is reset. The width of this field depends on the number of RX DMA channels and not all the values might be valid in some configurations. For example, if the number of RX DMA channels selected is2, only 000 and 001 are valid, the other bits are reserved.

The value in units of 256 nanoseconds that has to be added to the Launch time to compute the Launch Expiry time. Value valid only when LEOV is set.

Max value: 999,999,999 ns, additionally should be smaller than CTR-1 value when ESTM mode is set since this value is a modulo CTR value.

The number of GSN slots that have to be added to the Launch GSN to compute the Launch Expiry time. Value valid only when LEOV is set.

When set indicates the LEOS field is valid. When not set, indicates the Launch Expiry Offset is not valid and the MTL must not check for Launch expiry time.

Values:

• 0x0(INVALID): LEOS field is invalid
• 0x1(VALID): LEOS field is valid

When this bit is set, the Launch Time value used in Time Based Scheduling is interpreted as an EST offset value and is added to the Base Time Register (BTR) of the current list.

When reset, the Launch Time value is used as an absolute value that should be compared with the System time [39:8].

Values:

• 0x0(DISABLE): EST offset Mode is disabled
• 0x1(ENABLE): EST offset Mode is enabled

The value of PTP Clock period is multiplied by 6 in nanoseconds. This value is needed to avoid transmission overruns at the beginning of the installation of a new GCL.

Provides a12 bit time offset value in nanoseconds that is added to the current time to compensate for all the implementation pipeline delays such as the CDC sync delay, buffering delays, data path delays and so on. This offset helps to ensure that the impact of gate controls is visible on the line exactly at the pre-determined schedule (or as close to the schedule as possible).

This field provides the left shift amount for the programmed Time Interval values used in the Gate Control Lists.

• 000: No left shift needed (equal to x1ns)
• 001: Left shift TI by 1 bit (equal to x2ns)
• 010: Left shift TI by 2 bits (equal to x4ns)
• ...
• 100: Left shift TI by 7 bits (equal to x128ns)

Based on the configuration one or more bits of this field should be treated as Reserved/Read-Only.

Programmable number of GCL list iterations before reporting an HLBS error defined in EST_Status register.

Values:

• 0x0(M_4_ITERNS): 4 iterations
• 0x1(M_8_ITERNS): 8 iterations
• 0x2(M_16_ITERNS): 16 iterations
• 0x3(M_32_ITERNS): 32 iterations

When set frames reported to cause HOL Blocking due to not getting scheduled (HLBS field of EST_Status register) after 4,8,16,32 (based on LCSE field of this register) GCL iterations are dropped.

Values:

• 0x0(DONT_DROP): Do not Drop Frames causing Scheduling Error
• 0x1(DROP): Drop Frames causing Scheduling Error

When set, frames are not be dropped during Head-of-Line blocking due to Frame Size Error (HLBF field of EST_Status register).

Values:

• 0x0(DROP): Drop frames during Frame Size Error
• 0x1(DONT_DROP): Do not Drop frames during Frame Size Error

When set indicates that the software has programmed that list that it currently owns (SWOL) and the hardware should switch to the new list based on the new BTR. Hardware clears this bit when the switch to the SWOL happens to indicate the completion of the switch or when a BTR error (BTRE in Status register) is set. When BTRE is set this bit is cleared but SWOL is not updated as the switch was not successful.

Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect.

Values:

• 0x0(DISABLE): Switch to S/W owned list is disabled
• 0x1(ENABLE): Switch to S/W owned list is enabled

When reset, the gate control list processing is halted and all gates are assumed to be in an open state. Should be set for the hardware to start processing the gate control lists. During the toggle from 0 to 1, the gate control list processing starts only after the SSWL bit it set.

When DWC_EQOS_ASP_ECC is selected during the configuration, if any uncorrectable error is detected in the EST memory the hardware resets this bit and disables the EST function.

Values:

• 0x0(DISABLE): EST is disabled
• 0x1(ENABLE): EST is enabled

This field indicates the fixed overhead for every packet to account for EST Scheduler Delay, IPG or EIPG, and Preamble bytes.

Indicates the slot number of the GCL list. Slot number is a modulo 16 count of the GCL List loops executed so far.

Even if a new GCL list is installed, the count is incremental.

Provides the minimum count (N)for which the equation Current Time =< New BTR + (N * New Cycle Time) becomes true. N = "11111111" indicates the iterations exceeded the value of 128 and the hardware was not able to update New BTR to be equal to or greater than Current Time. Software intervention is needed to update the New BTR. Value cleared when BTRE field of this register is cleared.

When '0' indicates Gate control list number "0" is owned by software and when "1" indicates the Gate Control list "1" is owned by the software. Any reads/writes by the software (using indirect access through GCL_Control) is directed to the list indicated by this value by default. The inverse of this value is treated as HWOL.

R/W operations performed by hardware are directed to the list pointed by HWOL by default.

Values:

• 0x0(INACTIVE): Gate control list number "0" is owned by software
• 0x1(ACTIVE): Gate control list number "1" is owned by software

This error occurs when the list length (LLR) is 1 and the Cycle Time (CTR) is less than or equal to the programmed Time Interval (TI) value after the optional Left Shifting. This implies, Gates are either always Closed or always Open based on the Gate Control values; the same effect can be achieved by other simpler (non TSN) programming mechanisms. Since the implementation does not support such programming an error is reported.

Access restriction applies. Self-set to 1 on an internal event. Setting 1 clears. Setting 0 has no effect.

Values:

• 0x0(INACTIVE): Constant Gate Control Error not detected
• 0x1(ACTIVE): Constant Gate Control Error detected

Set when the frame is not able to win arbitration and get scheduled even after 4 iterations of the GCL. Indicates to software a potential programming error. The one hot encoded values of the Queue Numbers that are not able to make progress are indicated in the MTL_EST_Sch_Error register. Bit cleared when MTL_EST_Sch_Error register is all zeros.

Values:

• 0x0(INACTIVE): Head-Of-Line Blocking due to Scheduling not detected
• 0x1(ACTIVE): Head-Of-Line Blocking due to Scheduling detected

Set when HOL Blocking is noticed on one or more Queues as a result of none of the Time Intervals of gate open in the GCL being greater than or equal to the duration needed for frame size (or frame fragment size when preemption is enabled) transmission. The one hot encoded Queue numbers that are experiencing HLBF are indicated in the MTL_EST_Frm_Size_Error register. Additionally, the first Queue number that experienced HLBF along with the frame size is captured in MTL_EST_Frm_Size_Capture register. Bit cleared when MTL_EST_Frame_Size_ Error register is all zeros.

Values:

• 0x0(INACTIVE): Head-Of-Line Blocking due to Frame Size not detected
• 0x1(ACTIVE): Head-Of-Line Blocking due to Frame Size detected

When "1" indicates a programming error in the BTR of SWOL where the programmed value is less than current time. If the BTRL = "11111111", SWOL is not updated and software should reprogram the BTR to a value greater than current time and then set SSWL to re-initiate the switch to SWOL. Else if the value of BTRL < "11111111", SWOL is updated and this field indicates the number of iterations (of + Cycle Time) taken by hardware to update the BTR to a value greater than Current Time.

Access restriction applies. Self-set to 1 on an internal event. Setting 1 clears. Setting 0 has no effect.

Values:

• 0x0(INACTIVE): BTR Error not detected
• 0x1(ACTIVE): BTR Error detected

When "1" indicates the hardware has successfully switched to the SWOL, and the SWOL bit has been updated to that effect. Cleared when the SSWL of EST_Control register transitions from 0 to 1, or on a software write.

Access restriction applies. Self-set to 1 on an internal event. Setting 1 clears. Setting 0 has no effect.

Values:

• 0x0(INACTIVE): Switch to S/W owned list Complete not detected
• 0x1(ACTIVE): Switch to S/W owned list Complete detected

The One Hot Encoded Queue Numbers that have experienced error/timeout described in HLBS field of the status register.

Access restriction applies. Self-set to 1 on an internal event. Setting 1 clears. Setting 0 has no effect.

The One Hot Encoded Queue Numbers that have experienced error described in HLBF field of the status register.

Access restriction applies. Self-set to 1 on an internal event. Setting 1 clears. Setting 0 has no effect.

Captures the binary value of the of the first Queue (number) experiencing HLBF error (see HLBF field of status register). Value once written is not altered by any subsequent queue errors of similar nature. Once cleared the queue number of the next occurring HLBF error is captured.

Width is based on the number of Tx Queues configured; remaining bits are Read-Only. Cleared when MTL_EST_Frm_Size_Error register is all zeros.

Captures the Frame Size of the dropped frame related to queue number indicated in HBFQ field of this register.

Contents of this register should be considered invalid, if this field is zero.

Cleared when MTL_EST_Frm_Size_Error register is all zeros.

Reserved.

Interrupt Enabled for CGCE

When set, generates an interrupt when the Constant Gate Control Error occurs and is indicated in the status. When reset this event does not generate an interrupt

Values:

• 0x0(DISABLE): Interrupt for CGCE is disabled
• 0x1(ENABLE): Interrupt for CGCE is enabled

When set, generates an interrupt when the Head-of-Line Blocking due to a scheduling issue and is indicated in the status. When reset this event does not generate an interrupt.

Values:

• 0x0(DISABLE): Interrupt for HLBS is disabled
• 0x1(ENABLE): Interrupt for HLBS is enabled

When set, generates an interrupt when the Head-of-Line Blocking due to Frame Size error occurs and is indicated in the status. When reset this event does not generate an interrupt.

Values:

• 0x0(DISABLE): Interrupt for HLBF is disabled
• 0x1(ENABLE): Interrupt for HLBF is enabled

When set, generates an interrupt when the BTR Error occurs and is indicated in the status. When reset this event does not generate an interrupt.

Values:

• 0x0(DISABLE): Interrupt for BTR Error is disabled
• 0x1(ENABLE): Interrupt for BTR Error is enabled

When set, generates interrupt when the configuration change is successful and the hardware has switched to the new list. When reset this event does not generate an interrupt.

Values:

• 0x0(DISABLE): Interrupt for Switch List is disabled
• 0x1(ENABLE): Interrupt for Switch List is enabled

When ESTEIEE or ESTEIAEE bit of this register is set, the following are the errors inserted based on the value encoded in this field.

This field is valid only if DWC_EQOS_ASP_ECC feature is selected during the configuration, else it is reserved.

Values:

• 0x0(M_1BIT): Insert 1 bit error
• 0x1(M_2BIT): Insert 2 bit errors

When set along with EEST bit of MTL_EST_Control register, enables the ECC address error injection feature.

When reset, disables the ECC address error injection feature.

Values:

• 0x0(DISABLE): EST ECC Inject Address Error is disabled
• 0x1(ENABLE): EST ECC Inject Address Error is enabled

When set along with EEST bit of MTL_EST_Control register, enables the ECC error injection feature.

When reset, disables the ECC error injection feature.

Values:

• 0x0(DISABLE): EST ECC Inject Error is disabled
• 0x1(ENABLE): EST ECC Inject Error is enabled

Gate Control List Address:(GCLA when GCRR is "0"). Provides the address (row number) of the Gate Control List at which the R/W operation has to be performed. By default the Gate Control List pointed by SWOL of MTL_EST_Status is selected for R/W. However, if the DBGM bit of this register is set, a debug mode access is given to R/W from DBGB. The width of this field is dependent on DWC_EQOS_EST_DEP; unused bits should be treated as read-only.

Gate Control List Related Registers Address: (GCRA when GCRR is "1").

By default the GCL related register set pointed by SWOL of MTL_EST_Status is selected for R/W, however if the DBGM bit of this register is set, a debug mode access is given to R/W from DBGB. Lower 3 bits are only used in this mode, higher order bits are treated as don't care.

• 000: BTR Low (31:0)
• 001: BTR High (63:31)
• 010: CTR Low (31:0)
• 011: CTR High (39:32)
• 100: TER(31:0)
• 101: LLR(n:0) (where n is (log{DWC_EQOS_EST_DEP} / log2))
• Others: Reserved

When set to "0" indicates R/W in debug mode should be directed to Bank 0 (GCL0 and corresponding time related registers). When set to "1" indicates R/W in debug mode should be directed to Bank 1 (GCL1 and corresponding time related registers). This value is used when DBGM is set and overrides by value of SWOL which is normally used.

Values:

• 0x0(BANK0): R/W in debug mode should be directed to Bank 0
• 0x1(BANK1): R/W in debug mode should be directed to Bank 1

When set to "1" indicates R/W in debug mode where the memory bank (for GCL and Time related registers) is explicitly provided by DBGB value, when set to "0" SWOL bit is used to determine which bank to use.

Values:

• 0x0(DISABLE): Debug Mode is disabled
• 0x1(ENABLE): Debug Mode is enabled

When set to "1" indicates the R/W access is for the GCL related registers (BTR, CTR, TER, LLR) whose address is provided by GCRA. When "0" indicates R/W should be directed to GCL from the address provided by GCLA.

Values:

• 0x0(DISABLE): Gate Control Related Registers are disabled
• 0x1(ENABLE): Gate Control Related Registers are enabled

• 1: Read operation
• 0: Write operation.

Values:

• 0x0(WRITE): Write Operation
• 0x1(READ): Read Operation

• 1: Indicates the start/progress of a Read/Write operation.
• Reset by hardware: Indicates the R/W operation has completed or an error has occurred (when bit 20 is set)
• Reads: Data can be read from MTL_EST_GCL_Data register after this bit is reset
• Writes: MTL_EST_GCL_Data should be programmed with write data before setting SRWO.

Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect.

Values:

• 0x0(DISABLE): Start Read/Write Op disabled
• 0x1(ENABLE): Start Read/Write Op enabled

The data corresponding to the address selected in the GCL_Control register. Used for both Read and Write operations.

Hold/Release Status

• 1: Indicates a Set-and-Hold-MAC operation was last executed and the pMAC is in Hold State.
• 0: Indicates a Set-and-Release-MAC operation was last executed and the pMAC is in Release State.

Values:

• 0x0(SET_REL): Indicates a Set-and-Release-MAC operation was last executed and the pMAC is in Release State
• 0x1(SET_HOLD): Indicates a Set-and-Hold-MAC operation was last executed and the pMAC is in Hold State

When set indicates the corresponding Queue must be classified as preemptible, when '0' Queue is classified as express. When both EST (Qbv) and Preemption are enabled, Queue-0 is always assumed to be preemptible. When EST (Qbv) is enabled Queues categorized as preemptible here are always assumed to be in "Open" state in the Gate Control List.

used to indicate, in units of 64 bytes, the minimum number of bytes over 64 bytes required in non-final fragments of preempted frames. The minimum non-final fragment size is (AFSZ +1) * 64 bytes

The maximum time in nanoseconds that can elapse between issuing a RELEASE to the MAC and the MAC being ready to resume transmission of preemptible frames, in the absence of there being any express frames available for transmission.

The maximum time in nanoseconds that can elapse between issuing a HOLD to the MAC and the MAC ceasing to transmit any preemptible frame that is in the process of transmission or any preemptible frames that are queued for transmission.

This status bit is set to 1 when the Rx parser is in Idle State and waiting for a new packet for processing. This bit is used as a handshake with software when parser gets disables. After disabling, when bit is set then software can update the Rx parser instruction table.

Values:

• 0x0(INACTIVE): RX Parser not in Idle state
• 0x1(ACTIVE): RX Parser in Idle state

When this bit is set,RDES2[31:16] indicates the index of the last instruction executed in Rx Parse, when set to 0 indicates MAC filter status.

This control indicates the number of parsable entries in the Instruction Memory. This is used in Rx parser logic to detect programming Error.

In case the number of parsed entries for a packet is more than this entry then NPEOVIS bit in the MTL_RXP_Interrupt_Control_Status register is set.

This control indicates the number of valid entries address/index in the Instruction Memory (i.e. when NVE field in register=31, the maximum valid entry address is NVE+1 i.e. addresses/indices=0 to 32, or 33 entries). This is used in Rx parser logic to detect any programming Error. In case while parsing Table address (memory address) found to be more than this maximum valid entry address then NVEOVIS bit in the MTL_RXP_Interrupt_Control_Status register is set.

When this bit is set, the PDRFIS interrupt is enabled. When this bit is reset, the PDRFIS interrupt is disabled.

Values:

• 0x0(DISABLE): Packet Drop due to RF Interrupt is disabled
• 0x1(ENABLE): Packet Drop due to RF Interrupt is enabled

When this bit is set, the FOOVIS interrupt is enabled. When this bit is reset, the FOOVIS interrupt is disabled.

Values:

• 0x0(DISABLE): Frame Offset Overflow Interrupt is disabled
• 0x1(ENABLE): Frame Offset Overflow Interrupt is enabled

When this bit is set, the NPEOVIS interrupt is enabled. When this bit is reset, the NPEOVIS interrupt is disabled.

Values:

• 0x0(DISABLE): The number of Parsable Entries Overflow Interrupt is disabled
• 0x1(ENABLE): The number of Parsable Entries Overflow Interrupt is enabled

When this bit is set, the NVEOVIS interrupt is enabled. When this bit is reset, the NVEOVIS interrupt is disabled.

Values:

• 0x0(DISABLE): Number of Valid Entries Overflow Interrupt is disabled
• 0x1(ENABLE): Number of Valid Entries Overflow Interrupt is enabled

If the Rx Parser result says to drop the packet by setting RF=1 in the instruction memory, then this bit is set to 1.

This bit is cleared when the application writes 1 to this bit. Access restriction applies. Self-set to 1 on an internal event. Setting 1 clears. Setting 0 has no effect.

Values:

• 0x0(INACTIVE): Packet Dropped due to RF Interrupt Status not detected
• 0x1(ACTIVE): Packet Dropped due to RF Interrupt Status detected

While parsing if the Instruction table entry's 'Frame Offset' found to be more than EOF offset, then this bit is set. This bit is cleared when the application writes 1 to this bit. Access restriction applies. Self-set to 1 on an internal event. Setting 1 clears. Setting 0 has no effect.

Values:

• 0x0(INACTIVE): Frame Offset Overflow Interrupt Status not detected
• 0x1(ACTIVE): Frame Offset Overflow Interrupt Status detected

While parsing a packet if the number of parsed entries found to be more than NPE[] (Number of Parsable Entries in MTL_RXP_Control register), then this bit is set to 1.

This bit is cleared when the application writes 1 to this bit. Access restriction applies. Self-set to 1 on an internal event. Setting 1 clears. Setting 0 has no effect.

Values:

• 0x0(INACTIVE): Number of Parsable Entries Overflow Interrupt Status not detected
• 0x1(ACTIVE): Number of Parsable Entries Overflow Interrupt Status detected

While parsing if the Instruction address found to be more than NVE (Number of Valid Entry Address/index in MTL_RXP_Control register), then this bit is set to 1.

For example, when NVE field in register=31, the maximum valid entry address/index is NVE+1 i.e. 32 (addresses/indices=0 to 32, or 33 entries), so NVEOVIS is set when currently processed entry indicates the next address is 33 or more i.e. 34th or later entries.

This bit is cleared when the application writes 1 to this bit. Access restriction applies. Self-set to 1 on an internal event. Setting 1 clears. Setting 0 has no effect.

Values:

• 0x0(INACTIVE): The number of Valid Entries Overflow Interrupt Status not detected
• 0x1(ACTIVE): The number of Valid Entries Overflow Interrupt Status detected

When set, this bit indicates that the MTL_RXP_Drop_cnt (RXPDC) Counter field crossed the maximum limit. Access restriction applies. Clears on read. Self-set to 1 on an internal event.

Values:

• 0x0(INACTIVE): Rx Parser Drop count overflow has not occurred
• 0x1(ACTIVE): Rx Parser Drop count overflow occurred

This 31-bit counter is implemented when an Rx Parser Drops a packet due to RF =1. The counter is cleared when the register is read.

When set, this bit indicates that the MTL_RXP_Error_cnt (RXPEC) Counter field crossed the maximum limit.

Access restriction applies. Clears on read. Self-set to 1 on an internal event.

Values:

• 0x0(INACTIVE): Rx Parser Error count overflow not occurred
• 0x1(ACTIVE): Rx Parser Error count overflow occurred

This 31-bit counter is implemented when an Rx Parser encounters following Error scenarios

• Entry address >= NVE[]
• Number Parsed Entries >= NPE[]
• Entry address >EOF data entry address The counter is cleared when the register is read.

FRP Instruction Table Access Busy

• Set to 1by the software, indicates to start the Read/Write operation from/to the Rx Parser Memory. Software should read this bit as 0 before issuing read or write request to access the Parser Memory Instructions.
• Set to 1by the IP, indicates that the IP is busy until it is cleared by the IP. Software should not issue read or write operation.

Values:

• 0x0(INACTIVE): Hardware not busy
• 0x1(ACTIVE): Hardware is busy (Read/Write operation from/to the Rx Parser Memory)

When RXPEIEE or RXPEIAEE bit of this register is set, the following are the errors inserted based on the value encoded in this field:

• 1: Insert 1bit error.
• 0: Insert 2bit errors.

Values:

• 0x0(M_1BIT): Insert 1 bit error
• 0x1(M_2BIT): Insert 2 bit errors

• 1: Enables the ECC address error injection feature.
• 0: Disables the ECC address error injection feature.

Values:

• 0x0(DISABLE): ECC Inject Address Error for Rx Parser Memory is disabled
• 0x1(ENABLE): ECC Inject Address Error for Rx Parser Memory is enabled

• 1: Enables the ECC error injection feature.
• 0: Disables the ECC error injection feature.

Values:

• 0x0(DISABLE): ECC Inject Error for Rx Parser Memory is disabled
• 0x1(ENABLE): ECC Inject Error for Rx Parser Memory is enabled

• 1: Indicates the write operation to the Rx Parser Memory.
• 0: Indicates the read operation to the Rx Parser Memory.

Values:

• 0x0(READ): Read operation to the Rx Parser Memory
• 0x1(WRITE): Write operation to the Rx Parser Memory

This field indicates the ADDR of the 32-bit entry in Rx parser instruction table. Each entry has 128-bit (4x32-bit words).

The Xis based on the configurable DWC_EQOS_FRP_ENTRIES. If DWC_EQOS_FRP_ENTRIES is

• 256: X= 9
• 128: X= 8
• 64: X= 7

Software should write this register before issuing any write command.

The hardware provides the read data from the Rx Parser Memory for read operation when STARTBUSY =0 after read command.

When set, this bit indicates that the MTL_RXP_Bypass_cnt (RXPBC) Counter field crossed the maximum limit. Access restriction applies. Clears on read. Self-set to 1 on an internal event.

Values:

• 0x0(INACTIVE): Rx Parser Bypass count overflow not occurred
• 0x1(ACTIVE): Rx Parser Bypass count overflow occurred

Rx Parser Bypass Count

This 31-bit counter is implemented when an Rx Parser bypass a packet due to AF=1 and RF =1. The counter is cleared when the register is read.

• 1: The EUEAS/ECEAS field of MTL_ECC_Err_Ad- dr_Status register holds the last valid address where the error is detected.
• 0: The EUEAS/ECEAS field of MTL_ECC_Err_Ad- dr_Status register holds the first address where the error is detected.

Values:

• 0x0(DISABLE): MTL ECC Error Address Status Over-ride is disabled
• 0x1(ENABLE): MTL ECC Error Address Status Over-ride is enabled

• 1: Enables the ECC feature for DCACHE memory in DMA
• 0: Disables the ECC feature for DCACHE memory in DMA

Values:

• 0x0(DISABLE): DCACHE memory ECC is disabled
• 0x1(ENABLE): DCACHE memory ECC is enabled

• 1: Enables the ECC feature for TSO memory in DMA
• 0: Disables the ECC feature for TSO memory in DMA

Values:

• 0x0(DISABLE): TSO memory ECC is disabled
• 0x1(ENABLE): TSO memory ECC is enabled

• 1: Enables the ECC feature for Rx Parser memory
• 0: Disables the ECC feature for Rx Parser memory

Values:

• 0x0(DISABLE): MTL Rx Parser ECC is disabled
• 0x1(ENABLE): MTL Rx Parser ECC is enabled

• 1: Enables the ECC feature for EST memory
• 0: Disables the ECC feature for EST memory

Values:

• 0x0(DISABLE): MTL EST ECC is disabled
• 0x1(ENABLE): MTL EST ECC is enabled

• 1: Enables the ECC feature for MTL Rx FIFO memory.
• 0: Disables the ECC feature for MTL Rx FIFO memory.

Values:

• 0x0(DISABLE): MTL Rx FIFO ECC is disabled
• 0x1(ENABLE): MTL Rx FIFO ECC is enabled

• 1: Enables the ECC feature for MTL Tx FIFO memory
• 0: Disables the ECC feature for MTL Tx FIFO memory

Values:

• 0x0(DISABLE): MTL Tx FIFO ECC is disabled
• 0x1(ENABLE): MTL Tx FIFO ECC is enabled

Indicates an uncorrectable Safety-related Interrupt is set in the MAC module. MAC_DPP_FSM_Interrupt_Status register should be read when this bit is set, to get the cause of the Safety Interrupt in MAC.

This bit indicates an uncorrectable error interrupt event in the MTL ECC safety feature. To get the exact cause of the interrupt the application should read the MTL_ECC_Interrupt_Status register.

Values:

• 0x0(INACTIVE): MTL ECC Uncorrectable error Interrupt Status not detected
• 0x1(ACTIVE): MTL ECC Uncorrectable error Interrupt Status detected

This bit indicates that a correctable error interrupt event in the MTL ECC safety feature. To get the exact cause of the interrupt the application should read the MTL_ECC_Interrupt_Status register.

Values:

• 0x0(INACTIVE): MTL ECC Correctable error Interrupt Status not detected
• 0x1(ACTIVE): MTL ECC Correctable error Interrupt Status detected

When set, generates an interrupt when an uncorrectable error is detected at the Rx Parser memory interface. It is indicated in RPCES status bit of MTL_ECC_Interrupt_Status register.

When reset this event does not generate an interrupt.

Values:

• 0x0(DISABLE): Rx Parser memory Correctable Error Interrupt is disabled
• 0x1(ENABLE): Rx Parser memory Correctable Error Interrupt is enabled

X

When set, generates an interrupt when a correctable error is detected at the MTL EST memory interface. It is indicated in the ECES bit of MTL_ECC_Interrupt_Status register. When reset this event does not generate an interrupt.

Values:

• 0x0(DISABLE): EST memory Correctable Error Interrupt is disabled
• 0x1(ENABLE): EST memory Correctable Error Interrupt is enabled

When set, generates an interrupt when a correctable error is detected at the MTL Rx memory interface. It is indicated in the RXCES bit of MTL_ECC_Interrupt_Status register.

When reset this event does not generate an interrupt.

Values:

• 0x0(DISABLE): Rx memory Correctable Error Interrupt is disabled
• 0x1(ENABLE): Rx memory Correctable Error Interrupt is enabled

When set, generates an interrupt when a correctable error is detected at the MTL Tx memory interface. It is indicated in the TXCES bit of MTL_ECC_Interrupt_Status register.

When reset this event does not generate an interrupt.

Values:

• 0x0(DISABLE): Tx memory Correctable Error Interrupt is disabled
• 0x1(ENABLE): Tx memory Correctable Error Interrupt is enabled

When set, indicates that an uncorrectable error is detected at Rx Parser memory interface.

Values:

• 0x0(INACTIVE): Rx Parser memory Uncorrectable Error Status not detected
• 0x1(ACTIVE): Rx Parser memory Uncorrectable Error Status detected

This bit when set indicates that address mismatch is found for the address bus of Rx Parser memory.

Values:

• 0x0(INACTIVE): MTL Rx Parser memory Address Mismatch Status not detected
• 0x1(ACTIVE): MTL Rx Parser memory Address Mismatch Status detected

This bit when set indicates that a correctable error is detected at RX Parser memory interface.

Values:

• 0x0(INACTIVE): MTL Rx Parser memory Correctable Error Status not detected
• 0x1(ACTIVE): MTL Rx Parser memory Correctable Error Status detected

When set, indicates that an uncorrectable error is detected at MTL EST memory interface.

Values:

• 0x0(INACTIVE): MTL EST memory Uncorrectable Error Status not detected
• 0x1(ACTIVE): MTL EST memory Uncorrectable Error Status detected

This bit when set indicates that address mismatch is found for address bus of MTL EST memory.

Values:

• 0x0(INACTIVE): MTL EST memory Address Mismatch Status not detected
• 0x1(ACTIVE): MTL EST memory Address Mismatch Status detected

This bit when set indicates that a correctable error is detected at the MTL EST memory.

Values:

• 0x0(INACTIVE): MTL EST memory Correctable Error Status not detected
• 0x1(ACTIVE): MTL EST memory Correctable Error Status detected

When set, indicates that an uncorrectable error is detected at the MTL Rx memory interface.

Values:

• 0x0(INACTIVE): MTL Rx memory Uncorrectable Error Status not detected
• 0x1(ACTIVE): MTL Rx memory Uncorrectable Error Status detected

This bit when set indicates that address mismatch is found for address bus of the MTL Rx memory.

Values:

• 0x0(INACTIVE): MTL Rx memory Address Mismatch Status not detected
• 0x1(ACTIVE): MTL Rx memory Address Mismatch Status detected

This bit when set indicates that correctable error is detected at the MTL Rx memory.

Values:

• 0x0(INACTIVE): MTL Rx memory correctable Error Status not detected
• 0x1(ACTIVE): MTL Rx memory correctable Error Status detected

When set, indicates that an uncorrectable error is detected at the MTL TX memory interface.

Values:

• 0x0(INACTIVE): MTL Tx memory Uncorrectable Error Status not detected
• 0x1(ACTIVE): MTL Tx memory Uncorrectable Error Status detected

This bit when set indicates that address mismatch is found for address bus of the MTL Tx memory.

Values:

• 0x0(INACTIVE): MTL Tx memory Address Mismatch Status not detected
• 0x1(ACTIVE): MTL Tx memory Address Mismatch Status detected

This bit when set indicates that a correctable error is detected at the MTL Tx memory.

Values:

• 0x0(INACTIVE): MTL Tx memory Correctable Error Status not detected
• 0x1(ACTIVE): MTL Tx memory Correctable Error Status detected

When this bit is set along with EESRE bit of this register, based on the EMS field of this register, the respective memory's uncorrectable error address and uncorrectable error count values are cleared upon reading.

Hardware resets this bit when all the error status values are cleared.

Values:

• 0x0(INACTIVE): Clear Uncorrectable Error Status not detected
• 0x1(ACTIVE): Clear Uncorrectable Error Status detected

When this bit is set along with EESRE bit of this register, based on the EMS field of this register, the respective memory's correctable error address and correctable error count values are cleared upon reading. Hardware resets this bit when all the error status values are cleared.

Values:

• 0x0(INACTIVE): Clear Correctable Error Status not detected
• 0x1(ACTIVE): Clear Correctable Error Status detected

When EESRE bit of this register is set, this field indicates which memory's error status value to be read. The memory selection encoding is as described.

Values:

• 0x0(TX_MEM): MTL Tx memory
• 0x1(RX_MEM): MTL Rx memory
• 0x2(EST_MEM): MTL EST memory
• 0x3(RXP_MEM): MTL Rx Parser memory
• 0x4(TSO_MEM): DMA TSO memory
• 0x5(DCACHE_MEM): DMA DCACHE memory

When this bit is set, based on the EMS field of this register, the respective memory's error status values are captured as described:

• The correctable and uncorrectable error count values are captured into MTL_ECC_Err_Cnt_Status register
• The address locations of correctable and uncorrectable errors are captured into MTL_ECC_Err_Addr_Status register.

Hardware resets this bit when all the status values are captured into the MTL_ECC_Err_Cnt_Status and MTL_ECC_Err_Addr_Status registers.

Values:

• 0x0(DISABLE): MTL ECC Error Status Read is disabled
• 0x1(ENABLE): MTL ECC Error Status Read is enabled

Based on the EMS field of MTL_ECC_Err_Sts_Rctl register, this field holds the respective memory's address locations for which an uncorrectable error or address mismatch is detected.

• MEEAO field of MTL_ECC_Control register is 1: This field holds the last valid address of memory for which either an uncorrectable error or an address mismatch is detected.
• MEEAO field of MTL_ECC_Control register is 0: This field holds the first address of the memory for which either an uncorrectable error or address mismatch is detected.

Based on the EMS field of MTL_ECC_Err_Sts_Rctl register, this field holds the respective memory's address locations for which a correctable error is detected.

• MEEAO field of MTL_ECC_Control register is 1: This field holds the last valid address of memory for which correct- able error or address mismatch is detected.
• MEEAO field of MTL_ECC_Control register is 0: This field holds the first address of the memory for which correctable error is detected.

Based on the EMS field of MTL_ECC_Err_Cntr_Rctl register, this field holds the respective memory's uncorrectable error count value.

Based on the EMS field of MTL_ECC_Err_Cntr_Rctl register, this field holds the respective memory's correctable error count value.

When set to 1, parity/data bit of first valid input parity/data of the DMA DCACHE parity checker (or at PC-dbg as shown in DCACHE parity protection diagram) is flipped.

Based on the EIM/BLEI field of MTL_DPP_ECC_EIC register, software can corrupt any one bit of parity/data.

Hardware clears this bit once the respective parity bit is flipped.

Values:

• 0x0(DISABLE): Insert Parity Error in DCACHE parity checker is disabled
• 0x1(ENABLE): Insert Parity Error in DCACHE Header parity checker is enabled

• 0x0(DISABLE): Insert Parity error in MTL RWC data parity checker is disabled
• 0x1(ENABLE): Insert Parity error in MTL RWC data parity checker is enabled

When set to 1, parity/data bit of first valid input parity/data of the MAC TFC data parity checker (or at PC11 as shown in Transmit Data path parity protection diagram) is flipped.

Based on the EIM/BLEI field of MTL_DPP_ECC_EIC register, software can corrupt any one bit of parity/data.

Hardware clears this bit once the respective parity bit is flipped.

Values:

• 0x0(DISABLE): Insert Parity error in MAC TFC data parity checker is disabled
• 0x1(ENABLE): Insert Parity error in MAC TFC data parity checker is enabled

When set to 1, parity/data bit of first valid input parity/data of the MTL RWC data parity checker (or at PC12 as shown in Receive data path parity protection diagram) is flipped.

Based on the EIM/BLEI field of MTL_DPP_ECC_EIC register, software can corrupt any one bit of parity/data.

Hardware clears this bit once the respective parity bit is flipped.

Values:

• 0x0(DISABLE): Insert Parity error in MAC TBU data parity checker is disabled
• 0x1(ENABLE): Insert Parity error in MAC TBU data parity checker is enabled

When set to 1, parity/data bit of first valid input parity/data of the AXI Slave Read data parity checker is (or at PC9 as shown in AXI slave Interface Data path parity protection diagram) flipped.

Based on the EIM/BLEI field of MTL_DPP_ECC_EIC register, software can corrupt any one bit of parity/data.

Hardware clears this bit once the respective parity bit is flipped.

Values:

• 0x0(DISABLE): Insert Parity error in AXI Slave read data parity checker is disabled
• 0x1(ENABLE): Insert Parity error in AXI Slave read data parity checker is enabled

When set to 1, parity/data bit of first valid input parity/data of the MCI Slave Write data parity checker(or at PC8 as shown in AXI slave Interface Data path protection diagram) is flipped. Based on the EIM/BLEI field of MTL_DPP_ECC_EIC register, software can corrupt any one bit of parity/data.

Hardware clears this bit once the respective parity bit is flipped.

Values:

• 0x0(DISABLE): Insert Parity error in MCI slave write data parity checker is disabled
• 0x1(ENABLE): Insert Parity error in MCI slave write data parity checker is enabled

When set to 1, parity/data bit of first valid input parity/data of the AXI Slave Write data parity checker(or at PC7 as shown in AXI slave Interface Data path protection diagram) is flipped. Based on the EIM/BLEI field of MTL_DPP_ECC_EIC register, software can corrupt any one bit of parity/data.

Hardware clears this bit once respective parity bit is flipped.

Values:

• 0x0(DISABLE): Insert Parity error in AXI slave write data parity checker is disabled
• 0x1(ENABLE): Insert Parity error in AXI slave write data parity checker is enabled

When set to 1, parity/data bit of first valid input parity/data of the RX Interface Data parity checker is (or at PC6 as shown in Receive data path parity protection diagram) flipped.

Based on the EIM/BLEI field of MTL_DPP_ECC_EIC register, software can corrupt any one bit of parity/data.

Following are the input data bus on which parity bits are generated based on the configuration selected:

• In AHB Config, hwdata_o In AXI config, wdata_m_o
• In DMA Config, mdc_wdata_o In MTL Config, ari_data_o
• Hardware clears this bit once the respective parity bit is flipped.

Values:

• 0x0(DISABLE): Insert Parity Error in Rx Interface Data parity checker is disabled
• 0x1(ENABLE): Insert Parity Error in Rx Interface Data parity checker is enabled

When set to 1, parity/data bit of first valid input parity/data of the MTL Tx Status FIFO parity checker (or at PC5 as shown in Transmit data path parity protection diagram) is flipped.

Based on the EIM/BLEI field of MTL_DPP_ECC_EIC register, software can corrupt any one bit of parity/data.

Hardware clears this bit once the respective parity bit is flipped.

Values:

• 0x0(DISABLE): Insert Parity Error in MTL TX Status FIFO parity checker is disabled
• 0x1(ENABLE): Insert Parity Error in MTL TX Status FIFO parity checker is enabled

When set to 1, parity/data bit of first valid input parity/data of the MTL Tx FIFO write data parity checker (or at PC4 as shown in Transmit data path parity protection diagram) is flipped.

Based on the EIM/BLEI field of MTL_DPP_ECC_EIC register, software can corrupt any one bit of parity/data.

Hardware clears this bit once the respective parity bit is flipped.

Values:

• 0x0(DISABLE): Insert Parity Error in MTL Tx FIFO write data parity checker is disabled
• 0x1(ENABLE): Insert Parity Error in MTL Tx FIFO write data parity checker is enabled

When set to 1, parity/data bit of first valid input parity/data of the DMA Tx/Rx Descriptor parity checker (or at PC3 as shown in Transmit data path parity protection diagram) is flipped.

Based on the EIM/BLEI field of MTL_DPP_ECC_EIC register, software can corrupt any one bit of parity/data.

Hardware clears this bit once the respective parity bit is flipped.

Values:

• 0x0(DISABLE): Insert Parity Error in DMA Tx/Rx Descriptor parity checker is disabled
• 0x1(ENABLE): Insert Parity Error in DMA Tx/Rx Descriptor parity checker is enabled

When set to 1, parity/data bit of first valid input parity/data of the DMA TSO header parity checker (or at PC2 as shown in Transmit data path parity protection diagram) is flipped.

Based on the EIM/BLEI field of MTL_DPP_ECC_EIC register, software can corrupt any one bit of parity/data.

Hardware clears this bit once the respective parity bit is flipped.

Values:

• 0x0(DISABLE): Insert Parity Error in DMA TSO Header parity checker is disabled
• 0x1(ENABLE): Insert Parity Error in DMA TSO Header parity checker is enabled

When set to 1, parity/data bit of first valid input parity/data of the Tx Interface data parity checker(or at PC1 as shown in Transmit data path parity protection diagram) is flipped.

Based on the EIM/BLEI field of MTL_DPP_ECC_EIC register, SW could corrupt any one bit of parity/data.

Following are the input data bus on which parity bits are generated based on the configuration selected:

• In AHB Config, hrdata_i In AXI config, rdata_m_i
• In DMA Config, mdc_rdata_i In MTL Config, ati_data_i
• Hardware clears this bit once the respective parity bit is flipped.

Values:

• 0x0(DISABLE): Insert Parity Error in Tx Interface Data parity checker is disabled
• 0x1(ENABLE): Insert Parity Error in Tx Interface Data parity checker is enabled

When set to 1, enables the parity check for the slave interface ports and disables the internal generation of parity for the input slave data port. When set to 0, disables the parity check for the slave interface ports and enables the internal parity generation for the input slave data port.

Values:

• 0x0(DISABLE): Parity on Slave Interface port is disabled
• 0x1(ENABLE): Parity on Slave Interface port is enabled

When set to 1,enables odd parity protection on all the external interfaces and when set to 0, enables even parity protection on all the external interfaces.

Values:

• 0x0(DISABLE): Odd Parity is disabled
• 0x1(ENABLE): Odd Parity is enabled

When set to 1, enables the parity protection for EQOS data path by generating and checking the parity on EQOS data path. When set to 0, disables the parity protection for EQOS data path.

Values:

• 0x0(DISABLE): Data path Parity Protection is disabled
• 0x1(ENABLE): Data path Parity Protection is enabled

When it is set to 0, indicate error injection on data; When it is set to 1, indicate error injection on ECC/Parity bits(need to check the address error injection mode is disabled).

This field indicates the bit location of DPP/ECC error injection, determination of error in Parity/ECC bits or Data (being protected) depends on the Error Injection Mode(EIM field).

Depending on the interface being used for error injection not all bits of this field are valid. Example, for error injection on a 64 bit data interface this field should be programmed to a value between 63 and 0.

In case of 2-bit error injection bit 0 is always included in error injection and this field should represent the second bit selection for error injection. If the second bit is programed at bit 0 when 2-bit error injection is enabled, DUT only inserts 1-bit error at bit 0.