Register Description

This section describes the registers of the I2C. Registers are on the pclk domain, but status bits reflect actions that occur in the ic_clk domain. Therefore, there is delay when the pclk register reflects the activity that occurred on the ic_clk side.

Some registers may be written only when the I2C is disabled, programmed by the IC_ENABLE register. Software should not disable the I2C while it is active. If the I2C is in the process of transmitting when it is disabled, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. The slave continues receiving until the remote master aborts the transfer, in which case the I2C could be disabled. Registers that cannot be written to when the I2C is enabled are indicated in their descriptions.

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 1. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved
6 IC_SLAVE_DISABLE R/W This bit controls whether I2Chas its slave disabled, which means once the presetn signal is applied, then this bit takes on the value of the configuration parameter IC_SLAVE_DISABLE. You have the choice of having the slave enabled or disabled after reset is applied, which means software does not have to configure the slave. By default, the slave is always enabled (in reset state as well). If you need to disable it after reset, set this bit to 1.

If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. 0: slave is enabled 1: slave is disabled

Reset value: IC_SLAVE_DISABLE configuration parameter. NOTE: Software should ensure that if this bit is written with ‘0,’ then bit 0 should also be written with a ‘0’.
5 IC_RESTART_EN R/W Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations.
  • 0: disable
  • 1: enable
When the RESTART is disabled, the DW_apb_i2c master is incapable of performing the following functions:
  • Sendinga START BYTE
  • Performing any high-speed mode operation
  • Performing direction changes incombined format mode
  • Performing aread operation with a 10-bit address

By replacing RESTART condition followed by aSTOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register.

Reset value: IC_RESTART_EN configuration parameter
4 IC_10BITADDR_MASTER or IC_10BITADDR_MASTER_ rd_only R/W or R

Ifthe I2C_DYNAMIC_TAR_UPDATE configuration parameter is set to “No” (0), this bit is named IC_10BITADDR_MASTER and controlswhether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master.

IfI2C_DYNAMIC_TAR_UPDATE is set to “Yes” (1), the function of this bit is handled by bit 12 of IC_TAR register, andbecomes a read-only copy called IC_10BITADDR_MASTER_rd_only.

0: 7-bit addressing

1: 10-bit addressing

Dependencies: IfI2C_DYNAMIC_TAR_UPDATE = 1, then this bit is read-only. If I2C_DYNAMIC_TAR_UPDATE = 0, then this bit can be read or write.

Resetvalue: IC_10BITADDR_MASTER configuration parameter
3 IC_10BITADDR_SLAVE R/W

When acting as a slave, this bit controls whether the DW_apb_i2c

responds to7- or 10-bit addresses.

0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, onlythe lower 7 bits of the IC_SAR register are compared.

1: 10-bit addressing. TheDW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register.

Reset value: IC_10BITADDR_SLAVE configuration parameter
2:1 SPEED R/W
These bits control at whichspeed the DW_apb_i2c operates; its setting isrelevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. This register should beprogrammed only with a value inthe range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updatesthis register with the value of IC_MAX_SPEED_MODE.
  • 1: standard mode (0to 100 kbit/s)
  • 2:fast mode (£ 400kbit/s)
  • 3: high speed mode (£3.4Mbit/s)
Reset value: IC_MAX_SPEED_MODEconfiguration
0 MASTER_MODE R/W This bit controls whether the DW_apb_i2c master isenabled.

0: master disabled

1: master enabled

Reset value: IC_MASTER_MODE configuration parameterNOTE: Software should ensure thatif this bit is written with ‘1,’ then bit 6 should also be written with a ‘1’.

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 2. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 3. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 4. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 5. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 6. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 7. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 8. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 9. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 10. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 11. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 12. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 13. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 14. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 15. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 16. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 17. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 18. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 19. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 20. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 21. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 22. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 23. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 24. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 25. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 26. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 27. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 28. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 29. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 30. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 31. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 32. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 33. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 34. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 35. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 36. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 37. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 38. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 39. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 40. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 41. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 42. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 43. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 44. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved

IC_CON

  • Name: I2C Control Register
  • Size: 7 bits
  • Address Offset: 0x00
  • Read/write access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.

This register can be written only when the I2C is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.

Table 45. I2C IC_CON Register Description
Bits Name Access Description
15:7 Reserved N/A Reserved