Future Work

This thesis presented only the very first steps of assessing the Real-Time Linux on RISC-V architecture. There is a huge number of possibilities to study this topic further as other related research is practically nonexistent. The future work could include, e.g., testing the effect of some additional kernel options, evaluating more stress categories, and looking into some kernel optimizations such as things related to the multi-core operation. Also, experiments from different hardware platforms, measurements about completely different metrics, and practical PREEMPT_RT development work would be valuable in the future. Studying these topics further would give important information regarding the possibilities of RISC-V architecture for practical industrial real-time applications.

As stated earlier, the kernel configuration used in this thesis is very minimal and real systems would certainly need some additional features of the Linux kernel to be enabled. Because of this, it would be beneficial to do some further research by enabling some of the most important additional kernel configuration options and testing how they affect the latency performance. Excluding obvious debugging options, a properly behaving Real-Time Linux kernel should not be significantly affected by this. However, some parts of these options could introduce substantial latencies and thus would need some optimization work before they could be considered acceptable to be used in a real-time configuration. Also, simultaneously perhaps even additional errors related to locking and general real-time behavior could be discovered and fixed.

As the Linux systems are very complex, there are plenty of other interesting metrics in addition to the latency that could be measured. Having more statistics from areas like memory usage, power consumption, and system throughput would be very valuable information about other aspects of using a Real-Time Linux on RISC-V. In addition, a wider range of stress categories could be tested and evaluated as this study completely ignores areas such as networking or other sources that cause a significant number of interrupts. Designing these additional stress categories would most certainly have to be done together with the enabling of additional kernel features.

Regarding the current system, it might be possible to do some additional optimization on the settings used in this study and achieve even lower latencies. For example, restricting some interrupts to certain cores by setting CPU affinity bits might bring slight improvement to the experienced latencies on other cores. Also, some code-level optimization would probably be possible. This optimization work should be targeted to areas amounting to the longest latencies as discussed previously. With these changes, the latencies could be even smaller than presented in this thesis. Also, the RISC-V architecture itself is under continuous development having new features proposed and ratified regularly. For example, there is ongoing work to design and implement a better and more flexible interrupt controller hardware. This proposal for Core-Local Interrupt Controller (CLIC) aims to add completely new features to the current PLIC-based architectures. Significant improvements would include support for interrupt preemption and selective vectoring among others. These features could be useful or even critical for some time-sensitive applications, so in the future, RISC-V would be even more capable of handling different real-time workloads. However, it should be noted that these details are subject to change as the CLIC specification is still in the very early development phase. There will certainly be other similar development of new hardware blocks in the future.

Alongside RISC-V hardware, also the general software support will continue to improve. The most important pieces of software, e.g., compilers, debugging tools, and Linux kernel already have great support for RISC-V but of course, it is still a bit behind other older and more established architectures. For example, every feature of the Linux kernel is not yet fully supported when RISC-V architecture is used. But most certainly the ever-growing community and commercial interest will bring fixes to some of these issues. Overall, the whole RISC-V ecosystem is getting better every day.

In the end, the single most important thing for using Real-Time Linux on RISC-V architecture would be official support. This would guarantee the functionality to a certain degree, as at that point, the community using that product would be considerably larger. Starting from kernel v6.6 LTS, RISC-V has become the official support for RT-Linux, and most of StarFive JH-7110 driver code has been accepted in Kernel 6.6, which is of great advantage for JH-7110 to enter RT-Linux commercial industrial. Based on this article, the RISC-V architecture should be fully suitable for higher demand industrial applications.