2-Lane MIPI CSI Pin Definition

The following figure and table describe the 2-lane MIPI DSI definition:

Figure 1. 2-Lane MIPI CSI Pin Definition
Table 1. 2-Lane MIPI DSI Pin Definition
No. Definition Description Voltage
1 GND Ground -
2 50R_MIPIRX_DN0 MIPI Input Lane 0 Negative 1.8V
3 50R_MIPIRX_DP0 MIPI Input Lane 0 Positive 1.8V
4 GND Ground -
5 50R_MIPIRX_ DN1 MIPI Input Lane 1 Negative 1.8V
6 50R_MIPIRX_ DP1 MIPI Input Lane 1 Positive 1.8V
7 GND Ground -
8 50R_MIPIRX_CLK0N MIPI Input Clock 0 Negative 1.8V
9 50R_MIPIRX_CLK0P MIPI Input Clock 0 Positive 1.8V
10 GND Ground -
11 CSI_PWDN0_GPIO18 CSI power control 3.3V
12 NC NC -
13 CSI_I2C_SCL_GPIO16 CSII2C SCL 3.3V
14 CSI_I2C_SDA_GPIO17 CSII2C SDA 3.3V
15 +3.3 V Power Voltage for digital circuit 3.3 V 3.3V