Baseboard Management Controller: Typically, an independent microprocessor or system-on-chip with associated firmware in a computer system that completes out-of-band systems monitoring and management-related tasks.


Dynamic Random Access Memory.


Embedded DRAM.

Instruction Set

A group of commands for a CPU in machine language that can refer to all possible instructions for a CPU, or a subset of instructions to enhance its performance in specific situations, and includes:
  • Instruction length - which can vary, Opcodes - the command to be carried out.
  • Operands - on which the command will operate.
  • Registers - internal locations that are limited in number and ability while quick to access.
  • Memory - external storage - a larger and more versatile number of locations that are slower to access.


Instruction Set Architecture.


Keyboard, video, mouse redirection over IP


A circuit that has two stable states that is used to store state information, known as a bi-stable multi-vibrator.


Low Power Double Data Rate


Intelligent Platform Management Interface


Microprocessor without Interlocked Pipelined Stages—a reduced instruction set computer (RISC) instruction set architecture developed by MIPS Computer Systems, now MIPS Technologies, based in the United States, that influenced later RISC architectures.


Memory Management Unit.


A field within an instruction or instruction set that specifies the way the operand or the effective address is determined.


Message Signal Interrupt.


Network interface controller

OS-level Sandboxing

A form of sandboxing implemented by the pointer masking proposal. There is no guarantee that sandboxed code cannot modify the pointer mask and therefore the sandbox does not allow modifying pointer masks in user mode.


Peripheral Component Interconnect


Peripheral Component Interconnect Express


Short for pull down. When talking about PD in circuit layout, it is always used to indicate the need of a pull-down resistor (PD).

Pull-up and Pull-down resistors are used to correctly bias the inputs of digital gates to stop them from floating about randomly when there is no input condition


Platform-Level Interrupt Controller. The PLIC is a device designed to handle interrupts other than timer and software in RISC-V.


Provides security isolation, and a means to reduce code defects because code does not have to check for illegal values. Privileged contains state, is used primarily to run applications and can be used to debug implementations. It defines CSR address space and content trap when taken increases privilege mode (say from U to S) trap when taken stays at the current privilege mode access more than even M mode. Its addresses reserved in ISA. address includes highest mode that access the CSR and if it is r/w/rw/none preserve bits already there when you change a field.


ISA Profile is a set of extensions (instructions, state and behaviors) that users can depend on working together. Extensions are either required, optional, unsupported, or incompatible. RISC-V has defined two Profile types: Application (RVAyy)--appropriate for Linux-class and other embedded designs with more sophisticated ISA needs—and Micro-controller (RVMyy)-- appropriate for cost-sensitive application-optimized embedded designs running bare-metal or simple RTOS environments.

Pseudo Instructions

In support of a core design goal for RISC-V ISA - high-performance - pseudo instructions often include special commands to the assembler. The use of pseudo instructions supports a policy of keeping the instruction set as small as possible, while supporting optimization and adding clarity to software programming. For example, the use of a pseudo instruction enables loading into memory with a 32-bit offset (called big) that is not directly available, because only 16-bit offsets are permitted.


Page Table Entry - an entry in the data structure used by a virtual memory system in a computer operating system to store the mapping between virtual addresses (used by the program executed by the accessing process) and physical addresses (used by the hardware, or more specifically, by the RAM subsystem), that enables access data in memory


Short for pull up. When talking about PU in circuit layout, it is always used to indicate the need of a pull-up resistor (PU).

Pull-up and Pull-down resistors are used to correctly bias the inputs of digital gates to stop them from floating about randomly when there is no input condition


Parallel Telemetry Processor - a high- speed virtual processor architecture.


A group of flip-flops with each flip-flop capable of storing one bit of information. The simplest register is one that consists of only flip-flops with no external gates.


Reduced Instruction Set Computer architecture. Information processing using any of a family of microprocessors that are designed to execute computing tasks with the simplest instructions in the shortest amount of time possible. RISC-based machines execute one instruction per clock cycle as opposed to CISC (Complex Instruction Set Computer) machines that can have special instructions as well as instructions that take more than one cycle to execute.

Segmentation fault

A failure condition caused by a memory access violation in hardware operating with memory protection. The fault process notifies the operating system (OS) that software has attempted to access a restricted area of memory.


Secure Hash Algorithms—a family of cryptographic hash functions published by the National Institute of Standards and Technology as a U.S. Federal Information Processing Standard that started with what is now known as SHA-0, a retronym used for the original (1993) 160-bit hash function published under the name "SHA".




Static Random Access Memory.


True Random Number Generator - also known as HRNG, or Hardware Random Number Generator - a device that generates random numbers from a physical process, rather than by means of an algorithm. Such devices are often based on microscopic phenomena that generate low-level, statistically random "noise" signals, like thermal noise, the photoelectric effect involving a beam splitter, and other quantum phenomena.