PVRSRV_DEVICE_CONFIG

struct _PVRSRV_DEVICE_CONFIG_
{
/*! OS device passed to SysDevInit (linux: 'struct device') */
void *pvOSDevice;
/*!
*! Service representation of pvOSDevice. Should be set to NULL when the
*! config is created in SysDevInit. Set by Services once a device node has
*! been created for this config and unset before SysDevDeInit is called.
*/
struct _PVRSRV_DEVICE_NODE_ *psDevNode;
/*! Name of the device */
IMG_CHAR *pszName; // typically the name of the SoC
/*! Version of the device (optional) */
IMG_CHAR *pszVersion;
/*! Register bank address */
IMG_CPU_PHYADDR sRegsCpuPBase; // physical address of the GPU register bank
/*! Register bank size */
IMG_UINT32 ui32RegsSize; // size in bytes of the GPU register bank
/*! Device interrupt number */
IMG_UINT32 ui32IRQ; // IRQ number for the GPU device
PVRSRV_DEVICE_SNOOP_MODE eCacheSnoopingMode;
/*! Device specific data handle */
IMG_HANDLE hDevData; // handle (actually a pointer) to RGX_DATA
/*! System specific data. This gets passed into system callback func-tions */
IMG_HANDLE hSysData; // handle (actually a pointer) to optional SoC specific device data
IMG_BOOL bHasNonMappableLocalMemory;
/*! Indicates if system supports FBCDC v3.1 */
IMG_BOOL bHasFBCDCVersion31;
/*! Physical Heap definitions for this device.
* eDefaultHeap must be set to GPU_LOCAL or CPU_LOCAL. Specifying any other value
* (e.g. DEFAULT) will lead to an error at device discovery.
* pasPhysHeap array must contain at least one PhysHeap, the declared default heap.
*/
PVRSRV_PHYS_HEAP eDefaultHeap;
PHYS_HEAP_CONFIG *pasPhysHeaps; // pointer to array of physical heap configs
IMG_UINT32 ui32PhysHeapCount; // physical heap count
/*!
*! Callbacks to change system device power state at the beginning and end
*! of a power state change (optional).
*/
PFN_SYS_PRE_POWER pfnPrePowerState; // should perform SoC specific set-up required pre-power
transition for this device
PFN_SYS_POST_POWER pfnPostPowerState; // should perform SoC specific setup that is required
post-power transition for this device
PFN_SYS_GET_POWER pfnGpuDomainPower; // should query the state of the SoC power domain
which supplies the GPU
/*! Callback to obtain the clock frequency from the device (optional) */
PFN_SYS_DEV_CLK_FREQ_GET pfnClockFreqGet; // add this call back the current core clock
frequency (note: DFVS can change clock frequency dynamically
#if defined(SUPPORT_SOC_TIMER)
/*! Callback to read SoC timer register value (mandatory). */
PFN_SYS_DEV_SOC_TIMER_READ pfnSoCTimerRead;
#endif
Confidential Imagination Technologies
PowerVR Graphics GPU Services 11 Revision 1.17.83
/*!
*! Callback to handle memory budgeting. Can be used to reject alloca-tions
*! over a certain size (optional).
*/
PFN_SYS_DEV_CHECK_MEM_ALLOC_SIZE pfnCheckMemAllocSize;
/*!
*! Callback to perform host CPU cache maintenance. Might be needed for
*! architectures which allow extensions such as RISC-V (optional).
*/
PFN_SYS_DEV_HOST_CACHE_MAINTENANCE pfnHostCacheMaintenance;
IMG_BOOL bHasPhysicalCacheMaintenance;
#if defined(SUPPORT_TRUSTED_DEVICE)
/*!
*! Callback to send FW image and FW boot time parameters to the trusted
*! device.
*/
PFN_TD_SEND_FW_IMAGE pfnTDSendFWImage;
/*!
*! Callback to send parameters needed in a power transition to the trusted
*! device.
*/
PFN_TD_SET_POWER_PARAMS pfnTDSetPowerParams;
/*! Callbacks to ping the trusted device to securely run RGXStart/Stop() */
PFN_TD_RGXSTART pfnTDRGXStart;
PFN_TD_RGXSTOP pfnTDRGXStop;
#endif /* defined(SUPPORT_TRUSTED_DEVICE) */
/*! Function that does device feature specific system layer initialisa-tion */
PFN_SYS_DEV_FEAT_DEP_INIT pfnSysDevFeatureDepInit;
#if defined(SUPPORT_LINUX_DVFS) || defined(SUPPORT_PDVS)
PVRSRV_DVFS sDVFS; // Used by the IMG DVFS governor
#endif
#if defined(SUPPORT_ALT_REGBASE)
IMG_DEV_PHYADDR sAltRegsGpuPBase;
#endif
/*!
*! Indicates if device physical address 0x0 might be used as GPU memory
*! (e.g. LMA system or UMA system with CPU PA 0x0 reserved by the OS,
*! but CPU PA != device PA and device PA 0x0 available for the GPU)
*/
IMG_BOOL bDevicePA0IsValid;
/*!
*! Callback to notify system layer of device errors.
*! NB. implementers should ensure that the minimal amount of work is
*! done in the callback function, as it will be executed in the main
*! RGX MISR. (e.g. any blocking or lengthy work should be performed by
*! a worker queue/thread instead.)
*/
PFN_SYS_DEV_ERROR_NOTIFY pfnSysDevErrorNotify;
Confidential Imagination Technologies
PowerVR Graphics GPU Services 12 Revision 1.17.83
/*!
*! Slave DMA channel request callbacks
*/
PFN_SLAVE_DMA_CHAN pfnSlaveDMAGetChan;
PFN_SLAVE_DMA_FREE pfnSlaveDMAFreeChan;
/*!
*! Conversion of device memory to DMA addresses
*/
PFN_DEV_PHY_ADDR_2_DMA_ADDR pfnDevPhysAddr2DmaAddr;
/*!
*! DMA channel names
*/
IMG_CHAR *pszDmaTxChanName;
IMG_CHAR *pszDmaRxChanName;
/*!
*! DMA device transfer restrictions
*/
IMG_UINT32 ui32DmaAlignment;
IMG_UINT32 ui32DmaTransferUnit;
/*!
*! System-wide presence of DMA capabilities
*/
IMG_BOOL bHasDma;
};

• PVRSRV_DEVICE_SNOOP_NONE - This means that neither the CPU nor GPU supports having their caches snooped.
• PVRSRV_DEVICE_SNOOP_CPU_ONLY - This means that the CPU will allow the GPU to inspect the CPU cache. The GPU cache is not visible to the CPU.
• PVRSRV_DEVICE_SNOOP_DEVICE_ONLY - This means that the GPU will allow the CPU to inspect the GPU cache. The CPU cache is not visible to the GPU.
• PVRSRV_DEVICE_SNOOP_CROSS - This means that both CPU and GPU support cache snooping. They can each inspect the others caches.
• PVRSRV_DEVICE_SNOOP_EMULATED - This means that neither the CPU nor GPU supports having their caches snooped but the GPU software/firmware should emulate snooping by maintaining the CPU and GPU data caches appropriately.

• PVRSRV_PHYS_HEAP_GPU_LOCAL - This means that the device allocations will be fulfilled with memory that is physically (in terms of access time and throughput) closest to the GPU.
• PVRSRV_PHYS_HEAP_CPU_LOCAL - This means that the device allocations will be fulfilled with memory that is physically (in terms of access time and throughput) closest to the CPU. eDefaultHeap must be set to a physical heap provided in the pasPhysHeaps array member. bDevicePA0IsValid should be set to IMG_TRUE if device physical address 0x0 is available and can be accessed by the GPU, IMG_FALSE otherwise.

• LMA with local memory mapped in the GPU from physical address 0x0.
• UMA with CPU physical address != device physical address and 0x0 is a valid device address.

• Regular UMA with device and CPU physical address 0x0 reserved by the OS.
• UMA with a memory protection unit forbidding GPU accesses outside of specific ranges.

• pfnSlaveDMAGetChan and pfnSlaveDMAFreeChan: Should return and free DMA Engine Channels by their DMA driver-relative names. Upper GPU Service layers will also make use of the fields right below when calling these two functions.
• pszDmaTxChanName and pszDmaRxChanName: System DMA Engine driver names for send and receive channels. The above assignments will depend on these two, and should be set to whatever channel names for the DMA Engine driver the customer wants to connect with the Services DMA API.
• pfnDevPhysAddr2DmaAddr: Should perform the translation between RGX device physical addresses and DMA addresses that the underlying DMA device understands. Necessary for mapping DMA buffers before a SG transfer and programming the DMA hardware.
• ui32DmaAlignment and ui32DmaTransferUnit are used if the hardware has alignment and transfer size restrictions. ui32DmaAlignment is in bytes and refers to the byte alignment required at the start of a transfer buffer. ui32DmaTransferUnit is in bytes and refers to the minimum size of transfer supported by the hardware.
• bHasDma: Informs the upper layers of the Services kernel driver that all of the above DMA functionality is actually present in the system.