Camera MIPI IN/OUT Interface

The camera MIPI IN/OUT interface of JH-7110 has the following features.

• CSI-2 RX Controller
  • Support of the MIPI CSI-2 v1.3 protocol over DPHY PPI interface up to a maximum of 4 ×1.5 Gbps
  • Support Pixel interface
  • Byte to pixel conversion one-pixel interface
  • Direct memory dump using packed byte operation
  • Flow control
  • Payload FIFO operation
  • Monitoring of frame for automatic start/end of frame synchronization when enabled
  • Extended Functions for Virtual Channel extension and RAW16/20 modes as defined for MIPI CSI-2 V2.0 Specification
  • Can be enabled by setting the V2P0_SUPPORT_ENABLE bit in the STATIC_CFG configuration register
  • Support the data types of RAW6, RAW7, RAW8, RAW10, RAW12, RAW14, RAW16, and RAW20
  • Virtual Channel Extension (VCX) is employed - Effects ECC handing
• MIPI RX DPHY
  • Support standard 8b PPI interface compliant of MIPI DPHY Spec.
  • Support 1 clock lane and up to 4 Data Lanes scalability in DPHY mode.
  • Support HS-Rx data rate from 80 Mbps up to 1.5 Gbps. (DPHY)
  • Support LS-Rx data rate of 10 Mbps and ultra-low-power mode.
  • Support Triggers, ULPS, and LPDT.
  • Support on-die terminated and non-terminated operation with switchable termination integrated.
  • Support fault detection of sequence error. (Error report)
  • Support clock and data lane swapping function.
  • Build-in BISTTX for at-speed testing