MIPI Display Interface

The MIPI display interface of JH-7110 has the following features.

• MIPI TX DPHY
  • Support standard 8-bit PPI interface compliant with MIPI specifications.
  • Support 1 Clock Lane and up to 4 Data Lanes scalability.
  • Support HS-Tx data rate from 80 Mbps up to 2.5 Gbps. (Per lane)
  • Support LP-Tx data rate of 10 Mbps.
  • Support LP-Tx ULPS and LPDT.
  • Support reverse direction ULPS and LPDT.
  • Support on-die transmitter termination.
  • Support clock and data lane swapping function.
  • Minimalized lane-to-lane skew of multi-data lanes.
  • Smaller frequency step supports more power efficiency of the whole DPHY ecosystem.
  • Built-in LDO with 1.2 V voltage output to meet LS-Tx DC spec.