Feature Set

• Fully compliant with the RISC-V ISA specification
• 4 × RV64GC U74 Application Cores
  • 32 KB L1 I-cache with ECC
  • 32 KB L1 D-cache with ECC
  • 8 Region Physical Memory Protection
  • Sv39 Virtual Memory support with 38-bit (Physical Address)
• U74 is fully-coherent
• Integrated 2 MB L2 Cache with ECC
  • The L1 Instruction Cache and the L2 Cache can be configured into high-speed deterministic SRAMs
• Real-time Capabilities, and internal time counting integrated
• Debug with instruction trace

• support general DMA operations and Scatter Gather DMA
• Support up to 4 gather&scatter channels
• Support up to 32 requests
• Support AXI4 bus width of 64-bit
• Support memory to memory, memory to peripheral, peripheral to memory and peripheral to peripheral transfer
• Can generate both interrupts for transmission completion and for transmission failure due to errors
• Support arbitration - fixed and round robin
• Provide status information of each transfer for each channel in the status register

• DDR controller
  • DDR4/3 and LPDDR4/3 modes and signaling, rates up to the speed of 2,800 Mbps
  • The maximum size of DDR4/3 and LPDDR4/3 is 8 GB
  • Internal deskew PLLs for high speed, low jitter clock generation (clk4x)
  • x16/x32 data path interface extendable
  • DRAM ranks of 1, 2 (could be asymmetric)
  • Bank-interleaving and rank-interleaving (symmetric ranks only)
  • Support for dynamic DRAM frequency scaling
  • Automated clock gating of internal logics
  • Error-correction code (SECDED) to select DRAM memory space
  • Address region-based security control support
  • Automated low power control of DRAM devices
  • AMBA AXI4 protocol for main data path interface for DDR controller
  • AMBA APB4 protocol for configuration register access interface for DDR controller
  • Flexible refresh control
    • Automated adjustment of the refresh interval
    • Pulled-in or postponed refreshes
    • Dynamic per-bank / all-bank refresh switching
    • Opportunistic advanced per-bank refresh
  • Open page based advanced page policy
    • Programmable timeout pre-charge
    • Auto pre-charge for reducing command congestion
  • Independent read and write timing adjustments with auto-calibration
  • Various power-down modes for low power including self-refresh support
  • DFI 4.0 specification between DDR controller and DDR PHY
• DDR PHY
  • High resolution write/read timing control
  • Per-bit deskew on the write data path
  • Per-bit deskew on the read data path
  • Support for multiple leveling/training modes through PHY evaluation mode
  • Register programming interface to all PHY parameters
  • PHY independent mode training logic
  • Write/read data timing per-chip select
  • Low-power modes
  • Low-speed test interface (PHY BIST)
  • At-speed ATPG support (OPCG)
  • DBI support
  • PHY controller frequency ratio of 2:1
  • IO calibration
  • JTAG interface
  • Boundary-scan support
  • Testability features

• Programmable master mode
• Data rate up to 100 Mbps
• 1/2/4 data-bit and 2-chip-select
• Support XIP mode and boot mode
• Separate data input and output bit

• Support eMMC 5.0/SD 3.0
• Support 4-bit and 8-bit eMMC data width
• Support 512B block size
• Support devices with capacity up to 256 GB
• Support speed mode: Legacy/High SDR/High DDR/HS200
• Identification mode
• MMC full-speed mode
• MMC high-speed mode
• MMC DDR mode

• Compatible with SD3.0
• Support SD/SDHC/SDXC, with SDXC capacity 32 GB - 2 TB.
• Compatible with MMC5.0
• Support 4-bit data width
• Support the following speed modes:
  • DEFAULT
  • HIGHSPD
  • UHSI_SDR12

• CSI-2 RX Controller
  • Support of the MIPI CSI-2 v1.3 protocol over DPHY PPI interface up to a maximum of 4 ×1.5 Gbps
  • Support Pixel interface
  • Byte to pixel conversion one-pixel interface
  • Direct memory dump using packed byte operation
  • Flow control
  • Payload FIFO operation
  • Monitoring of frame for automatic start/end of frame synchronization when enabled
  • Extended Functions for Virtual Channel extension and RAW16/20 modes as defined for MIPI CSI-2 V2.0 Specification
  • Can be enabled by setting the V2P0_SUPPORT_ENABLE bit in the STATIC_CFG configuration register
  • Support the data types of RAW6, RAW7, RAW8, RAW10, RAW12, RAW14, RAW16, and RAW20
  • Virtual Channel Extension (VCX) is employed - Effects ECC handing
• MIPI RX DPHY
  • Support standard 8b PPI interface compliant of MIPI DPHY Spec.
  • Support 1 clock lane and up to 4 Data Lanes scalability in DPHY mode.
  • Support HS-Rx data rate from 80 Mbps up to 1.5 Gbps. (DPHY)
  • Support LS-Rx data rate of 10 Mbps and ultra-low-power mode.
  • Support Triggers, ULPS, and LPDT.
  • Support on-die terminated and non-terminated operation with switchable termination integrated.
  • Support fault detection of sequence error. (Error report)
  • Support clock and data lane swapping function.
  • Build-in BISTTX for at-speed testing

• Sensor Interface
  • Support up to 1080P @30fps CMOS RGGB image sensor with the output format of RAW
  • Support 1 MIPI and 1 DVP sensor input interface
  • Support 12-bit sensor data input
• Image processing engine
  • Built-in color pattern generation
  • Sensor black level compensation
  • Defective pixel correction
  • R/G/B LUT for sensor linearisation correction
  • Image analysis for AE, AWB, and AF
  • Programmable histogram analysis
  • White balance control
  • Lens shading compensation
  • Color shading compensation
  • CMOS sensor spatial crosstalk cancellation (Gr and Gb balance filter)
  • Advanced Bayer CFA color interpolation
  • False-color suppression
  • Advanced edge control and enhancement
  • R/G/B Gamma LUT
  • Color correction matrix
  • Color space conversion
  • Brightness/contrast and hue/saturation adjustment
  • Global tone mapping
  • Spatial noise reduction
• Back-end processing
  • Seamless digital scale down from 1/4 × to 1 ×
  • Support up to 3 channel video streaming

• IMG BXE-4-32 MC1 with work frequency up to 600 MHz (400 MHz by default)
• Fully compliant with the following APIs:
  • Support OpenCL 3.0
  • Support OpenGL ES 3.2
  • Support Vulkan 1.2
• Tile-based deferred rendering architecture for 3D graphics workloads, with concurrent processing of multiple tiles
• Programmable high-quality image anti-aliasing
• Fine-grain triangle culling
• Support for DRM security
• Support for GPU visualization
  • Up to 8 virtual GPUs
  • Support for IMG Hyper-Lane technology, with 8 hyper-lanes available
  • Separate IRQs per OSID
• Multi-threaded Unified Shading Cluster (USC) engine incorporating pixel shader, vertex shader, and GP-GPU (compute shader) functionality
• USC incorporates an ALU architecture with high SIMD efficiency
• Fully virtual memory addressing (up to 64 GB address space), supporting unified memory architecture
• Fine-grained task switching, workload balancing, and power management
• Advanced DMA driven operation for minimum host CPU interaction
• System Level Cache (SLC)
• Specialized Texture Cache Unit (TCU)
• Compressed texture decoding
• Lossless and/or visually lossless low area image compression - the Imagination
• frame buffer compression and decompression (TFBC) algorithm
• Dedicated processor for B-Series core firmware execution
  • Single-threaded firmware processor with a 2 KB instruction cache and a 2 KB data cache.

• H.265 Encoder, 1080p@30fps
• I/P slices
• CTU64
  • Supported Prediction Unit (PU) size: 16 × 16, 8 × 8
  • Supported Transform Unit (TU) size: 16 × 16 to 8 × 8
• Parallel tools
  • Multi-slice: Independent slice segment and a dependent slice segment
• High-performance CABAC encoding
• In-loop de-blocking filtering
• Loop filtering across the slice
• Lossless coding
• Noise reduction
• Rate Control
  • VBR, CBR, and ABR
  • ROI support

• 1-channel 4K@30fps or 8-channel 1080p@30fps
• Support Format 420, 8-bit/10-bit
• Support I/P type slice
• H.265 Main/Main10, L5.1 up to 4096 × 2160@60fps
• H.264 High/High10, L5.2 up to 4096 × 2160@60fps
• 128bit AXI Bus interface
• Support Lossless Compression for frame buffer to save bandwidth
• Frame-based Processing promises the lowest burden to the host processor for video operation
• Generating an interrupt when(ever) a specified number of MB-/CTU-rows are reached for low delay decoding
• H.264 decoding tools including:
  • Compatible with the ITU-T Recommendation H.264 specification
  • Support MVC Stereo High Profile
  • Support CABAC
  • Support CAVLC
  • Variable block size (16 × 16, 16 × 8, 8 × 16, 8 × 8, 4 × 8, and 4 × 4)
  • Interlaced coding tools are NOT supported
  • FMO/ASO is NOT supported
• H.265 decoding tools include:
  • Compatible with ISO/IEC 23008-2 high-efficiency video coding
  • I/P slices
    • All intra-prediction modes
    • All inter-prediction modes
  • Variable CTU size: 64 × 64 to 16 × 16
    • Variable Transform Unit (TU) size: 32 × 32 to 4 × 4
    • Variable Prediction Unit (PU) size: 64 × 64 to 4 × 4
  • Advanced Motion Vector Prediction (AMVP) and merge mode
  • ¼ Motion compensation with 8 tap filters
  • Uniform reconstruction quantization (URQ)
  • High-performance CABAC decoding
  • In-loop de-blocking filtering
  • Sample Adaptive Offset (SAO)
  • Loop filtering across slice/tile boundaries
  • Data reporting to the external host
  • Robust error concealment
  • Sequence change detection

• 290 MPixel/sec for YUV420, 210 MPixel/sec for YUV422, 140 MPixel/sec for YUV444
• Bit rate 480Mbps (MJPG 8M 30fps 422 1:8)
• Baseline/Extended sequential ISO/IEC 10918-1 JPEG compliance
• Compliant with Motion JPEG
• Support 1 or 3 color components
• 8-bit or 12-bit samples for each component - configurable
• Support 4:2:0, 4:2:2, 4:4:0, 4:4:4 and 4:0:0 color format (Maximum 6 8 × 8 blocks in 1 MCU)
• Support from 16 × 16 pixels to 32K × 32K (32,768 × 32,768)
• Support ROI (Region of Interest) - decoder only
• Support 422/444 packed mode for all color formats
• After conversion to 422/444 color format
• Value-added Features for Encoding
  • Partial mode for encoding
  • On-the-fly rotator/mirror
• Value-added features for decoding
  • Partial mode for decoding
  • ROI (Region of Interest)
  • On-the-fly rotator/mirror
  • On-the-fly downsample

• DP: RGB101010, RGB656, RGB666, RGB888 output formats
• DPI: RGB101010, DPI_D16/18/24 output formats
• Pixel inputs accepted from multiple RGB and YUV formats
• Color Space Conversion BT.2020 and BT.709
• Pixel output is up to 30-bit RGB in multiple formats
• Support ARGB888 and Mask cursor formats
• A separate Look-Up Table for Dither
• A separate Look-Up Table for Gamma Correction
• Overlay with coordinate generator with 6 image layers shared by 2 display panels (screens)
• Alpha Blending: 8 Porter Duff Blending modes
• Vertical and horizontal scaling
• Horizontal 3/5 tap; vertical 3 tap
• Programmable filter order
• 15.16 fixed point scaling factor
• Default display: 1080p
• Maximum display: 4K2K
• Independent sync and blank signals for each display
• Independent gamma and dither tables for each display
• Support 24-bit RGB parallel display interface up to 1280 × 720p@60fps or 1920 × 1080p@30fps

• Compliant with HDMI2.0, HDMI1.4, and DVI1.0 specifications
• Up to 6 Gbps per data channel
• Support YUV4:4:4, YUV4:2:2, YUV4:2:0 and RGB4:4:4 video format
• Support 8/10/12-bit color depth
• Support standard I2C master interface for DDC interface
• Support programmable output swing, termination, and pre-emphasis
• Support 8-channel I2S for audio, and up to 192 KHz audio sampling rate
• Support display resolution up to 4K@30fps

• Support standard 8-bit PPI interface compliant with MIPI specifications.
• Support 1 Clock Lane and up to 4 Data Lanes scalability.
• Support HS-Tx data rate from 80 Mbps up to 2.5 Gbps. (Per lane)
• Support LP-Tx data rate of 10 Mbps.
• Support LP-Tx ULPS and LPDT.
• Support reverse direction ULPS and LPDT.
• Support on-die transmitter termination.
• Support clock and data lane swapping function.
• Minimalized lane-to-lane skew of multi-data lanes.
• Smaller frequency step supports more power efficiency of the whole DPHY ecosystem.
• Built-in LDO with 1.2 V voltage output to meet LS-Tx DC spec.

• PCIe2.0 Controller
  • Support 2 PCIe2 .0 x1 interface with 2 PCIe2.0 controller
  • Support link rate of 2.5, 5.0 GT/s per lane, and 32-bit PIPE interface
  • PHY Interface for PCI Express (PIPE), Revision 4.4.1/5.1.1 compliant
  • Designed for Endpoint, Rootport, and dual-mode/shared silicon
  • 128-byte maximum payload size
  • 1 Virtual Channel (VC)
  • Up to 64 Physical Functions (in Endpoint mode)
  • Configurable Receive and Transmit buffer size
  • Advanced Error Reporting (AER) support
  • ECRC generation and check support
  • Integrated Clock Domain Crossing (CDC) to support user-selected frequency for the Bridge
  • Lane reversal support
  • Alternate Routing ID Interpretation (ARI)
  • Legacy PCI Power Management support
  • Clock and power gating support
  • Native Active State Power Management L0s and L1 state support
  • Power Management Event (PME message)
  • MSI (up to 32) and INT message support
  • MSI-X Capability support
  • Latency Tolerance Reporting (LTR)
  • L1 PM Substates with CLKREQ
  • SR-IOV support with up to 512 virtual functions
  • Address Translation Service, including Page Request interface
  • Process Address Space ID (PASID)
  • VPD Capability support
  • TLP Processing Hints
• PCIe2.0 PHY
  • Compatible with PCIe/USB3/SATA base Specification
  • Fully compatible with the PIPE3.1 interface specification
  • Data rate configurable to 1.5G/2.5G/3G/5G/6G for different application
  • Support 16-bit or 32-bit parallel interface when encode/decode enabled
  • Support 20-bit parallel interface when encode/decode bypassed
  • Support flexible reference clock frequency
  • Support 100 MHz differential reference clock input or output (optional with SSC) in PCIe Mode
  • Support Spread-Spectrum clock (SSC) generation and receiving from -5000ppm to 0ppm
  • Support programmable transmit amplitude and De-emphasis
  • Support TX detect RX function in PCIe and USB3.0 Mode
  • Support Beacon signal generation and detection in PCIe Mode
  • Support Low-Frequency Periodic Signaling (LFPS) generation and detection in USB3.0 Mode
  • Support COMWAKE, COMINIT, and COMRESET (OOB) generation and detection in SATA Mode
  • Support L1 sub-state power management
  • Support RX low latency mode in SATA operation mode
  • Support Loopback BERT and Multiple Pattern BIST Mode

• 1 × USB2.0/3.0 controller (port)
  • USB Interface:
    • Compliant with USB 3.0 Specification
    • Compliant with xHCI 1.0 Specification
    • SuperSpeed, Hi-Speed, and Full-Speed supported
    • Single USB2.0 Port
    • Single USB3.0 Port (By reusing 1 of the PCIe2.0 lanes)
    • USB 3.0 PIPE interface compliant
    • USB 2.0 UTMI+ interface compliant
    • USB2 L1/L2 Support
    • USB3 U1/U2/U3 Support
  • Application Interface:
    • AXI4 Master Interface with 64-bit data and 32-bit address
    • APB4 Slave interface with 32-bit data and address
  • Dual Mode Operation:
    • HW selectable default mode selection supporting operation without any SW interaction
    • Programmable runtime mode change
    • Host Negotiate Protocol (HNP) support
    • SRP support
    • Provide separate power domains for host and peripheral device logics
  • Host Mode (CDNSXHCI):
    • Support configurable total slots (maximum of 32)
    • 32 endpoints per slot
    • Support 256 Primary Streams
    • MSI Support
    • Root Hub functionality implemented
    • xHCI Dynamic and Static Low Power Management Support
    • xHCI DMA engine with 64-bit @ 125 MHz Full Duplex Data Path
  • Peripheral Mode (USBSS-DEV):
    • Support 8 endpoints for both read and write, and Endpoint #0 supports control transfers
    • Scatter-gather DMA
    • Dynamic data buffering
  • Integrated Protocol Stack
    • Memory integration
    • Clock, reset and power management integration
• USB2.0 PHY
  • Compliant with USB2.0 and USB1.1 specification
  • Compliant with UTMI Specification Version 1.0
  • Support HS (480 Mbps)/FS (12 Mbps)/LS (1.5 Mbps) modes
  • All required terminations, including 1.5 K Ω pull-up on DP and DM, and 15 K Ω pull-down on DP and DM are internal to the chip
  • 16-bit, 30 MHz or 8-bit, 60 MHz parallel interface for HS/FS
  • Serializing for transmitting data stream and De-serializing for receiving the data stream
  • USB Data Recovery and Clock Recovery on receiving
  • Integrated Bit Stuffing and NRZI encoding for Transmit
  • Integrated Bit Un-Stuffing and NRZI decoding for Receive
  • SYNC and EOP generation on transmit packets and detection on receive packets
  • Support termination calibration with the external resistor
  • Support scan test of digital block
  • Built-in self-test for production testing
  • Support USB suspend state and remote wakeup
  • Support detection of USB reset, suspend and resume signaling
  • Support high-speed identification and detection as defined by USB 2.0 Specification
  • Support high-speed host disconnection detection

• Compliant with IEEE 802.3 specifications
• Support for IEEE 1588-2002 and IEEE 1588-2008 standards including:
  • IEEE 802.3-az for Energy Efficient Ethernet (EEE)
  • IEEE 802.3x flow control automatic transmission of zero-quanta pause frame on flow control input de-assertion.
  • IEEE 802.1Q VLAN tag detection for reception frames
• Support data transfer rates of 10/100/1,000 Mbps auto-negotiation using the following PHY models
  • YT8521DH/DC
  • YT8531DH/DC
• Support data transfer rates of 1,000 Mbps only using all other PHY models
• Multiple TCP/IP offload functions supported

Power Management Module (PMT) with remote wake-up frame and magic packet frame processing options

• RGMII interface to communicate with an external gigabit PHY.

• Support up to 2 SDIO 3.0 interfaces
• Compatible with SDIO3.0 protocol
• Support 4-bit data width

• Support 2 CAN2.0B interfaces
• Support CAN2.0B specification
• Data rates up to 1 Mbps
• Programmable baud rate pre-scaler (1 to 1/256)
• Separate clock domains for host interface and CAN protocol machine
• Configurable receive buffer and Two Transmit Buffers
• Independent and programmable internal 29-bit acceptance filters
• Time-stamping:
  • ISO 11898-4 Time-Triggered CAN with partial hardware support
  • CiA 603 time-stamping

• Support short frame sync, long frame sync and multi-slot mode
• Multi slot supported, and up to 16 slots
• Slot width including 8-bit, 16-bit, 20-bit, and 32-bit
• Sample rate up to 192 KHz, and data transferred with system DMA
• Support master and slave mode, and software configurable

• 2 × I2S transmitters, and 1 for HDMI audio
• 1 × I2S receiver to receive data from internal PDM or from external audio I2S ADC
• Support programmable sample rate: 16 K/44.1 K/48 K/96 K/192 KHz
• Data resolution support 16-bit (programmable)
• Programmable FIFO depth up 64 for each channel
• Support to select between master and slave modes, software configurable

• Provide 2 sets of SPDIF, 1 for RX and 1 for TX mode
• Support sample rates from 16 KHz up to 192 KHz.
• Support PCM format with a resolution of 16-bit per sample

• Support up to 4 PDM channels (MICs) with the same sample rate
• Pulse Density Modulation interface for digital MIC interface
• 128 oversample ratio, output sample clock: 62.5 KHz to 6.144MHz (48KHz)
• Combine clock source for each 2 channels
• I2S interface connect with I2S RX internally in slave mode

• AES
  • Support encryption and decryption
  • Support 128-bit/192-bit/256-bit of key size
  • Support ECB/CBC/CFB/OFB/CTR/CCM/GCM operation modes
  • Support SCA countermeasure
  • Support DMA mode
• DES/3DES
  • Support standard DES with 64(56)-bit of key size
  • Support 3-DES with 128(112)-bit or 192(168)-bit of key size
  • Support ECB/CBC/CFB/OFB operation modes
  • Support SCA countermeasure
  • Support DMA mode
• HASH
  • Support SHA0/1
  • Support SH224/256/384/512
  • Support HMAC_SHA0/HMC_SHA1
  • Support HMAC_SHA224/256/384/512
  • Support DMA mode
• PKA
  • Support modular addition from 32-bit to 2048-bit with granularity of 32-bit
  • Support modular subtraction from 32-bit to 2048-bit with granularity of 32-bit
  • Support modular multiplication from 32-bit to 2048-bit with granularity of 32-bit
  • Support modular exponentiation from 32-bit to 2048-bit with granularity of 32-bit
  • Support Montgomery modular multiplication from 32-bit to 2048-bit bits with granularity of 32-bit
  • Support up to 512-bit of point addition/double under prime field
  • Support SCA countermeasure
• ECC for 512-bit

• Ring-oscillator based entropy source
• Support LFSR based digital post process
• Support self re-seeding
• 256-bit random number generation

• VDD and VDD2 power supply: 0.9 V VDD, 1.8 V VDD2 for reading and programming
• Memory organization 512 x 32-bit (2 KB)
• Bit program operation
• Data retention: >10 Years
• Access time: 50 ns (max)
• Bit cell program time: 10 us (min)

• Support 7 SPI interfaces
• Support serial-master and serial-slave mode, software-configurable
• Separate data input and output bit
• Provide configurable FIFO with size up to 8 × 16-bit for both TX and RX channel
• Support DMA access for TX and RX FIFO

• Support 6 UART interfaces
• Support 4-wire mode (HW flow control with CTS/RTS)
• Separate up to 256-Byte of TX and 384-Byte of RX FIFOs
• Programmable FIFO disabling for 1-Byte depth
• Programmable baud rate generator supports up to 3 Mbps
• Support DMA access for TX and RX channel
• Standard asynchronous communication bits (for start, stop, and parity).
• Independent masking of transmit FIFO, receive FIFO, receive timeout, modem status, and error condition interrupts.
• False start bit detection
• Line break generation and detection
• Programmable hardware flow control
• Fully-programmable serial interface characteristics

• Support 7 I2C interfaces
• Compatible with Philips I2C standard
• Support multi-master operation
• Provide software-programmable clock frequency
• Support clock Stretching and “Wait” state generation
• Software programmable acknowledge bit
• Interrupt or bit-polling driven byte-by-byte data-transfers
• Arbitration lost interrupt, with automatic transfer cancellation
• Start/Stop/Repeated Start/Acknowledge generation
• Start/Stop/Repeated Start detection
• Bus busy detection
• Support 7-bit and 10-bit addressing modes
• Operates from a wide range of input clock frequencies
• Support 100 KHz/400 KHz/1 MHz modes

• 4 timers for system application
• Maskable interrupt
• Register lock function
• Programmable output frequency

• 32-bit down counter
• Non-Maskable Interrupt (NMI) or WDOG reset
• Optional automatic WDOG reset if NMI handler fails to update the Watchdog register
• Maskable Watchdog freeze by a user program
• Configurable clock source

• ±3 ℃ untrimmed accuracy (-40 ℃ to 100 ℃)
• ±1.0 ℃ trimmed accuracy (0 ℃ to 70 ℃)
• ±1.25 ℃ trimmed accuracy (-40 ℃ to 125 ℃)
• Calibration sequence requires no knowledge of die temperature
• Digital interface, 12-bit resolution

• Dual power supply: 1.8 V (analog)/0.9 V(digital) allows for excellent supply noise rejection
• Reference clock frequency range from 5 MHz to 500 MHz
• PFD frequency range 5 MHz to 100 MHz
• VCO frequency range from 1 GHz to 3 GHz
• Low jitter
• Lock detector to indicate frequency locked state

• Less DFF/Power
• Provide calendar register with year, month, day, hour, minute, second
• Support leap year judgment
• The range is 2001/01/01/00/00/00 to 2099/12/31/23/59/59
• Support DayClk/HourClk/MinClk, in BCD code
• Implement timer interrupt function through register
• The clock frequency of the input crystal is 32768 Hz
• There are 32 reference calibration clocks chosen by software with reference clock coming from GPIO
• Hardware calibration interval is 1D/1H only works when reference calibration clock connected
• Support software calibration

• 2 INTCs that support a total 4 sets of 32-bit source interrupt input
• Support separate interrupt with a programmable type (level, edge) and polarity
• Software interrupt control

• Support 8 PWM interfaces
• 32-bit counter/timer facility
• Single-run or continuous run of PTC counter
• Programmable PWM mode
• System clock and external clock sources for timer functionality
• HI/LO Reference and Capture registers
• 3-state control for PWM output driver
• PWM/Timer/Counter functionalities can cause an interrupt to the CPU

• Support 3 general-purpose clock outputs to GPIO pins.
• Output clock up to 50 MHz

• Send messages or signals between RISC-V cores
• Support 4 mailbox elements, and each mailbox element includes 1 data word, 1 command register, and 1 flag bit for interrupt
• Provide 32 registers for software to use to indicate whether the mailbox is occupied

• Support up to 64 GPIOs
• Individually programmable input/output pins, default to output at reset.
• Each GPIO has a dedicated control signal
• Support separate interrupt with a programmable type (level, edge) and polarity
• All pins with MUX with function pins