Pin and I/O Related Specification
Signal Description
The following table displays the system signals of JH-7110, including Pull-Up (PU) and
Pull-Down (PD) settings.
Note: The maximum current that a GPIO pin
can afford is 3 A.
| Signal Name | Description | PU | PD |
|---|---|---|---|
| TESTEN | Test Enable Signal Negative | Tied to 0, not configurable | Tied to 1, not configurable |
| RGPIO0 | RGPIO0 | 0 | 0 |
| RGPIO1 | RGPIO1 | 0 | 0 |
| RGPIO2 | RGPIO2 | 0 | 0 |
| RGPIO3 | RGPIO3 | 0 | 1 |
| SD_SEL18 | SD Select 18 | 0 | 1 |
| QSPI_SEL18 | QSPI Select 18 | 1 | 0 |
| GPIO0 | GPIO0 | 0 | 0 |
| GPIO1 | GPIO1 | 1 | 0 |
| GPIO2 | GPIO2 | 0 | 0 |
| GPIO3 | GPIO3 | 0 | 0 |
| GPIO4 | GPIO4 | 1 | 0 |
| GPIO5 | GPIO5 | 1 | 0 |
| GPIO6 | GPIO6 | 1 | 0 |
| GPIO7 | GPIO7 | 0 | 0 |
| GPIO8 | GPIO8 | 0 | 0 |
| GPIO9 | GPIO9 | 1 | 0 |
| GPIO10 | GPIO10 | 0 | 0 |
| GPIO11 | GPIO11 | 0 | 0 |
| GPIO12 | GPIO12 | 1 | 0 |
| GPIO13 | GPIO13 | 1 | 0 |
| GPIO14 | GPIO14 | 0 | 0 |
| GPIO15 | GPIO15 | 0 | 0 |
| GPIO16 | GPIO16 | 0 | 0 |
| GPIO17 | GPIO17 | 0 | 0 |
| GPIO18 | GPIO18 | 1 | 0 |
| GPIO19 | GPIO19 | 1 | 0 |
| GPIO20 | GPIO20 | 0 | 0 |
| GPIO21 | GPIO21 | 0 | 0 |
| GPIO22 | GPIO22 | 0 | 0 |
| GPIO23 | GPIO23 | 0 | 0 |
| GPIO24 | GPIO24 | 0 | 0 |
| GPIO25 | GPIO25 | 0 | 0 |
| GPIO26 | GPIO26 | 0 | 0 |
| GPIO27 | GPIO27 | 0 | 0 |
| GPIO28 | GPIO28 | 0 | 0 |
| GPIO29 | GPIO29 | 0 | 0 |
| GPIO30 | GPIO30 | 0 | 0 |
| GPIO31 | GPIO31 | 0 | 0 |
| GPIO32 | GPIO32 | 0 | 0 |
| GPIO33 | GPIO33 | 0 | 0 |
| GPIO34 | GPIO34 | 0 | 1 |
| GPIO35 | GPIO35 | 0 | 0 |
| GPIO36 | GPIO36 | 1 | 0 |
| GPIO37 | GPIO37 | 1 | 0 |
| GPIO38 | GPIO38 | 1 | 0 |
| GPIO39 | GPIO39 | 1 | 0 |
| GPIO40 | GPIO40 | 1 | 0 |
| GPIO41 | GPIO41 | 1 | 0 |
| GPIO42 | GPIO42 | 1 | 0 |
| GPIO43 | GPIO43 | 1 | 0 |
| GPIO44 | GPIO44 | 1 | 0 |
| GPIO45 | GPIO45 | 1 | 0 |
| GPIO46 | GPIO46 | 1 | 0 |
| GPIO47 | GPIO47 | 1 | 0 |
| GPIO48 | GPIO48 | 1 | 0 |
| GPIO49 | GPIO49 | 0 | 0 |
| GPIO50 | GPIO50 | 0 | 0 |
| GPIO51 | GPIO51 | 0 | 0 |
| GPIO52 | GPIO52 | 1 | 0 |
| GPIO53 | GPIO53 | 0 | 0 |
| GPIO54 | GPIO54 | 0 | 0 |
| GPIO55 | GPIO55 | 0 | 0 |
| GPIO56 | GPIO56 | 1 | 0 |
| GPIO57 | GPIO57 | 0 | 0 |
| GPIO58 | GPIO58 | 0 | 0 |
| GPIO59 | GPIO59 | 0 | 0 |
| GPIO60 | GPIO60 | 1 | 0 |
| GPIO61 | GPIO61 | 0 | 0 |
| GPIO62 | GPIO62 | 0 | 0 |
| GPIO63 | GPIO63 | 0 | 0 |
| RSTN | Reset Negative | Tied to 1 | Tied to 0 |
| RTC_XIN | RTC Input Signal | NONE | NONE |
| RTC_XOUT | RTC Output Signal | NONE | NONE |
| OSC_XIN | Oscillator Input Signal | NONE | NONE |
| OSC_XOUT | Oscillator Output Signal | NONE | NONE |
| SD0_CLK | SD0 Clock Signal | 0 | 0 |
| SD0_CMD | SD0 Command Signal | 0 | 0 |
| SD0_DATA0 | SD0 DATA Lane 0 | 1 | 0 |
| SD0_DATA1 | SD0 DATA Lane 1 | 0 | 0 |
| SD0_DATA2 | SD0 DATA Lane 2 | 0 | 0 |
| SD0_DATA3 | SD0 DATA Lane 3 | 1 | 0 |
| SD0_DATA4 | SD0 DATA Lane 4 | 1 | 0 |
| SD0_DATA5 | SD0 DATA Lane 5 | 0 | 0 |
| SD0_DATA6 | SD0 DATA Lane 6 | 0 | 0 |
| SD0_DATA7 | SD0 DATA Lane 7 | 0 | 0 |
| SD0_STRB | SD0 STR8 | 0 | 0 |
| GMAC1_MDC | GMAC1 Management Device Clock | NONE | NONE |
| GMAC1_MDIO | GMAC1 Management Data Input and Output | NONE | NONE |
| GMAC1_RXD0 | GMAC1 Input Data Lane 0 | NONE | NONE |
| GMAC1_RXD1 | GMAC1 Input Data Lane 1 | NONE | NONE |
| GMAC1_RXD2 | GMAC1 Input Data Lane 2 | NONE | NONE |
| GMAC1_RXD3 | GMAC1 Input Data Lane 3 | NONE | NONE |
| GMAC1_RXDV | GMAC1 Input Collision and Data Valid | NONE | NONE |
| GMAC1_RXC | GMAC1 Input Clock | NONE | NONE |
| GMAC1_TXD0 | GMAC1 Output Data Lane 0 | NONE | NONE |
| GMAC1_TXD1 | GMAC1 Output Data Lane 1 | NONE | NONE |
| GMAC1_TXD2 | GMAC1 Output Data Lane 2 | NONE | NONE |
| GMAC1_TXD3 | GMAC1 Output Data Lane 3 | NONE | NONE |
| GMAC1_TXEN | GMAC1 Output Enable | NONE | NONE |
| GMAC1_TXC | GMAC1 Output Clock | NONE | NONE |
| GMAC0_MDC | GMAC0 Management Device Clock | NONE | NONE |
| GMAC0_MDIO | GMAC0 Management Data Input and Output | NONE | NONE |
| GMAC0_RXD0 | GMAC0 Input Data Lane 0 | NONE | NONE |
| GMAC0_RXD1 | GMAC0 Input Data Lane 1 | NONE | NONE |
| GMAC0_RXD2 | GMAC0 Input Data Lane 2 | NONE | NONE |
| GMAC0_RXD3 | GMAC0 Input Data Lane 3 | NONE | NONE |
| GMAC0_RXDV | GMAC0 Input Collision and Data Valid | NONE | NONE |
| GMAC0_RXC | GMAC0 Input Clock | NONE | NONE |
| GMAC0_TXD0 | GMAC0 Output Data Lane 0 | NONE | NONE |
| GMAC0_TXD1 | GMAC0 Output Data Lane 1 | NONE | NONE |
| GMAC0_TXD2 | GMAC0 Output Data Lane 2 | NONE | NONE |
| GMAC0_TXD3 | GMAC0 Output Data Lane 3 | NONE | NONE |
| GMAC0_TXEN | GMAC0 Output Enable | NONE | NONE |
| GMAC0_TXC | GMAC0 Output Clock | NONE | NONE |
| QSPI_SCLK | QSPI_SCLK | 0 | 0 |
| QSPI_CSn0 | QSPI Chip Select | 1 | 0 |
| QSPI_DATA0 | QSPI Data Lane 0 | 0 | 0 |
| QSPI_DATA1 | QSPI Data Lane 1 | 0 | 0 |
| QSPI_DATA2 | QSPI Data Lane 2 | 0 | 0 |
| QSPI_DATA3 | QSPI Data lane 3 | 0 | 0 |
| OTP_PENVDD2 | OTP_PENVDD2 | NONE | NONE |
| DDR_ACT_N | DDR_ACT_N | NONE | NONE |
| DDR_ADR[13:0] | DDR Address [13:0] | NONE | NONE |
| DDR_ATB0 | DDR_ATB0 | NONE | NONE |
| DDR_ATB1 | DDR_ATB1 | NONE | NONE |
| DDR_BA[1:0] | DDR BANK Address Input [1:0] | NONE | NONE |
| DDR_BG[1:0] | DDR_BG[1:0] | NONE | NONE |
| DDR_CAL | DDR_CAL | NONE | NONE |
| DDR_CAS_N_ADR15 | DDR Column Address Select Address 15 | NONE | NONE |
| DDR_CKE[1:0] | DDR Clock Enable [1:0] | NONE | NONE |
| DDR_CK_N[1:0] | DDR Clock Negative [1:0] | NONE | NONE |
| DDR_CK_P[1:0] | DDR Clock Positive [1:0] | NONE | NONE |
| DDR_CS_N[3:0] | DDR Chip Select Negative [3:0] | NONE | NONE |
| DDR_DM_DBI_N[3:0] | DDR_DM_DBI_N[3:0] | NONE | NONE |
| DDR_DQ[0:31] | DDR Data Communication [0:31] | NONE | NONE |
| DDR_DQS_N[3:0] | DDR Data Communication Select Negative [3:0] | NONE | NONE |
| DDR_DQS_P[3:0] | DDR Data Communication Select Positive [3:0] | NONE | NONE |
| DDR_ERR_N | DDR Error Negative | NONE | NONE |
| DDR_ODT[1:0] | DDR On-Die Termination [1:0] | NONE | NONE |
| DDR_PAR | DDR_PAR | NONE | NONE |
| DDR_PLL_REFOUT_N | DDR PLL Reference Output Negative | NONE | NONE |
| DDR_PLL_REFOUT_P | DDR PLL Reference Output Positive | NONE | NONE |
| DDR_PLL_TESTOUT_N | DDR PLL Test Output Negative | NONE | NONE |
| DDR_PLL_TESTOUT_P | DDR PLL Test Output Positive | NONE | NONE |
| DDR_RAS_N_ADR16 | DDR Row Address Select Negative Address 16 | NONE | NONE |
| DDR_RESET_N | DDR Reset Negative | NONE | NONE |
| DDR_WE_N_ADR14 | DDR Write Enable Negative Address 14 | NONE | NONE |
| HDMITX0_EXTR | HDMI Output 0 Extra | NONE | NONE |
| HDMITX0_TX0N | HDMI Output 0 Negative | NONE | NONE |
| HDMITX0_TX0P | HDMI Output 0 Positive | NONE | NONE |
| HDMITX0_TX1N | HDMI Output 1 Negative | NONE | NONE |
| HDMITX0_TX1P | HDMI Output 1 Positive | NONE | NONE |
| HDMITX0_TX2N | HDMI Output 2 Negative | NONE | NONE |
| HDMITX0_TX2P | HDMI Output 2 Positive | NONE | NONE |
| HDMITX0_TX3N | HDMI Output 3 Negative | NONE | NONE |
| HDMITX0_TX3P | HDMI Output 3 Positive | NONE | NONE |
| MIPITX_L0N | MIPI Output Lane 0 Negative | NONE | NONE |
| MIPITX_L0P | MIPI Output Lane 0 Positive | NONE | NONE |
| MIPITX_L1N | MIPI Output Lane 1 Negative | NONE | NONE |
| MIPITX_L1P | MIPI Output Lane 1 Positive | NONE | NONE |
| MIPITX_L2N | MIPI Output Lane 2 Negative | NONE | NONE |
| MIPITX_L2P | MIPI Output Lane 2 Positive | NONE | NONE |
| MIPITX_L3N | MIPI Output Lane 3 Negative | NONE | NONE |
| MIPITX_L3P | MIPI Output Lane 3 Positive | NONE | NONE |
| MIPITX_L4N | MIPI Output Lane 4 Negative | NONE | NONE |
| MIPITX_L4P | MIPI Output Lane 4 Positive | NONE | NONE |
| MIPIRX_DN0 | MIPI Input DN Lane 0 | NONE | NONE |
| MIPIRX_DN1 | MIPI Input DN Lane 1 | NONE | NONE |
| MIPIRX_DN2 | MIPI Input DN Lane 2 | NONE | NONE |
| MIPIRX_DN3 | MIPI Input DN Lane 3 | NONE | NONE |
| MIPIRX_DN4 | MIPI Input DN Lane 4 | NONE | NONE |
| MIPIRX_DN5 | MIPI Input DN Lane 5 | NONE | NONE |
| MIPIRX_DP0 | MIPI Input DP Lane 0 | NONE | NONE |
| MIPIRX_DP1 | MIPI Input DP Lane 1 | NONE | NONE |
| MIPIRX_DP2 | MIPI Input DP Lane 2 | NONE | NONE |
| MIPIRX_DP3 | MIPI Input DP Lane 3 | NONE | NONE |
| MIPIRX_DP4 | MIPI Input DP Lane 4 | NONE | NONE |
| MIPIRX_DP5 | MIPI Input DP Lane 5 | NONE | NONE |
| PCIE0_CKREFN | PCIE0 Clock Reference Negative | NONE | NONE |
| PCIE0_CKREFP | PCIE0 Clock Reference Positive | NONE | NONE |
| PCIE0_RXN | PCIE0 Input Negative | NONE | NONE |
| PCIE0_RXP | PCIE0 Input Positive | NONE | NONE |
| PCIE0_TXN | PCIE0 Output Negative | NONE | NONE |
| PCIE0_TXP | PCIE0 Output Positive | NONE | NONE |
| PCIE1_CKREFN | PCIE1 Clock Reference Negative | NONE | NONE |
| PCIE1_CKREFP | PCIE1 Clock Reference Positive | NONE | NONE |
| PCIE1_RXN | PCIE1 Input Negative | NONE | NONE |
| PCIE1_RXP | PCIE1 Input Positive | NONE | NONE |
| PCIE1_TXN | PCIE1 Output Negative | NONE | NONE |
| PCIE1_TXP | PCIE1 Output Positive | NONE | NONE |
| USB_DM | USB Device Management | NONE | NONE |
| USB_DP | USB DP | NONE | NONE |
| USB_ID | USB ID | NONE | NONE |
| USB_RREF | USB_RREF | NONE | NONE |
| USB_VBUS | USB_VBUS | NONE | NONE |
| ANA18_TEMP_VCAL | Analog 18 Temperature VCAL | NONE | NONE |
| ANA18_TEMP_VSS | Analog 18 Temperature VSS | NONE | NONE |
| ANA18_TEMP_TEST1 | Analog 18 Temperature Test 1 | NONE | NONE |
| ANA18_TEMP_TEST0 | Analog 18 Temperature Test 0 | NONE | NONE |
Ball Map
The following figure provides a general view of the pins and their corresponding signal names, for more detailed information, see Pin List.
In the figure, a letter on the left edge from “A” to “AE” and a number on the top edge from “1” to “25” are used together to locate a pin. For example, A1 = “VSS”, A2 = “QSPI_DATA0”.
Pin Delay
The following table lists the pin delay information for all pins.
Important: Make sure you have considered the factor of
pin delay in your hardware design practice. Calculate the delay in the target of
your design, or your design may not be valid!
| Pin | Pin Name | Pin Delay | |
|---|---|---|---|
| Length (mm) | Delay (ps) | ||
| PMUIO (1.8 V only) | |||
| V1 | RSTN | 8.496 | 51.696 |
| W1 | TESTEN | 7.886 | 47.788 |
| W4 | RGPIO0 | 8.628 | 52.471 |
| W5 | RGPIO1 | 6.725 | 40.215 |
| W2 | RGPIO2 | 7.593 | 45.947 |
| W6 | RGPIO3 | 5.707 | 33.512 |
| C3 | QSPI_SEL18 | 7.449 | 45.165 |
| E6 | SD_SEL18 | 4.336 | 24.966 |
| GPIO (1.8 V/3.3 V) | |||
| A4 | GPIO0 | 7.93 | 47.619 |
| C4 | GPIO1 | 7.854 | 47.673 |
| B4 | GPIO2 | 8.011 | 48.616 |
| C5 | GPIO3 | 7.316 | 44.167 |
| C6 | GPIO4 | 6.719 | 40.341 |
| D6 | GPIO5 | 5.891 | 33.987 |
| D5 | GPIO6 | 6.746 | 40.527 |
| J3 | GPIO7 | 4.378 | 25.22 |
| J1 | GPIO8 | 5.349 | 31.396 |
| H1 | GPIO9 | 5.548 | 32.685 |
| J4 | GPIO10 | 3.67 | 20.842 |
| H2 | GPIO11 | 4.686 | 27.338 |
| H5 | GPIO12 | 3.241 | 17.871 |
| H3 | GPIO13 | 4.188 | 24.119 |
| G4 | GPIO14 | 4.121 | 23.618 |
| G3 | GPIO15 | 4.846 | 28.381 |
| F2 | GPIO16 | 5.456 | 32.142 |
| G1 | GPIO17 | 5.469 | 32.379 |
| F1 | GPIO18 | 6.198 | 36.986 |
| G6 | GPIO19 | 3.307 | 18.431 |
| G5 | GPIO20 | 4.856 | 28.435 |
| W24 | GPIO21 | 5.514 | 30.77 |
| Y21 | GPIO22 | 3.878 | 20.27 |
| Y23 | GPIO23 | 4.783 | 27.698 |
| W22 | GPIO24 | 3.682 | 20.972 |
| W25 | GPIO25 | 5.707 | 33.94 |
| W23 | GPIO26 | 4.52 | 26.269 |
| W21 | GPIO27 | 3.515 | 19.688 |
| V23 | GPIO28 | 4.367 | 25.228 |
| W19 | GPIO29 | 2.377 | 12.518 |
| Y20 | GPIO30 | 3.614 | 20.45 |
| W20 | GPIO31 | 2.933 | 16.07 |
| V21 | GPIO32 | 3.322 | 18.539 |
| U22 | GPIO33 | 3.176 | 17.641 |
| U21 | GPIO34 | 2.959 | 16.164 |
| T22 | GPIO35 | 3.085 | 16.968 |
| D21 | GPIO36 | 7.546 | 45.483 |
| D18 | GPIO37 | 5.637 | 32.908 |
| F17 | GPIO38 | 4.047 | 23.272 |
| C19 | GPIO39 | 6.453 | 37.013 |
| F18 | GPIO40 | 4.904 | 28.738 |
| B19 | GPIO41 | 6.164 | 36.188 |
| B20 | GPIO42 | 6.716 | 40.21 |
| E21 | GPIO43 | 6.797 | 40.63 |
| F22 | GPIO44 | 7.777 | 46.706 |
| C17 | GPIO45 | 5.654 | 33.384 |
| E18 | GPIO46 | 5.411 | 31.884 |
| F14 | GPIO47 | 3.046 | 16.781 |
| E16 | GPIO48 | 4.136 | 23.561 |
| A17 | GPIO49 | 6.418 | 37.548 |
| D15 | GPIO50 | 4.236 | 24.267 |
| A19 | GPIO51 | 6.44 | 38.243 |
| B18 | GPIO52 | 5.835 | 34.413 |
| A18 | GPIO53 | 6.256 | 36.867 |
| E15 | GPIO54 | 4.59 | 25.789 |
| E19 | GPIO55 | 5.865 | 34.707 |
| D16 | GPIO56 | 5.132 | 30.065 |
| F21 | GPIO57 | 7.606 | 45.802 |
| G21 | GPIO58 | 6.029 | 35.567 |
| C21 | GPIO59 | 7.431 | 44.784 |
| F19 | GPIO60 | 4.167 | 23.967 |
| F20 | GPIO61 | 5.471 | 31.926 |
| D17 | GPIO62 | 4.177 | 23.474 |
| D20 | GPIO63 | 7.114 | 42.528 |
| QSPI (1.8 V/3.3 V) | |||
| B3 | QSPI_CSN0 | 7.893 | 47.992 |
| A2 | QSPI_DATA0 | 8.351 | 50.84 |
| B2 | QSPI_DATA1 | 8.354 | 50.795 |
| B1 | QSPI_DATA2 | 8.969 | 54.869 |
| C1 | QSPI_DATA3 | 7.899 | 47.964 |
| A3 | QSPI_SCLK | 8.392 | 49.953 |
| D2 | SD0_CLK | 7.684 | 46.662 |
| E4 | SD0_CMD | 6.206 | 37.006 |
| D1 | SD0_DATA0 | 7.598 | 45.868 |
| E1 | SD0_DATA1 | 7.364 | 44.438 |
| E5 | SD0_DATA2 | 4.381 | 25.22 |
| E2 | SD0_DATA3 | 6.795 | 40.918 |
| F3 | SD0_DATA4 | 6.654 | 39.921 |
| F4 | SD0_DATA5 | 5.819 | 34.609 |
| F6 | SD0_DATA6 | 4.716 | 27.564 |
| F5 | SD0_DATA7 | 4.976 | 29.278 |
| F7 | SD0_STRB | 3.129 | 17.414 |
| GMAC0 (AON 1.8 V/2.5 V) | |||
| V2 | GMAC0_MDC | 7.183 | 43.285 |
| V4 | GMAC0_MDIO | 7.015 | 42.191 |
| T2 | GMAC0_RXC | 6.141 | 36.341 |
| U3 | GMAC0_RXD0 | 6.274 | 37.566 |
| R4 | GMAC0_RXD1 | 5.31 | 31.379 |
| U2 | GMAC0_RXD2 | 7.008 | 41.742 |
| V3 | GMAC0_RXD3 | 7.039 | 42.44 |
| T1 | GMAC0_RXDV | 6.69 | 39.723 |
| R2 | GMAC0_TXC | 5.534 | 32.54 |
| U4 | GMAC0_TXD0 | 7.188 | 43.365 |
| R1 | GMAC0_TXD1 | 6.668 | 39.787 |
| P3 | GMAC0_TXD2 | 6.014 | 35.675 |
| T3 | GMAC0_TXD3 | 6.194 | 36.989 |
| P1 | GMAC0_TXEN | 6.197 | 36.613 |
| GMAC1 (1.8 V/2.5 V) | |||
| N1 | GMAC1_MDC | 5.553 | 32.49 |
| M2 | GMAC1_MDIO | 4.677 | 27.191 |
| M3 | GMAC1_RXC | 4.341 | 25.117 |
| L3 | GMAC1_RXD0 | 3.828 | 21.885 |
| M1 | GMAC1_RXD1 | 5.237 | 30.59 |
| N3 | GMAC1_RXD2 | 5.143 | 30.176 |
| N2 | GMAC1_RXD3 | 5.406 | 31.993 |
| K3 | GMAC1_RXDV | 4.193 | 24.057 |
| K2 | GMAC1_TXC | 5.047 | 29.491 |
| L1 | GMAC1_TXD0 | 5.178 | 30.475 |
| M4 | GMAC1_TXD1 | 4.716 | 27.63 |
| K4 | GMAC1_TXD2 | 3.535 | 19.881 |
| K1 | GMAC1_TXD3 | 5.136 | 30.248 |
| K5 | GMAC1_TXEN | 2.751 | 14.807 |
| MIPI RX | |||
| U24 | MIPIRX_DN0 | 5.802 | 33.128 |
| T24 | MIPIRX_DN1 | 5.524 | 32.797 |
| R24 | MIPIRX_DN2 | 5.341 | 30.292 |
| P24 | MIPIRX_DN3 | 5.343 | 31.596 |
| N24 | MIPIRX_DN4 | 5.493 | 31.184 |
| M24 | MIPIRX_DN5 | 5.71 | 34.001 |
| U25 | MIPIRX_DP0 | 5.788 | 33.084 |
| T25 | MIPIRX_DP1 | 5.539 | 32.888 |
| R25 | MIPIRX_DP2 | 5.327 | 30.147 |
| P25 | MIPIRX_DP3 | 5.326 | 31.503 |
| N25 | MIPIRX_DP4 | 5.479 | 31.121 |
| M25 | MIPIRX_DP5 | 5.716 | 32.862 |
| MIPI TX | |||
| G24 | MIPITX_L0N | 6.669 | 38.47 |
| G25 | MIPITX_L0P | 6.657 | 38.385 |
| H24 | MIPITX_L1N | 6.403 | 38.437 |
| H25 | MIPITX_L1P | 6.369 | 38.234 |
| J24 | MIPITX_L2N | 6.261 | 35.922 |
| J25 | MIPITX_L2P | 6.237 | 35.826 |
| K24 | MIPITX_L3N | 6.039 | 36.047 |
| K25 | MIPITX_L3P | 6.047 | 36.17 |
| L24 | MIPITX_L4N | 5.891 | 33.673 |
| L25 | MIPITX_L4P | 5.872 | 33.596 |
| HDMI2.0 TX | |||
| E24 | HDMITX0_EXTR | 6.211 | 37.205 |
| C25 | HDMITX0_TX0N | 8.193 | 49.881 |
| C24 | HDMITX0_TX0P | 8.176 | 49.856 |
| A24 | HDMITX0_TX1N | 8.274 | 48.233 |
| A23 | HDMITX0_TX1P | 8.254 | 48.124 |
| A22 | HDMITX0_TX2N | 7.43 | 45.026 |
| A21 | HDMITX0_TX2P | 7.416 | 44.923 |
| E25 | HDMITX0_TX3N/CKN | 7.172 | 41.445 |
| D25 | HDMITX0_TX3P/CKP | 7.186 | 41.576 |
| PCIE2.0 & USB3.0 | |||
| A10 | PCIE0_CKREFN | 6.529 | 39.089 |
| B10 | PCIE0_CKREFP | 6.526 | 39.16 |
| D11 | PCIE0_RXN | 5.269 | 31.099 |
| C11 | PCIE0_RXP | 5.249 | 30.652 |
| B12 | PCIE0_TXN | 6.654 | 40.019 |
| A12 | PCIE0_TXP | 6.607 | 39.787 |
| A6 | PCIE1_CKREFN | 8.065 | 49.052 |
| B6 | PCIE1_CKREFP | 8.062 | 49.07 |
| D7 | PCIE1_RXN | 5.415 | 31.96 |
| C7 | PCIE1_RXP | 5.401 | 31.984 |
| B8 | PCIE1_TXN | 6.789 | 40.899 |
| A8 | PCIE1_TXP | 6.75 | 40.69 |
| USB2.0 | |||
| A16 | USB_DM | 6.439 | 38.588 |
| A15 | USB_DP | 6.447 | 38.714 |
| A14 | USB_ID | 5.796 | 34.529 |
| C14 | USB_RREF | 5.651 | 33.469 |
| B14 | USB_VBUS18 | 5.81 | 34.392 |
| Temp Sensor | |||
| T21 | ANA18_TEMP_TEST0 | 2.714 | 14.703 |
| R21 | ANA18_TEMP_TEST1 | 2.923 | 15.951 |
| T20 | ANA18_TEMP_VCAL | ||
| R20 | ANA18_TEMP_VSS | ||
| System Clock | |||
| AB1 | OSC_XIN | 8.134 | 49.408 |
| AB2 | OSC_XOUT | 7.864 | 47.685 |
| OTP | |||
| P5 | OTP_PENVDD2 | 2.326 | 11.787 |
| RTC Clock | |||
| Y1 | RTC_XIN | 7.972 | 48.404 |
| Y2 | RTC_XOUT | 8.091 | 48.744 |
| DDR | |||
| AB12 | DDR_ACT_N | 3.668 | 20.7 |
| AB11 | DDR_ADR[0] | 4.891 | 28.586 |
| AC14 | DDR_ADR[1] | 5.039 | 29.428 |
| AC13 | DDR_ADR[2] | 4.521 | 26.17 |
| AD13 | DDR_ADR[3] | 5.438 | 31.998 |
| AE11 | DDR_ADR[4] | 6.189 | 37.05 |
| Y12 | DDR_ADR[5] | 2.949 | 16.173 |
| AA11 | DDR_ADR[6] | 3.306 | 18.373 |
| AA12 | DDR_ADR[7] | 3.382 | 18.801 |
| AC12 | DDR_ADR[8] | 4.508 | 25.888 |
| AE10 | DDR_ADR[9] | 6.73 | 40.416 |
| AD11 | DDR_ADR[10] | 5.196 | 30.491 |
| AC11 | DDR_ADR[11] | 4.697 | 27.161 |
| AC10 | DDR_ADR[12] | 4.988 | 29.246 |
| AA10 | DDR_ADR[13] | 3.888 | 22.19 |
| AD17 | DDR_ATB0 | 5.631 | 33.173 |
| AC16 | DDR_ATB1 | 4.854 | 28.169 |
| AB16 | DDR_BA[0] | 4.412 | 25.456 |
| AA13 | DDR_BA[1] | 3.105 | 17.126 |
| AC15 | DDR_BG[0] | 4.882 | 28.543 |
| Y13 | DDR_BG[1] | 4.242 | 24.483 |
| AE19 | DDR_CAL | 7.062 | 42.511 |
| AB15 | DDR_CAS_N_ADR15 | 4.126 | 23.777 |
| AD15 | DDR_CK_N[0] | 6.764 | 40.646 |
| AE12 | DDR_CK_N[1] | 6.339 | 37.874 |
| AE15 | DDR_CK_P[0] | 6.765 | 40.642 |
| AD12 | DDR_CK_P[1] | 6.337 | 37.92 |
| AA18 | DDR_CKE[0] | 5.702 | 33.81 |
| Y16 | DDR_CKE[1] | 4.237 | 24.463 |
| AC18 | DDR_CS_N[0] | 5.493 | 32.378 |
| AB17 | DDR_CS_N[1] | 4.38 | 25.321 |
| AD18 | DDR_CS_N[2] | 5.898 | 34.875 |
| AA14 | DDR_CS_N[3] | 4.18 | 23.981 |
| AA25 | DDR_DM_DBI_N[0] | 7.602 | 45.995 |
| AE20 | DDR_DM_DBI_N[1] | 6.988 | 41.968 |
| AE6 | DDR_DM_DBI_N[2] | 7.25 | 43.725 |
| AD1 | DDR_DM_DBI_N[3] | 9.002 | 54.835 |
| AB25 | DDR_DQ[0] | 7.533 | 45.563 |
| AC25 | DDR_DQ[1] | 7.483 | 45.233 |
| AB23 | DDR_DQ[2] | 6.544 | 39.104 |
| Y25 | DDR_DQ[3] | 7.273 | 43.875 |
| AC24 | DDR_DQ[4] | 7.957 | 48.285 |
| AD23 | DDR_DQ[5] | 7.048 | 42.503 |
| AA24 | DDR_DQ[6] | 7.68 | 46.493 |
| AA23 | DDR_DQ[7] | 6.299 | 37.554 |
| AD21 | DDR_DQ[8] | 6.437 | 38.359 |
| AA21 | DDR_DQ[9] | 5.74 | 34.144 |
| AC22 | DDR_DQ[10] | 6.743 | 40.499 |
| AB21 | DDR_DQ[11] | 7.476 | 45.172 |
| AB20 | DDR_DQ[12] | 5.962 | 35.527 |
| AA22 | DDR_DQ[13] | 6.222 | 37.214 |
| AD20 | DDR_DQ[14] | 6.245 | 37.36 |
| AC20 | DDR_DQ[15] | 6.046 | 36.068 |
| AE9 | DDR_DQ[16] | 6.488 | 38.961 |
| AD9 | DDR_DQ[17] | 5.986 | 35.586 |
| AC9 | DDR_DQ[18] | 5.001 | 29.342 |
| AD8 | DDR_DQ[19] | 6.125 | 36.548 |
| AB9 | DDR_DQ[20] | 5.29 | 31.216 |
| AD6 | DDR_DQ[21] | 6.794 | 40.654 |
| AC7 | DDR_DQ[22] | 5.781 | 34.332 |
| AB8 | DDR_DQ[23] | 6.088 | 36.357 |
| AE3 | DDR_DQ[24] | 7.907 | 47.875 |
| AD3 | DDR_DQ[25] | 8.157 | 49.547 |
| AE5 | DDR_DQ[26] | 7.341 | 44.447 |
| AD2 | DDR_DQ[27] | 8.194 | 49.737 |
| AB4 | DDR_DQ[28] | 7.013 | 42.311 |
| AC3 | DDR_DQ[29] | 7.228 | 43.692 |
| AC5 | DDR_DQ[30] | 5.989 | 35.578 |
| AB5 | DDR_DQ[31] | 5.699 | 33.823 |
| AD24 | DDR_DQS_N[0] | 8.248 | 50.038 |
| AE22 | DDR_DQS_N[1] | 7.655 | 46.377 |
| AD7 | DDR_DQS_N[2] | 7.457 | 45.17 |
| AD4 | DDR_DQS_N[3] | 7.84 | 47.638 |
| AE24 | DDR_DQS_P[0] | 8.253 | 50.212 |
| AD22 | DDR_DQS_P[1] | 7.633 | 46.2 |
| AE7 | DDR_DQS_P[2] | 7.455 | 45.16 |
| AE4 | DDR_DQS_P[3] | 7.83 | 47.587 |
| AD16 | DDR_ERR_N | 5.174 | 30.305 |
| AC19 | DDR_ODT[0] | 5.876 | 34.936 |
| AD19 | DDR_ODT[1] | 6.318 | 37.747 |
| AE14 | DDR_PAR | 5.848 | 34.648 |
| Y15 | DDR_PLL_REFOUT_N | 3.765 | 20.351 |
| AA15 | DDR_PLL_REFOUT_P | 3.767 | 21.432 |
| AA17 | DDR_PLL_TESTOUT_N | 3.75 | 21.23 |
| Y17 | DDR_PLL_TESTOUT_P | 3.744 | 21.192 |
| AB14 | DDR_RAS_N_ADR16 | 3.996 | 22.761 |
| AB18 | DDR_RESET_N | 4.535 | 26.169 |
| AE17 | DDR_WE_N_ADR14 | 6.595 | 39.414 |
GPIO Summary
JH-7110 provides up to 64 GPIO pins with full pin multiplexing capability. This feature allows multiple signals to be mapped to a single physical pin, effectively reducing the total ball count and complexity.
GPIO Pin Default Function
The following table lists all the GPIO pins, where the Function 0 column indicates the default function of an I/O, and Function 2 and Function 3 are provided as examples, indicating that each pin can be flexibly configured to select other available alternate functions as required.
| IOPAD | Function 0 | Function 0 Description | Function 1 | Function 1 Description | Function 2 | Function 2 Description |
|---|---|---|---|---|---|---|
| GPIO0 | SYS_GPIO0 | The test reset input line for JTAG, Negative | ||||
| GPIO1 | SYS_GPIO1 | The test clock input line for JTAG | ||||
| GPIO2 | SYS_GPIO2 | The Test Data Input (TDI) line for JTAG certification | ||||
| GPIO3 | SYS_GPIO3 | The Test Data Output (TDO) line for JTAG certification | ||||
| GPIO4 | SYS_GPIO4 | The Test Mode Selection (TMS) line for JTAG certification | ||||
| GPIO5 | SYS_GPIO5 | The Transmit Data (TXD) line of UART | ||||
| GPIO6 | SYS_GPIO6 | The Receive Data (RXD) line of UART | DVP_CLK | DVP clock | ||
| GPIO7 | SYS_GPIO7 | GPIO7 | LCD_CLK | LCD data output | DVP_VSYNC | DVP vertical synchronization |
| GPIO8 | SYS_GPIO8 | GPIO8 | LCD_VSYNC | LCD vertical synchronization | DVP_HSYNC | DVP horizontal synchronization |
| GPIO9 | SYS_GPIO9 | The test clock input line for JTAG on HIFI4 (Audio DSP) | LCD_HSYNC | LCD horizontal synchronization | DVP_DATA[0] | DVP data lane |
| GPIO10 | SYS_GPIO10 | The Test Data Input (TDI) line for JTAG on HIFI4 (Audio DSP) | LCD_DE | LCD Data Enable (DE) mode | DVP_DATA[1] | DVP data lane |
| GPIO11 | SYS_GPIO11 | The Test Data Output (TDO) line for JTAG on HIFI4 (Audio DSP) | LCD_DATAOUT[0] | LCD data output | DVP_DATA[2] | DVP data lane |
| GPIO12 | SYS_GPIO12 | The Test Mode Selection (TMS) line for JTAG on HIFI4 (Audio DSP) | LCD_DATAOUT[1] | LCD data output | DVP_DATA[3] | DVP data lane |
| GPIO13 | SYS_GPIO13 | The test reset input line for JTAG on HIFI4 (Audio DSP), Negative | LCD_DATAOUT[2] | LCD data output | DVP_DATA[4] | DVP data lane |
| GPIO14 | SYS_GPIO14 | GPIO14 | LCD_DATAOUT[3] | LCD data output | DVP_DATA[5] | DVP data lane |
| GPIO15 | SYS_GPIO15 | GPIO15 | LCD_DATAOUT[4] | LCD data output | DVP_DATA[6] | DVP data lane |
| GPIO16 | SYS_GPIO16 | GPIO16 | LCD_DATAOUT[5] | LCD data output | DVP_DATA[7] | DVP data lane |
| GPIO17 | SYS_GPIO17 | GPIO17 | LCD_DATAOUT[6] | LCD data output | DVP_DATA[8] | DVP data lane |
| GPIO18 | SYS_GPIO18 | The Transmit Data (TXD) line of UART | LCD_DATAOUT[7] | LCD data output | DVP_DATA[9] | DVP data lane |
| GPIO19 | SYS_GPIO19 | The Receive Data (RXD) line of UART | LCD_DATAOUT[8] | LCD data output | DVP_DATA[10] | DVP data lane |
| GPIO20 | SYS_GPIO20 | GPIO20 | LCD_DATAOUT[9] | LCD data output | DVP_DATA[11] | DVP data lane |
| GPIO21 | SYS_GPIO21 | GPIO21 | LCD_DATAOUT[10] | LCD data output | DVP_CLK | DVP clock |
| GPIO22 | SYS_GPIO22 | GPIO22 | LCD_DATAOUT[11] | LCD data output | DVP_VSYNC | DVP vertical synchronization |
| GPIO23 | SYS_GPIO23 | GPIO23 | LCD_DATAOUT[12] | LCD data output | DVP_HSYNC | DVP horizontal synchronization |
| GPIO24 | SYS_GPIO24 | GPIO24 | LCD_DATAOUT[13] | LCD data output | DVP_DATA[0] | DVP data lane |
| GPIO25 | SYS_GPIO25 | GPIO25 | LCD_DATAOUT[14] | LCD data output | DVP_DATA[1] | DVP data lane |
| GPIO26 | SYS_GPIO26 | GPIO26 | LCD_DATAOUT[15] | LCD data output | DVP_DATA[2] | DVP data lane |
| GPIO27 | SYS_GPIO27 | GPIO27 | LCD_DATAOUT[16] | LCD data output | DVP_DATA[3] | DVP data lane |
| GPIO28 | SYS_GPIO28 | GPIO28 | LCD_DATAOUT[17] | LCD data output | DVP_DATA[4] | DVP data lane |
| GPIO29 | SYS_GPIO29 | GPIO29 | LCD_DATAOUT[18] | LCD data output | DVP_DATA[5] | DVP data lane |
| GPIO30 | SYS_GPIO30 | GPIO30 | LCD_DATAOUT[19] | LCD data output | DVP_DATA[6] | DVP data lane |
| GPIO31 | SYS_GPIO31 | GPIO31 | LCD_DATAOUT[20] | LCD data output | DVP_DATA[7] | DVP data lane |
| GPIO32 | SYS_GPIO32 | GPIO32 | LCD_DATAOUT[21] | LCD data output | DVP_DATA[8] | DVP data lane |
| GPIO33 | SYS_GPIO33 | GPIO33 | LCD_DATAOUT[22] | LCD data output | DVP_DATA[9] | DVP data lane |
| GPIO34 | SYS_GPIO34 | GPIO34 | LCD_DATAOUT[23] | LCD data output | DVP_DATA[10] | DVP data lane |
| GPIO35 | SYS_GPIO35 | The reset output line of WDT | DVP_DATA[11] | DVP data lane | ||
| GPIO36 | SYS_GPIO36 | The SCL signal trace of I2C | LCD_CLK | LCD data output | DVP_VSYNC | DVP vertical synchronization |
| GPIO37 | SYS_GPIO37 | The SDA signal trace of I2C | LCD_VSYNC | LCD vertical synchronization | DVP_HSYNC | DVP horizontal synchronization |
| GPIO38 | SYS_GPIO38 | The SCL signal trace of I2C | LCD_HSYNC | LCD horizontal synchronization | DVP_DATA[0] | DVP data lane |
| GPIO39 | SYS_GPIO39 | The SDA signal trace of I2C | LCD_DE | LCD Data Enable (DE) mode | DVP_DATA[1] | DVP data lane |
| GPIO40 | SYS_GPIO40 | The Receive Data (RXD) line of UART | LCD_DATAOUT[0] | LCD data output | DVP_DATA[2] | DVP data lane |
| GPIO41 | SYS_GPIO41 | The Transmit Data (TXD) line of UART | LCD_DATAOUT[1] | LCD data output | DVP_DATA[3] | DVP data lane |
| GPIO42 | SYS_GPIO42 | The modem control Request To Send (RTS) output line of UART, Negative | LCD_DATAOUT[2] | LCD data output | DVP_DATA[4] | DVP data lane |
| GPIO43 | SYS_GPIO43 | The Clear To Send (CTS) modem status of UART, Negative | LCD_DATAOUT[3] | LCD data output | DVP_DATA[5] | DVP data lane |
| GPIO44 | SYS_GPIO44 | The Receive Data (RXD) line of UART | LCD_DATAOUT[4] | LCD data output | DVP_DATA[6] | DVP data lane |
| GPIO45 | SYS_GPIO45 | The Transmit Data (TXD) line of UART | LCD_DATAOUT[5] | LCD data output | DVP_DATA[7] | DVP data lane |
| GPIO46 | SYS_GPIO46 | The modem control Request To Send (RTS) output line of UART, Negative | LCD_DATAOUT[6] | LCD data output | DVP_DATA[8] | DVP data lane |
| GPIO47 | SYS_GPIO47 | The Clear To Send (CTS) modem status of UART, Negative | LCD_DATAOUT[7] | LCD data output | DVP_DATA[9] | DVP data lane |
| GPIO48 | SYS_GPIO48 | The chip select line of SPI, Negative | LCD_DATAOUT[8] | LCD data output | DVP_DATA[10] | DVP data lane |
| GPIO49 | SYS_GPIO49 | The series clock line of SPI | LCD_DATAOUT[9] | LCD data output | DVP_DATA[11] | DVP data lane |
| GPIO50 | SYS_GPIO50 | The Receive Data (RXD) line of SPI | LCD_DATAOUT[10] | LCD data output | ||
| GPIO51 | SYS_GPIO51 | The Transmit Data (TXD) line of SPI | LCD_DATAOUT[11] | LCD data output | ||
| GPIO52 | SYS_GPIO52 | The chip select line of SPI, Negative | LCD_DATAOUT[12] | LCD data output | ||
| GPIO53 | SYS_GPIO53 | The series clock line of SPI | LCD_DATAOUT[13] | LCD data output | ||
| GPIO54 | SYS_GPIO54 | The Receive Data (RXD) line of SPI | LCD_DATAOUT[14] | LCD data output | ||
| GPIO55 | SYS_GPIO55 | The Transmit Data (TXD) line of SPI | LCD_DATAOUT[15] | LCD data output | ||
| GPIO56 | SYS_GPIO56 | The chip select line of SPI, Negative | LCD_DATAOUT[16] | LCD data output | ||
| GPIO57 | SYS_GPIO57 | The series clock line of SPI | LCD_DATAOUT[17] | LCD data output | ||
| GPIO58 | SYS_GPIO58 | The Receive Data (RXD) line of SPI | LCD_DATAOUT[18] | LCD data output | ||
| GPIO59 | SYS_GPIO59 | The Transmit Data (TXD) line of SPI | LCD_DATAOUT[19] | LCD data output | ||
| GPIO60 | SYS_GPIO60 | The chip select line of SPI, Negative | LCD_DATAOUT[20] | LCD data output | ||
| GPIO61 | SYS_GPIO61 | The series clock line of SPI | LCD_DATAOUT[21] | LCD data output | ||
| GPIO62 | SYS_GPIO62 | The Receive Data (RXD) line of SPI | LCD_DATAOUT[22] | LCD data output | ||
| GPIO63 | SYS_GPIO63 | The Transmit Data (TXD) line of SPI | LCD_DATAOUT[23] | LCD data output |
Alternate Peripheral Signals
The following table lists all alternate peripheral signals configurable via multiplexing for each GPIO pin.
| Signal | Description | Direction | Type | Connect |
|---|---|---|---|---|
| hifi4_jtag_tck | The TAP clock signal for JTAG on HIFI4 | Input | GPIO/Clock | sys_iomux |
| hifi4_jtag_tdi | The TAP data input signal for JTAG on HIFI4 | Input | GPIO | sys_iomux |
| hifi4_jtag_tdo | The TAP data output signal for JTAG on HIFI4 | Output | GPIO | sys_iomux |
| hifi4_jtag_tms | The TAP mode switch signal for JTAG on HIFI4 | Input | GPIO | sys_iomux |
| hifi4_jtag_trstn | The TAP reset negative signal for JTAG on HIFI4 | Input | GPIO | sys_iomux |
| cdns_qspi_qspi_csn1 | The chip select negative signal for QSPI | Output | GPIO | sys_iomux |
| uart0_rxd | The data receiving signal for UART0 | Input | GPIO | sys_iomux |
| uart0_txd | The data transmission signal for UART0 | Output | GPIO | sys_iomux |
| uart1_cts_n | The Clear to Send (CTS) negative signal for UART1 | Input | GPIO | sys_iomux |
| uart1_rts_n | The Require to Send (RTS) negative signal for UART1 | Output | GPIO | sys_iomux |
| uart1_rxd | The data receiving signal for UART1 | Input | GPIO | sys_iomux |
| uart1_txd | The data transmission signal for UART1 | Output | GPIO | sys_iomux |
| uart2_cts_n | The Clear to Send (CTS) negative signal for UART2 | Input | GPIO | sys_iomux |
| uart2_rts_n | The Require to Send (RTS) negative signal for UART2 | Output | GPIO | sys_iomux |
| uart2_rxd | The data transmission signal for UART2 | Input | GPIO | sys_iomux |
| uart2_txd | The data transmission signal for UART2 | Output | GPIO | sys_iomux |
| i2c0_i2c_scl | The clock signal for I2C0 | Input/Output | GPIO | sys_iomux |
| i2c0_i2c_sda | The data transmission signal for I2C0 | Input/Output | GPIO | sys_iomux |
| i2c1_i2c_scl | The clock signal for I2C1 | Input/Output | GPIO | sys_iomux |
| i2c1_i2c_sda | The data transmission signal for I2C1 | Input/Output | GPIO | sys_iomux |
| i2c2_i2c_scl | The clock signal for I2C2 | Input/Output | GPIO | sys_iomux |
| i2c2_i2c_sda | The data transmission signal for I2C2 | Input/Output | GPIO | sys_iomux |
| tdm_rx | The receiving signal for TDM | Input | GPIO | sys_iomux |
| tdm_sync | The synchronization signal for TDM | Input/Output | GPIO | sys_iomux |
| tdm_tx | The transmission signal for TDM | Output | GPIO | sys_iomux |
| pdm_4mic_dmic0_din | The data input signal for PDM DMIC0 | Input | GPIO | sys_iomux |
| pdm_4mic_dmic1_din | The data input signal for PDM DMIC1 | Input | GPIO | sys_iomux |
| pdm_4mic_dmic_clk | The clock signal for PDM DMIC | Output | GPIO | sys_iomux |
| uart3_rxd | The data receiving signal for UART3 | Input | GPIO | sys_iomux |
| uart3_txd | The data transmission signal for UART3 | Output | GPIO | sys_iomux |
| uart4_cts_n | The Clear to Send (CTS) negative signal for UART4 | Input | GPIO | sys_iomux |
| uart4_rts_n | The Require to Send (RTS) negative signal for UART4 | Output | GPIO | sys_iomux |
| uart4_rxd | The data receiving signal for UART3 | Input | GPIO | sys_iomux |
| uart4_txd | The data transmission signal for UART4 | Output | GPIO | sys_iomux |
| uart5_cts_n | The Clear to Send (CTS) negative signal for UART5 | Input | GPIO | sys_iomux |
| uart5_rts_n | The Require to Send (RTS) negative signal for UART5 | Output | GPIO | sys_iomux |
| uart5_rxd | The data receiving signal for UART5 | Input | GPIO | sys_iomux |
| uart5_txd | The data transmission signal for UART5 | Output | GPIO | sys_iomux |
| i2c3_scl | The clock signal for I2C3 | Input/Output | GPIO | sys_iomux |
| i2c3_sda | The data transmission signal for I2C3 | Input/Output | GPIO | sys_iomux |
| i2c4_scl | The clock signal for I2C4 | Input/Output | GPIO | sys_iomux |
| i2c4_sda | The data transmission signal for I2C4 | Input/Output | GPIO | sys_iomux |
| i2c5_scl | The clock signal for I2C5 | Input/Output | GPIO | sys_iomux |
| i2c5_sda | The data transmission signal for I2C5 | Input/Output | GPIO | sys_iomux |
| i2c6_scl | The clock signal for I2C6 | Input/Output | GPIO | sys_iomux |
| i2c6_sda | The data transmission signal for I2C6 | Input/Output | GPIO | sys_iomux |
| spi0_ssp_sclk | The clock signal for SPI0 | Input/Output | GPIO | sys_iomux |
| spi0_ssp_csn | The chip select negative signal for SPI0 | Input/Output | GPIO | sys_iomux |
| spi0_ssp_rxd | The data receiving signal for SPI0 | Input | GPIO | sys_iomux |
| spi0_ssp_txd | The data transmission signal for SPI0 | Output | GPIO | sys_iomux |
| spi1_ssp_sclk | The clock signal for SPI1 | Input/Output | GPIO | sys_iomux |
| spi1_ssp_csn | The chip select negative signal for SPI1 | Input/Output | GPIO | sys_iomux |
| spi1_ssp_rxd | The data receiving signal for SPI1 | Input | GPIO | sys_iomux |
| spi1_ssp_txd | The data transmission signal for SPI1 | Output | GPIO | sys_iomux |
| spi2_ssp_sclk | The clock signal for SPI2 | Input/Output | GPIO | sys_iomux |
| spi2_ssp_csn | The chip select negative signal for SPI2 | Input/Output | GPIO | sys_iomux |
| spi2_ssp_rxd | The data receiving signal for SPI2 | Input | GPIO | sys_iomux |
| spi2_ssp_txd | The data transmission signal for SPI2 | Output | GPIO | sys_iomux |
| spi3_ssp_sclk | The clock signal for SPI3 | Input/Output | GPIO | sys_iomux |
| spi3_ssp_csn | The chip select negative signal for SPI3 | Input/Output | GPIO | sys_iomux |
| spi3_ssp_rxd | The data receiving signal for SPI3 | Input | GPIO | sys_iomux |
| spi3_ssp_txd | The data transmission signal for SPI3 | Output | GPIO | sys_iomux |
| spi4_ssp_sclk | The clock signal for SPI4 | Input/Output | GPIO | sys_iomux |
| spi4_ssp_csn | The chip select negative signal for SPI4 | Input/Output | GPIO | sys_iomux |
| spi4_ssp_rxd | The data receiving signal for SPI4 | Input | GPIO | sys_iomux |
| spi4_ssp_txd | The data transmission signal for SPI4 | Output | GPIO | sys_iomux |
| spi5_ssp_sclk | The clock signal for SPI5 | Input/Output | GPIO | sys_iomux |
| spi5_ssp_csn | The chip select negative signal for SPI5 | Input/Output | GPIO | sys_iomux |
| spi5_ssp_rxd | The data receiving signal for SPI5 | Input | GPIO | sys_iomux |
| spi5_ssp_txd | The data transmission signal for SPI5 | Output | GPIO | sys_iomux |
| spi6_ssp_sclk | The clock signal for SPI6 | Input/Output | GPIO | sys_iomux |
| spi6_ssp_csn | The chip select negative signal for SPI6 | Input/Output | GPIO | sys_iomux |
| spi6_ssp_rxd | The data receiving signal for SPI6 | Input | GPIO | sys_iomux |
| spi6_ssp_txd | The data transmission signal for SPI6 | Output | GPIO | sys_iomux |
| pwm[0] | The PWM 0 signal | Output | GPIO | sys_iomux |
| pwm[1] | The PWM 1 signal | Output | GPIO | sys_iomux |
| pwm[2] | The PWM 2 signal | Output | GPIO | sys_iomux |
| pwm[3] | The PWM 3 signal | Output | GPIO | sys_iomux |
| pwm[4] | The PWM 4 signal | Output | GPIO | aon_iomux |
| pwm[5] | The PWM 5 signal | Output | GPIO | aon_iomux |
| pwm[6] | The PWM 6 signal | Output | GPIO | aon_iomux |
| pwm[7] | The PWM 7 signal | Output | GPIO | aon_iomux |
| sys_crg_clk_jtag_tck | The TAP clock signal for JTAG on System CRG clock | Input | GPIO | sys_iomux |
| clkrst_src_bypass_jtag_trstn | The TAP reset negative signal for JTAG on clock reset source bypass | Input | GPIO | sys_iomux |
| jtag_certification_tdi | The TAP data input signal for JTAG on Certification | Input | GPIO | sys_iomux |
| jtag_certification_tdo | The TAP data output signal for JTAG on Certification | Output | GPIO | sys_iomux |
| jtag_certification_tms | The TAP mode switch signal for JTAC on Certification | Input | GPIO | sys_iomux |
| sdio0_back_end_power | The back end power signal for SDIO0 | Output | GPIO | sys_iomux |
| sdio0_card_int_n | The card initialization negative signal for SDIO0 | Input | GPIO | sys_iomux |
| sdio0_card_power_en | The card power supply signal for SDIO0 | Output | GPIO | sys_iomux |
| sdio0_card_write_prt | The card data write signal for SDIO0 | Input | GPIO | sys_iomux |
| sdio0_card_rst_n | The card reset negative signal for SDIO0 | Output | GPIO | sys_iomux |
| sdio0_ccmd_od_pullup_en_n | The pullup enable signal for SDIO0 | Output | GPIO | sys_iomux |
| sdio0_card_detect_n | The card detect negative signal for SDIO0 | Input | GPIO | sys_iomux |
| sdio1_back_end_power | The back end power signal for SDIO1 | Output | GPIO | sys_iomux |
| sdio1_card_int_n | The card initialization negative signal for SDIO1 | Input | GPIO | sys_iomux |
| sdio1_card_power_en | The card power supply signal for SDIO1 | Output | GPIO | sys_iomux |
| sdio1_card_write_prt | The card data write signal for SDIO1 | Input | GPIO | sys_iomux |
| sdio1_clk | The clock signal for SDIO1 | Output | GPIO | sys_iomux |
| sdio1_ccmd | The Command signal of SDIO1 | Input/Output | GPIO | sys_iomux |
| sdio1_cdata[0] | The Data 0 signal of SDIO0 | Input/Output | GPIO | sys_iomux |
| sdio1_cdata[1] | The Data 1 signal of SDIO0 | Input/Output | GPIO | sys_iomux |
| sdio1_cdata[2] | The Data 2 signal of SDIO0 | Input/Output | GPIO | sys_iomux |
| sdio1_cdata[3] | The Data 3 signal of SDIO0 | Input/Output | GPIO | sys_iomux |
| sdio1_cdata[4] | The Data 4 signal of SDIO0 | Input/Output | GPIO | sys_iomux |
| sdio1_cdata[5] | The Data 5 signal of SDIO0 | Input/Output | GPIO | sys_iomux |
| sdio1_cdata[6] | The Data 6 signal of SDIO0 | Input/Output | GPIO | sys_iomux |
| sdio1_cdata[7] | The Data 7 signal of SDIO0 | Input/Output | GPIO | sys_iomux |
| sdio1_card_rst_n | The card reset signal of SDIO1 | Output | GPIO | sys_iomux |
| sdio1_ccmd_od_pullup_en_n | The pullup enable signal for SDIO1 | Output | GPIO | sys_iomux |
| sdio1_data_strobe | The data strobe signal for SDIO1 | Input | GPIO | sys_iomux |
| sdio1_card_detect_n | The card detect signal for SDIO1 | Input | GPIO | sys_iomux |
| sys_crg_ext_mclk | The external main clock signal for System CRG. | Input | GPIO | sys_iomux |
| sys_crg_mclk_out | The main clock output signal for System CRG. | Output | GPIO | sys_iomux |
| sys_crg_clk_gmac_phy | The GMAC PHY signal for System CRG. | Output | GPIO | sys_iomux |
| sys_crg_i2stx_bclk_mst | The bit clock master signal for I2S Transmission | Output | GPIO | sys_iomux |
| sys_crg_i2stx_lrck_mst | The left-right clock (frame clock) master signal for I2S Transmission | Output | GPIO | sys_iomux |
| sys_crg_i2srx_bclk_mst | The bit clock master signal for I2S Receiving | Output | GPIO | sys_iomux |
| sys_crg_i2srx_lrck_mst | The left-right clock (frame clock) master signal for I2S Receiving | Output | GPIO | sys_iomux |
| sys_crg_i2stx_bclk_slv | The bit clock slave signal for I2S Transmission | Input | GPIO | sys_iomux |
| sys_crg_i2stx_lrck_slv | The left-right clock (frame clock) slave signal for I2S Transmission | Input | GPIO | sys_iomux |
| sys_crg_i2srx_bclk_slv | The bit clock slave signal for I2S Receiving | Input | GPIO | sys_iomux |
| sys_crg_i2srx_lrck_slv | The left-right clock (frame clock) slave signal for I2S Receiving | Input | GPIO | sys_iomux |
| sys_crg_tdm_clk_slv | The TDM slave clock signal for System CRG | Input | GPIO | sys_iomux |
| sys_crg_tdm_clk_mst | The TDM master clock signal for System CRG | Output | GPIO | sys_iomux |
| aon_crg_clk_32k_out | The clock 32K output signal for AON CRG | Output | GPIO | aon_iomux |
| i2stx_4ch_sdo0 | The Sound Output 0 for I2S | Output | GPIO | sys_iomux |
| i2stx_4ch_sdo1 | The Sound Output 1 for I2S | Output | GPIO | sys_iomux |
| i2stx_4ch_sdo2 | The Sound Output 2 for I2S | Output | GPIO | sys_iomux |
| i2stx_4ch_sdo3 | The Sound Output 3 for I2S | Output | GPIO | sys_iomux |
| audio_i2srx_ext_sdin0 | The Sound Input 0 for I2S | Input | GPIO | sys_iomux |
| audio_i2srx_ext_sdin1 | The Sound Input 1 for I2S | Input | GPIO | sys_iomux |
| audio_i2srx_ext_sdin2 | The Sound Input 2 for I2S | Input | GPIO | sys_iomux |
| sys_crg_clk_gclk0 | The Global Clock 0 signal for System CRG | Output | GPIO | aon_iomux |
| sys_crg_clk_gclk1 | The Global Clock 1 signal for System CRG | Output | GPIO | aon_iomux |
| sys_crg_clk_gclk2 | The Global Clock 2 signal for System CRG | Output | GPIO | aon_iomux |
| spdif_spdifi | The input signal for SPDIF | Input | GPIO | sys_iomux |
| spdif_spdifo | The output signal for SPDIF | Output | GPIO | sys_iomux |
| vout_hdmi_tx_cec_sda | The serial data CEC signal for HDMI Transmission | Input/Output | GPIO | sys_iomux |
| vout_hdmi_tx_ddc_scl | The serial clock DDC signal for HDMI Transmission | Input/Output | GPIO | sys_iomux |
| vout_hdmi_tx_ddc_sda | The serial data DDC signal for HDMI Transmission | Input/Output | GPIO | sys_iomux |
| vout_hdmi_tx_hdmitx_hpd | The Hot Plug Detect (HPD) signal for HDMI Transmission | Input | GPIO | sys_iomux |
| usb_drive_vbus_io | The VBUS (power supply + cable) input/output signal for USB | Output | GPIO | sys_iomux |
| usb_overcurrent_n_io | The over-current input/output signal for USB | Input | GPIO | sys_iomux |
| u7mc_sft7110_tref | The Timer Reference signal for U74 MC | Output | GPIO | sys_iomux |
| u7mc_sft7110_tdata[0] | The Timer Data 0 signal for U74 MC | Output | GPIO | sys_iomux |
| u7mc_sft7110_tdata[1] | The Timer Data 1 signal for U74 MC | Output | GPIO | sys_iomux |
| u7mc_sft7110_tdata[2] | The Timer Data 2 signal for U74 MC | Output | GPIO | sys_iomux |
| u7mc_sft7110_tdata[3] | The Timer Data 3 signal for U74 MC | Output | GPIO | sys_iomux |
| WAVE511_i_uart_rxsin | The UART receiving input signal for WAVE511 | Input | GPIO | sys_iomux |
| WAVE511_o_uart_txsout | The UART transmission input signal for WAVE511 | Output | GPIO | sys_iomux |
| GPIO_wakeup[3] | The GPIO Wakeup 3 signal | Input | GPIO | aon_iomux |
| GPIO_wakeup[2] | The GPIO Wakeup 2 signal | Input | GPIO | aon_iomux |
| GPIO_wakeup[1] | The GPIO Wakeup 1 signal | Input | GPIO | aon_iomux |
| GPIO_wakeup[0] | The GPIO Wakeup 0 signal | Input | GPIO | aon_iomux |
| can_ctrl0_can_txd | The data transmission signal for CAN Controller 0 | Output | GPIO | sys_iomux |
| can_ctrl0_can_rxd | The data receiving signal for CAN Controller 0 | Input | GPIO | sys_iomux |
| can_ctrl1_can_stby | The standby signal for CAN Controller 1 | Output | GPIO | sys_iomux |
| can_ctrl1_can_txd | The data transmission signal for CAN Controller 1 | Output | GPIO | sys_iomux |
| can_ctrl1_can_rxd | The data receiving signal for CAN Controller 1 | Input | GPIO | sys_iomux |
| can_ctrl1_can_stby | The standby signal for CAN Controller 1 | Output | GPIO | sys_iomux |
| can_ctrl0_tst_sample_point | The test sample point for CAN Controller 0 | Output | GPIO | sys_iomux |
| can_ctrl0_tst_next_bit | The test next point for CAN Controller 0 | Output | GPIO | sys_iomux |
| can_ctrl1_tst_sample_point | The test sample point for CAN Controller 1 | Output | GPIO | sys_iomux |
| can_ctrl1_tst_next_bit | The test next point for CAN Controller 1 | Output | GPIO | sys_iomux |
| dskit_wdt_rstout | The reset output signal for WDT | Output | GPIO | sys_iomux |