PCIe2.0

The PCIe module of JH-7110 has the following features.
  • PCIe2.0 Controller
    • Support 2 PCIe2 .0 x1 interface with 2 PCIe2.0 controller
    • Support link rate of 2.5, 5.0 GT/s per lane, and 32-bit PIPE interface
    • PHY Interface for PCI Express (PIPE), Revision 4.4.1/5.1.1 compliant
    • Designed for Endpoint, Rootport, and dual-mode/shared silicon
    • 128-byte maximum payload size
    • 1 Virtual Channel (VC)
    • Up to 64 Physical Functions (in Endpoint mode)
    • Configurable Receive and Transmit buffer size
    • Advanced Error Reporting (AER) support
    • ECRC generation and check support
    • Integrated Clock Domain Crossing (CDC) to support user-selected frequency for the Bridge
    • Lane reversal support
    • Alternate Routing ID Interpretation (ARI)
    • Legacy PCI Power Management support
    • Clock and power gating support
    • Native Active State Power Management L0s and L1 state support
    • Power Management Event (PME message)
    • MSI (up to 32) and INT message support
    • MSI-X Capability support
    • Latency Tolerance Reporting (LTR)
    • L1 PM Substates with CLKREQ
    • SR-IOV support with up to 512 virtual functions
    • Address Translation Service, including Page Request interface
    • Process Address Space ID (PASID)
    • VPD Capability support
    • TLP Processing Hints
  • PCIe2.0 PHY
    • Compatible with PCIe/USB3/SATA base Specification
    • Fully compatible with the PIPE3.1 interface specification
    • Data rate configurable to 1.5G/2.5G/3G/5G/6G for different application
    • Support 16-bit or 32-bit parallel interface when encode/decode enabled
    • Support 20-bit parallel interface when encode/decode bypassed
    • Support flexible reference clock frequency
    • Support 100 MHz differential reference clock input or output (optional with SSC) in PCIe Mode
    • Support Spread-Spectrum clock (SSC) generation and receiving from -5000ppm to 0ppm
    • Support programmable transmit amplitude and De-emphasis
    • Support TX detect RX function in PCIe and USB3.0 Mode
    • Support Beacon signal generation and detection in PCIe Mode
    • Support Low-Frequency Periodic Signaling (LFPS) generation and detection in USB3.0 Mode
    • Support COMWAKE, COMINIT, and COMRESET (OOB) generation and detection in SATA Mode
    • Support L1 sub-state power management
    • Support RX low latency mode in SATA operation mode
    • Support Loopback BERT and Multiple Pattern BIST Mode