USB

The USB module of JH-7110 provides the following features.
  • 1 × USB2.0/3.0 controller (port)
    • USB Interface:
      • Compliant with USB 3.0 Specification
      • Compliant with xHCI 1.0 Specification
      • SuperSpeed, Hi-Speed, and Full-Speed supported
      • Single USB2.0 Port
      • Single USB3.0 Port (By reusing 1 of the PCIe2.0 lanes)
      • USB 3.0 PIPE interface compliant
      • USB 2.0 UTMI+ interface compliant
      • USB2 L1/L2 Support
      • USB3 U1/U2/U3 Support
    • Application Interface:
      • AXI4 Master Interface with 64-bit data and 32-bit address
      • APB4 Slave interface with 32-bit data and address
    • Dual Mode Operation:
      • HW selectable default mode selection supporting operation without any SW interaction
      • Programmable runtime mode change
      • Host Negotiate Protocol (HNP) support
      • SRP support
      • Provide separate power domains for host and peripheral device logics
    • Host Mode (CDNSXHCI):
      • Support configurable total slots (maximum of 32)
      • 32 endpoints per slot
      • Support 256 Primary Streams
      • MSI Support
      • Root Hub functionality implemented
      • xHCI Dynamic and Static Low Power Management Support
      • xHCI DMA engine with 64-bit @ 125 MHz Full Duplex Data Path
    • Peripheral Mode (USBSS-DEV):
      • Support 8 endpoints for both read and write, and Endpoint #0 supports control transfers
      • Scatter-gather DMA
      • Dynamic data buffering
    • Integrated Protocol Stack
      • Memory integration
      • Clock, reset and power management integration
  • USB2.0 PHY
    • Compliant with USB2.0 and USB1.1 specification
    • Compliant with UTMI Specification Version 1.0
    • Support HS (480 Mbps)/FS (12 Mbps)/LS (1.5 Mbps) modes
    • All required terminations, including 1.5 K Ω pull-up on DP and DM, and 15 K Ω pull-down on DP and DM are internal to the chip
    • 16-bit, 30 MHz or 8-bit, 60 MHz parallel interface for HS/FS
    • Serializing for transmitting data stream and De-serializing for receiving the data stream
    • USB Data Recovery and Clock Recovery on receiving
    • Integrated Bit Stuffing and NRZI encoding for Transmit
    • Integrated Bit Un-Stuffing and NRZI decoding for Receive
    • SYNC and EOP generation on transmit packets and detection on receive packets
    • Support termination calibration with the external resistor
    • Support scan test of digital block
    • Built-in self-test for production testing
    • Support USB suspend state and remote wakeup
    • Support detection of USB reset, suspend and resume signaling
    • Support high-speed identification and detection as defined by USB 2.0 Specification
    • Support high-speed host disconnection detection