Power-Up Sequence

JH-7110 has 3 power supplies, VDD, AVDL, and AVDH. VDD and AVDL are both core power supplies and while separate pins are used for noise isolation purposes.

The recommended power sequence is that from digital core voltage to analog I/O voltage and from low voltage level to high voltage level. This is not considered a constraint, but instead, a guideline, as it could result in the best-case operating scenario, where the leakage currents during power up are kept to a minimum.

The following table and diagram shows the ball name, recommended merge net and power-on sequence of different power groups.

Table 1. Merge Net and Ball Name
Recommended Merge Net	Ball Name
VDD18_AON	VDD18_OSC VDD18_OTP VDD1833_AON VDD1825_GMAC0
VDD09_CPU VDD09_AON	VDD_CPU VDD VDD_RTC
VCC18A_MIPITX VCC18A_MIPIRX VDD18 VDDQ11	AVDD_HDMI VCC18A_MIPITX VCC18A_MIPIRX VCCA18_PLL0..2 VDD18_TEMP VDDA18_TEMP AVDH PCIE0 AVDH PCIE1 VCCA18_USB VDD1825_GMAC1 VDDQ_DDR VDDQCK_DDR
VDD_MIPITX VCCO9A_MIPIRX VDD09	AVDD09_HDMI PVDD_HDMI VDD_MIPITX VCC09A_MIPIRX VDDO9_USB AVDL_PCIE0 AVDL_PCIE1 VDD_PLL0..2 VDD DDR VDDPLL_DDR
VDD18/VDD33	VCCA33_USB VDD1833_GPIO1 VDD1833_GPIO2 VDD1833_GPIO3 VDD1833_GPIO4 VDD1833_SD0 VDD1833_QSPI
PAD_RSTN	PAD_RSTN

Table 2. Power Up Sequence Intervals
Sequence	Interval
T1	1ms
T2	1ms
T3	1ms
T4	1ms
T5	1ms
T6	1ms
T7	64ms