Clock and Reset Specification

Clock Specification

The clock specification of ISP are displayed in the following sheet.

Table 1. ISP Clock Specification
Module Clock Internal Default Freq (MHz) Max Freq (MHz) Typ. Freq (MHz)
dom_isp_syscon clk_isp_2x TRUE 0 614.4 614.4
clk_isp_axi TRUE 0 307.2 307.2
clk_dom4_apb_func TRUE 0 51.2 51.2
dom_isp_crg clk_mipi_rx0_pxl TRUE 0 307.2 204.8
clk_bist_apb TRUE 50 50 50
u3_pclk_mux.func_pclk FALSE 0 51.2 51.2
u3_pclk_mux.bist_pclk FALSE 50 50 50
clk_dom4_apb TRUE 0 51.2 51.2
clk_dvp_inv TRUE 148.5 200 148.5
u0_vin u0_m31dphy.cfgclk_in FALSE 0 153.6 102.4
u0_m31dphy.refclk_in FALSE 0 102.4 51.2
u0_m31dphy.txclkesc_lan0 FALSE 0 40.96 20.48
u0_vin.pclk_free FALSE 0 51.2 51.2
u0_vin.pclk FALSE 0 51.2 51.2
u0_vin.sys_clk FALSE 0 614.4 307.2
u0_vin.pixel_clk_if0 FALSE 0 307.2 204.8
u0_vin.pixel_clk_if1 FALSE 0 307.2 204.8
u0_vin.pixel_clk_if2 FALSE 0 307.2 204.8
u0_vin.pixel_clk_if3 FALSE 0 307.2 204.8
u0_vin.clk_p_axird FALSE 0 307.2 204.8
u0_vin.clk_p_axiwr FALSE 0 307.2 204.8
u0_vin.ACLK FALSE 0 307.2 307.2
u0_ispv2_top_wrapper.clk_isp_axi_in FALSE 0 307.2 307.2
u0_ispv2_top_wrapper.clk_isp_x2 FALSE 0 614.4 614.4
u0_ispv2_top_wrapper u0_ispv2_top_wrapper.clk_isp FALSE 0 307.2 307.2
u0_ispv2_top_wrapper.clk_p FALSE 0 307.2 204.8
u0_ispv2_top_wrapper.clk_c FALSE 0 307.2 204.8
dom_isp_crg u0_crg.pclk TRUE 0 51.2 51.2
dom_isp_syscon u0_syscon.pclk FALSE 0 51.2 51.2
m31dphy_apbcfg u0_m31dphy_apbcfg.pclk FALSE 0 51.2 51.2
axi2apb_bridge u0_axi2apb_bridge.clk_dom4_apb FALSE 0 51.2 51.2
u0_axi2apb_bridge.isp_axi4slv_clk FALSE 0 307.2 307.2

Reset Specification

The reset specification of ISP are displayed in the following sheet.

Table 2. ISP Reset Specification
Module Reset Soft rootReset0
u0_isp u0_ispv2_top_wrapper.rst_p TRUE dom_isp_top.ip_top_reset_n
u0_ispv2_top_wrapper.rst_c TRUE dom_isp_top.ip_top_reset_n
u0_ispv2_top_wrapper.rstn_isp FALSE dom_isp_top.rstn_isp_axi
u0_ispv2_top_wrapper.rstn_isp_axi FALSE dom_isp_top.rstn_isp_axi
u0_m31dphy.hw_rstn TRUE dom_isp_top.ip_top_reset_n
u0_m31dphy.RSTB09_ALWAYS_ON TRUE dom_isp_top.ip_top_reset_n
u0_vin.rst_n_pclk TRUE dom_isp_top.ip_top_reset_n
u0_vin.rst_n_pixel_clk_if0 TRUE dom_isp_top.ip_top_reset_n
u0_vin.rst_n_pixel_clk_if1 TRUE dom_isp_top.ip_top_reset_n
u0_vin.rst_n_pixel_clk_if2 TRUE dom_isp_top.ip_top_reset_n
u0_vin.rst_n_pixel_clk_if3 TRUE dom_isp_top.ip_top_reset_n
u0_vin.rst_n_sys_clk TRUE dom_isp_top.ip_top_reset_n
u0_vin.rst_p_axird TRUE dom_isp_top.ip_top_reset_n
u0_vin.rst_p_axiwr TRUE dom_isp_top.ip_top_reset_n
u0_vin.ARESETn FALSE dom_isp_top.rstn_isp_axi
u0_axi2apb_bridge.ip_top_reset_n FALSE dom_isp_top.ip_top_reset_n
u0_axi2apb_bridge.isp_axi4slv_rstn FALSE dom_isp_top.rstn_isp_axi
u0_crg.func_resetn FALSE dom_isp_top.ip_top_reset_n
u0_crg.presetn FALSE dom_isp_top.ip_top_reset_n
u0_syscon.presetn FALSE dom_isp_top.ip_top_reset_n
u0_m31dphy_apbcfg.presetn FALSE dom_isp_top.ip_top_reset_n

Detailed Information

If you still need more information on the clock and reset specifications of ISP, contact StarFive for the following documentation.
  • ISP subsystem clock and reset specification