Register Description

The PMU of JH-7110 has the following registers.

Hardware Event Turn-On Mask

The following table displays information on the hardware event turn-on mask Control Registers.
Table 1. Hardware Event Turn-On Mask Register Description
Offset Address: 0x4
Default: 0x0
Bit Name Access Default Description
[0] Hard_event_0_on_mask RW 0 RTC event encourage turn-on sequence
  • 1: mask hardware event
  • 0: enable hardware event
[1] Hard_event_1_on_mask RW 0 GMAC event encourage turn-on sequence
  • 1: mask hardware event
  • 0: enable hardware event
[2] Hard_event_2_on_mask RW 0 RFU
  • 1: mask hardware event
  • 0: enable hardware event
[3] Hard_event_3_on_mask RW 0 RGPIO0 event encourage turn-on sequence
  • 1: mask hardware event
  • 0: enable hardware event
[4] Hard_event_4_on_mask RW 0 RGPIO1 event encourage turn-on sequence
  • 1: mask hardware event
  • 0: enable hardware event
[5] Hard_event_5_on_mask RW 0 RGPIO2 event encourage turn-on sequence
  • 1: mask hardware event
  • 0: enable hardware event
[6] Hard_event_6_on_mask RW 0 RGPIO3 event encourage turn-on sequence
  • 1: mask hardware event
  • 0: enable hardware event
[7] Hard_event_7_on_mask RW 0 GPU event
  • 1: mask hardware event
  • 0: enable hardware event
[8:31] Reserved Reserved

Software Turn-On Power Mode

The software turn-on power mode Control Registers are used to configure the power-on mode of the destination via software.

The following table displays information on the software turn-on power mode Control Registers.
Table 2. Software Turn-On Power Mode Register Description
Offset Address: 0xc
Default: 0x003
Bit Name Access Default Description
[0] systop_power_mode RW 0x1 SYSTOP turn-on power mode
[1] cpu_power_mode RW 0x1 CPU turn-on power mode
[2] gpua_power_mode RW 0x0 GPUA turn-on power mode
[3] vdec_power_mode RW 0x0 VDEC turn-on power mode
[4] vout_power_mode RW 0x0 VOUT turn-on power mode
[5] isp_power_mode RW 0x0 ISP turn-on power mode
[6] venc_power_mode RW 0x0 VENC turn-on power mode
[31:7] Reserved Reserved

Software Turn-Off Power Mode

The software turn-on power mode Control Registers are used to configure the power-off mode of the destination via software.

The following table displays information on the software turn-off power mode Control Registers.
Table 3. Software Turn-Off Power Mode Register Description
Offset Address: 0x10
Default: 0x00
Bit Name Access Default Description
[0] systop_power_mode RW 0x0 SYSTOP turn-on power mode
[1] cpu_power_mode RW 0x0 CPU turn-on power mode
[2] gpua_power_mode RW 0x0 GPUA turn-on power mode
[3] vdec_power_mode RW 0x0 VDEC turn-on power mode
[4] vout_power_mode RW 0x0 VOUT turn-on power mode
[5] isp_power_mode RW 0x0 ISP turn-on power mode
[6] venc_power_mode RW 0x0 VENC turn-on power mode
[31:7] Reserved Reserved

Threshold Sequence Timeout

The following table displays information on the threshold sequence timeout Control Registers.
Table 4. Threshold Sequence Timeout Register Description
Offset Address: 0x14
Default: 0xffff
Bit Name Access Default Description
[15:0] timeout_seq_thd RW 0xffff Threshold sequence timeout
[31:16] Reserved Reserved

Powerdomain Cascade 0

The following table displays information on the Powerdomain Cascade 0 Control Registers.
Table 5. Powerdomain Cascade 0 Register Description
Offset Address: 0x18
Default: 0x04008402
Bit Name Access Default Description
[4:0] pd0_off_cas RW 0x2 Power domain 0 turn-off cascade.

The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid.
[9:5] pd0_on_cas RW 0x0 Power domain 0 turn-on cascade.

The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid.
[14:10] pd1_off_cas RW 0x1 Power domain 1 turn-off cascade.

The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid.
[19:15] pd1_on_cas RW 0x1 Power domain 1 turn-on cascade.

The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid.
[24:20] pd2_off_cas RW 0x0 Power domain 2 turn-off cascade.

The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid.
[29:25] pd2_on_cas RW 0x2 Power domain 2 turn-on cascade.

The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid.
[30:31] Reserved Reserved

Powerdomain Cascade 1

The following table displays information on the Powerdomain Cascade 1 Control Registers.
Table 6. Powerdomain Cascade 1 Register Description
Offset Address: 0x1c
Default: 0x04010040
Bit Name Access Default Description
[4:0] pd3_off_cas RW 0x0 Power domain 3 turn-off cascade.

The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid.
[9:5] pd3_on_cas RW 0x2 Power domain 3 turn-on cascade.

The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid.
[14:10] pd4_off_cas RW 0x0 Power domain 4 turn-off cascade.

The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid.
[19:15] pd4_on_cas RW 0x2 Power domain 4 turn-on cascade.

The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid.
[24:20] pd5_off_cas RW 0x0 Power domain 5 turn-off cascade.

The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid.
[29:25] pd5_on_cas RW 0x2 Power domain 5 turn-on cascade.

The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid.
[30:31] Reserved Reserved

Powerdomain Cascade 2

The following table displays information on the Powerdomain Cascade 2 Control Registers.
Table 7. Powerdomain Cascade 2 Register Description
Offset Address: 0x20
Default: 0x04010040
Bit Name Access Default Description
[4:0] pd6_off_cas RW 0x0 Power domain 6 turn-off cascade.

The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid.
[9:5] pd6_on_cas RW 0x2 Power domain 6 turn-on cascade.

The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid.
[14:10] pd7_off_cas RW 0x0 Power domain 7 turn-off cascade.

The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid.
[19:15] pd7_on_cas RW 0x2 Power domain 7 turn-on cascade.

The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid.
[24:20] pd8_off_cas RW 0x0 Power domain 8 turn-off cascade.

The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid.
[29:25] pd8_on_cas RW 0x2 Power domain 8 turn-on cascade.

The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid.
[30:31] Reserved Reserved

Software Encourage

The following table displays information on the Software Encourage Control Registers.
Table 8. Software Encourage Register Description
Offset Address: 0x44
Default: 0x00
Bit Name Access Default Description
[7:0] sw_encourage RW 0x00 Software encouragement
[8:31] Reserved Reserved

TIMER Interrupt Mask Register

The following table displays information on the TIMER Interrupt Mask Register Control Registers.
Table 9. TIMER Interrupt Mask Register Description
Offset Address: 0x48
Default: 0x1ff
Bit Name Access Default Description
[0] seq_done_mask RW 0x1 Mask the sequence complete event.
  • 0: mask
  • 1: Unmask
[1] hw_req_mask RW 0x1 Mask the hardware encouragement request.
  • 0: mask
  • 1: Unmask
[2:3] sw_fail_mask RW 0x1 Mask the software encouragement failure event.
  • 0: mask
  • 1: Unmask
[4:5] hw_fail_mask RW 0x1 Mask the hardware encouragement failure event.
  • 0: mask
  • 1: Unmask
[8:6] pch_fail_mask RW 0x1 Mask the P-channel failure event.
  • 0: mask
  • 1: Unmask
[31:9] Reserved Reserved

P-channel Bypass

The following table displays information on the P-channel Bypass Control Registers.
Table 10. P-channel Bypass Register Description
Offset Address: 0x4c
Default: 0x0
Bit Name Access Default Description
[0] pch_bypass RW 0x0 Bypass p-channel.
  • 0: Enable p-channel
  • 1: Bypass p-channel
[1:31] Reserved Reserved

P-channel PSTATE

The following table displays information on the P-channel Bypass Control Registers.
Table 11. P-channel Bypass Register Description
Offset Address: 0x50
Default: 0Xffff_ffff
Bit Name Access Default Description
[4:0] pch_pstate RW 0x1f P-channel state set
[31:5] Reserved Reserved

P-channel Timeout Threshold

The following table displays information on the P-channel timeout threshold Control Registers.
Table 12. P-channel Timeout Threshold Register Description
Offset Address: 0x54
Default: 0x01
Bit Name Access Default Description
[7:0] lp_timeout RW 0x01 P-channel waiting device acknowledge timeout.
[8:31] Reserved Reserved

LP Cell Control Timeout Threshold

The following table displays information on the LP Cell Control timeout threshold Control Registers.
Table 13. LP Cell Control Timeout Threshold Register Description
Offset Address: 0x58
Default: 0x01
Bit Name Access Default Description
[7:0] lp_timeout RW 0x01 LP Cell Control signal waiting carriers acknowledge timeout.
[8:31] Reserved Reserved

Hardware Turn-On Power Mode

The hardware turn-on power mode Control Registers are used to configure the power-on mode of the destination via hardware.

The following table displays information on the hardware turn-on power mode Control Registers.
Table 14. Hardware Turn-On Power Mode Register Description
Offset Address: 0x5c
Default: 0x003
Bit Name Access Default Description
[0] systop_power_mode RW 0x1 SYSTOP turn-on power mode
[1] cpu_power_mode RW 0x1 CPU turn-on power mode
[2] gpua_power_mode RW 0x0 GPUA turn-on power mode
[3] vdec_power_mode RW 0x0 VDEC turn-on power mode
[4] vout_power_mode RW 0x0 VOUT turn-on power mode
[5] isp_power_mode RW 0x0 ISP turn-on power mode
[6] venc_power_mode RW 0x0 VENC turn-on power mode
[31:7] Reserved Reserved

Current Power Mode

The following table displays information on the current power mode Control Registers.
Table 15. Current Power Mode Register Description
Offset Address: 0x80
Default: 0x103
Bit Name Access Default Description
[0] systop_power_mode RW 0x1 SYSTOP turn-on power mode
[1] cpu_power_mode RW 0x1 CPU turn-on power mode
[2] gpua_power_mode RW 0x0 GPUA turn-on power mode
[3] vdec_power_mode RW 0x0 VDEC turn-on power mode
[4] vout_power_mode RW 0x0 VOUT turn-on power mode
[5] isp_power_mode RW 0x0 ISP turn-on power mode
[6] venc_power_mode RW 0x0 VENC turn-on power mode
[31:7] Reserved Reserved

Current Sequence State

The following table displays information on the current sequence state Control Registers.
Table 16. Current Sequence State Register Description
Offset Address: 0x84
Default: 0x0
Bit Name Access Default Description
[1:0] powermode_cur RO 0x0 Current sequence state.
[2:31] Reserved Reserved

Event Status

The following table displays information on the event status Control Registers.
Table 17. PMU Event Status Register Description
Offset Address: 0x88
Default: 0x0
Bit Name Access Default Description
[0] seq_done_event RO 0x1 Sequence complete.
[1] hw_req_event RO 0x1 Hardware encouragement request.
[2:3] sw_fail_event RO 0x1 Software encouragement failure.
[4:5] hw_fail_event RO 0x1 Hardware encouragement failure.
[8:6] pch_fail_event RO 0x1 P-channel failure.
[31:9] Reserved Reserved

Interrupt Status

The following table displays information on the interrupt status Control Registers.
Table 18. PMU Event Status Register Description
Offset Address: 0x8c
Default: 0x0
Bit Name Access Default Description
[0] seq_done_event RO 0x1 Sequence complete.
[1] hw_req_event RO 0x1 Hardware encouragement request.
[2:3] sw_fail_event RO 0x1 Software encouragement failure.
[4:5] hw_fail_event RO 0x1 Hardware encouragement failure.
[8:6] pch_fail_event RO 0x1 P-channel failure.
[31:9] Reserved Reserved

Hardware Event Record

The following table displays information on the hardware event record Control Registers.
Table 19. Hardware Event Record Register Description
Offset Address: 0x90
Default: 0x0
Bit Name Access Default Description
[7:0] hw_event_crd RO 0x0 Hardware event record.
[8:31] Reserved Reserved

Hardware Event Type Record

The following table displays information on the hardware event type record Control Registers.
Table 20. Hardware Event Type Record Register Description
Offset Address: 0x94
Default: 0x0
Bit Name Access Default Description
[0] encourage_type_crd RO 0x0 Hardware/Software encouragement type record.
  • 0: Software
  • 1: Hardware
[1:31] Reserved Reserved

P-channel PACTIVE status

The following table displays information on the P-channel PACTIVE Control Registers.
Table 21. P-channel PACTIVE Register Description
Offset Address: 0x98
Default: 0x0
Bit Name Access Default Description
[10:0] pch_active RO 0x0 P-channel PACTIVE status
[31:11] Reserved Reserved