Bus Connection
The system bus connection is shown in the following table.
OIC 18x8 | Slave Port ID | ||||||
---|---|---|---|---|---|---|---|
OMC | axi_cfg0 | axi_cfg1 | apb_cfg0 | apb_cfg1 | orbit_cr1 | ||
Master Port ID | CPUSYS | 0 | 0 | X | X | X | X |
CPUPER | X | X | 0 | 0 | 0 | 0 | |
CPUMEM | 0 | X | X | X | X | X | |
GPU | 0 | X | X | X | X | X | |
VDEC | 0 | X | X | X | X | X | |
VENC | 0 | X | X | X | X | X | |
VOUT0 | 0 | X | X | X | X | X | |
VOUT1 | 0 | X | X | X | X | X | |
ISP0 | 0 | X | X | X | X | X | |
STG | 0 | 0 | 0 | 0 | 0 | 0 |
In the STG subsystem, system includes 2 bus inter-connectors. The connection and address
offsets are displayed in the following diagram.