Signal Description
The following table displays the system signals of JH-7110, including Pull-Up (PU) and
Pull-Down (PD) settings.
Note: The maximum current that a GPIO pin
can afford is 3 A.
Note: The following table only
displays the default Pull-Up and Pull-Down settings of a signal. By writing 0 (No)
or 1 (Yes) to the following signals, most of the PU/PD settings are configurable.
"Tied to" means the PU PD settings of the signal are fixed, and not configurable.
| Signal Name | Description | PU | PD |
|---|---|---|---|
| TESTEN | Test Enable Signal Negative | Tied to 0 | Tied to 1 |
| RGPIO0 | RGPIO0 | 0 | 0 |
| RGPIO1 | RGPIO1 | 0 | 0 |
| RGPIO2 | RGPIO2 | 0 | 0 |
| RGPIO3 | RGPIO3 | 0 | 1 |
| SD_SEL18 | SD Select 18 | 0 | 1 |
| QSPI_SEL18 | QSPI Select 18 | 1 | 0 |
| GPIO0 | GPIO0 | 0 | 0 |
| GPIO1 | GPIO1 | 1 | 0 |
| GPIO2 | GPIO2 | 0 | 0 |
| GPIO3 | GPIO3 | 0 | 0 |
| GPIO4 | GPIO4 | 1 | 0 |
| GPIO5 | GPIO5 | 1 | 0 |
| GPIO6 | GPIO6 | 1 | 0 |
| GPIO7 | GPIO7 | 0 | 0 |
| GPIO8 | GPIO8 | 0 | 0 |
| GPIO9 | GPIO9 | 1 | 0 |
| GPIO10 | GPIO10 | 0 | 0 |
| GPIO11 | GPIO11 | 0 | 0 |
| GPIO12 | GPIO12 | 1 | 0 |
| GPIO13 | GPIO13 | 1 | 0 |
| GPIO14 | GPIO14 | 0 | 0 |
| GPIO15 | GPIO15 | 0 | 0 |
| GPIO16 | GPIO16 | 0 | 0 |
| GPIO17 | GPIO17 | 0 | 0 |
| GPIO18 | GPIO18 | 1 | 0 |
| GPIO19 | GPIO19 | 1 | 0 |
| GPIO20 | GPIO20 | 0 | 0 |
| GPIO21 | GPIO21 | 0 | 0 |
| GPIO22 | GPIO22 | 0 | 0 |
| GPIO23 | GPIO23 | 0 | 0 |
| GPIO24 | GPIO24 | 0 | 0 |
| GPIO25 | GPIO25 | 0 | 0 |
| GPIO26 | GPIO26 | 0 | 0 |
| GPIO27 | GPIO27 | 0 | 0 |
| GPIO28 | GPIO28 | 0 | 0 |
| GPIO29 | GPIO29 | 0 | 0 |
| GPIO30 | GPIO30 | 0 | 0 |
| GPIO31 | GPIO31 | 0 | 0 |
| GPIO32 | GPIO32 | 0 | 0 |
| GPIO33 | GPIO33 | 0 | 0 |
| GPIO34 | GPIO34 | 0 | 1 |
| GPIO35 | GPIO35 | 0 | 0 |
| GPIO36 | GPIO36 | 1 | 0 |
| GPIO37 | GPIO37 | 1 | 0 |
| GPIO38 | GPIO38 | 1 | 0 |
| GPIO39 | GPIO39 | 1 | 0 |
| GPIO40 | GPIO40 | 1 | 0 |
| GPIO41 | GPIO41 | 1 | 0 |
| GPIO42 | GPIO42 | 1 | 0 |
| GPIO43 | GPIO43 | 1 | 0 |
| GPIO44 | GPIO44 | 1 | 0 |
| GPIO45 | GPIO45 | 1 | 0 |
| GPIO46 | GPIO46 | 1 | 0 |
| GPIO47 | GPIO47 | 1 | 0 |
| GPIO48 | GPIO48 | 1 | 0 |
| GPIO49 | GPIO49 | 0 | 0 |
| GPIO50 | GPIO50 | 0 | 0 |
| GPIO51 | GPIO51 | 0 | 0 |
| GPIO52 | GPIO52 | 1 | 0 |
| GPIO53 | GPIO53 | 0 | 0 |
| GPIO54 | GPIO54 | 0 | 0 |
| GPIO55 | GPIO55 | 0 | 0 |
| GPIO56 | GPIO56 | 1 | 0 |
| GPIO57 | GPIO57 | 0 | 0 |
| GPIO58 | GPIO58 | 0 | 0 |
| GPIO59 | GPIO59 | 0 | 0 |
| GPIO60 | GPIO60 | 1 | 0 |
| GPIO61 | GPIO61 | 0 | 0 |
| GPIO62 | GPIO62 | 0 | 0 |
| GPIO63 | GPIO63 | 0 | 0 |
| RSTN | Reset Negative | Tied to 1 | Tied to 0 |
| RTC_XIN | RTC Input Signal | NONE | NONE |
| RTC_XOUT | RTC Output Signal | NONE | NONE |
| OSC_XIN | Oscillator Input Signal | NONE | NONE |
| OSC_XOUT | Oscillator Output Signal | NONE | NONE |
| SD0_CLK | SD0 Clock Signal | 0 | 0 |
| SD0_CMD | SD0 Command Signal | 0 | 0 |
| SD0_DATA0 | SD0 DATA Lane 0 | 1 | 0 |
| SD0_DATA1 | SD0 DATA Lane 1 | 0 | 0 |
| SD0_DATA2 | SD0 DATA Lane 2 | 0 | 0 |
| SD0_DATA3 | SD0 DATA Lane 3 | 1 | 0 |
| SD0_DATA4 | SD0 DATA Lane 4 | 1 | 0 |
| SD0_DATA5 | SD0 DATA Lane 5 | 0 | 0 |
| SD0_DATA6 | SD0 DATA Lane 6 | 0 | 0 |
| SD0_DATA7 | SD0 DATA Lane 7 | 0 | 0 |
| SD0_STRB | SD0 STR8 | 0 | 0 |
| GMAC1_MDC | GMAC1 Management Device Clock | NONE | NONE |
| GMAC1_MDIO | GMAC1 Management Data Input and Output | NONE | NONE |
| GMAC1_RXD0 | GMAC1 Input Data Lane 0 | NONE | NONE |
| GMAC1_RXD1 | GMAC1 Input Data Lane 1 | NONE | NONE |
| GMAC1_RXD2 | GMAC1 Input Data Lane 2 | NONE | NONE |
| GMAC1_RXD3 | GMAC1 Input Data Lane 3 | NONE | NONE |
| GMAC1_RXDV | GMAC1 Input Collision and Data Valid | NONE | NONE |
| GMAC1_RXC | GMAC1 Input Clock | NONE | NONE |
| GMAC1_TXD0 | GMAC1 Output Data Lane 0 | NONE | NONE |
| GMAC1_TXD1 | GMAC1 Output Data Lane 1 | NONE | NONE |
| GMAC1_TXD2 | GMAC1 Output Data Lane 2 | NONE | NONE |
| GMAC1_TXD3 | GMAC1 Output Data Lane 3 | NONE | NONE |
| GMAC1_TXEN | GMAC1 Output Enable | NONE | NONE |
| GMAC1_TXC | GMAC1 Output Clock | NONE | NONE |
| GMAC0_MDC | GMAC0 Management Device Clock | NONE | NONE |
| GMAC0_MDIO | GMAC0 Management Data Input and Output | NONE | NONE |
| GMAC0_RXD0 | GMAC0 Input Data Lane 0 | NONE | NONE |
| GMAC0_RXD1 | GMAC0 Input Data Lane 1 | NONE | NONE |
| GMAC0_RXD2 | GMAC0 Input Data Lane 2 | NONE | NONE |
| GMAC0_RXD3 | GMAC0 Input Data Lane 3 | NONE | NONE |
| GMAC0_RXDV | GMAC0 Input Collision and Data Valid | NONE | NONE |
| GMAC0_RXC | GMAC0 Input Clock | NONE | NONE |
| GMAC0_TXD0 | GMAC0 Output Data Lane 0 | NONE | NONE |
| GMAC0_TXD1 | GMAC0 Output Data Lane 1 | NONE | NONE |
| GMAC0_TXD2 | GMAC0 Output Data Lane 2 | NONE | NONE |
| GMAC0_TXD3 | GMAC0 Output Data Lane 3 | NONE | NONE |
| GMAC0_TXEN | GMAC0 Output Enable | NONE | NONE |
| GMAC0_TXC | GMAC0 Output Clock | NONE | NONE |
| QSPI_SCLK | QSPI_SCLK | 0 | 0 |
| QSPI_CSn0 | QSPI Chip Select | 1 | 0 |
| QSPI_DATA0 | QSPI Data Lane 0 | 0 | 0 |
| QSPI_DATA1 | QSPI Data Lane 1 | 0 | 0 |
| QSPI_DATA2 | QSPI Data Lane 2 | 0 | 0 |
| QSPI_DATA3 | QSPI Data lane 3 | 0 | 0 |
| OTP_PENVDD2 | OTP_PENVDD2 | NONE | NONE |
| DDR_ACT_N | DDR_ACT_N | NONE | NONE |
| DDR_ADR[13:0] | DDR Address [13:0] | NONE | NONE |
| DDR_ATB0 | DDR_ATB0 | NONE | NONE |
| DDR_ATB1 | DDR_ATB1 | NONE | NONE |
| DDR_BA[1:0] | DDR BANK Address Input [1:0] | NONE | NONE |
| DDR_BG[1:0] | DDR_BG[1:0] | NONE | NONE |
| DDR_CAL | DDR_CAL | NONE | NONE |
| DDR_CAS_N_ADR15 | DDR Column Address Select Address 15 | NONE | NONE |
| DDR_CKE[1:0] | DDR Clock Enable [1:0] | NONE | NONE |
| DDR_CK_N[1:0] | DDR Clock Negative [1:0] | NONE | NONE |
| DDR_CK_P[1:0] | DDR Clock Positive [1:0] | NONE | NONE |
| DDR_CS_N[3:0] | DDR Chip Select Negative [3:0] | NONE | NONE |
| DDR_DM_DBI_N[3:0] | DDR_DM_DBI_N[3:0] | NONE | NONE |
| DDR_DQ[0:31] | DDR Data Communication [0:31] | NONE | NONE |
| DDR_DQS_N[3:0] | DDR Data Communication Select Negative [3:0] | NONE | NONE |
| DDR_DQS_P[3:0] | DDR Data Communication Select Positive [3:0] | NONE | NONE |
| DDR_ERR_N | DDR Error Negative | NONE | NONE |
| DDR_ODT[1:0] | DDR On-Die Termination [1:0] | NONE | NONE |
| DDR_PAR | DDR_PAR | NONE | NONE |
| DDR_PLL_REFOUT_N | DDR PLL Reference Output Negative | NONE | NONE |
| DDR_PLL_REFOUT_P | DDR PLL Reference Output Positive | NONE | NONE |
| DDR_PLL_TESTOUT_N | DDR PLL Test Output Negative | NONE | NONE |
| DDR_PLL_TESTOUT_P | DDR PLL Test Output Positive | NONE | NONE |
| DDR_RAS_N_ADR16 | DDR Row Address Select Negative Address 16 | NONE | NONE |
| DDR_RESET_N | DDR Reset Negative | NONE | NONE |
| DDR_WE_N_ADR14 | DDR Write Enable Negative Address 14 | NONE | NONE |
| HDMITX0_EXTR | HDMI Output 0 Extra | NONE | NONE |
| HDMITX0_TX0N | HDMI Output 0 Negative | NONE | NONE |
| HDMITX0_TX0P | HDMI Output 0 Positive | NONE | NONE |
| HDMITX0_TX1N | HDMI Output 1 Negative | NONE | NONE |
| HDMITX0_TX1P | HDMI Output 1 Positive | NONE | NONE |
| HDMITX0_TX2N | HDMI Output 2 Negative | NONE | NONE |
| HDMITX0_TX2P | HDMI Output 2 Positive | NONE | NONE |
| HDMITX0_TX3N | HDMI Output 3 Negative | NONE | NONE |
| HDMITX0_TX3P | HDMI Output 3 Positive | NONE | NONE |
| MIPITX_L0N | MIPI Output Lane 0 Negative | NONE | NONE |
| MIPITX_L0P | MIPI Output Lane 0 Positive | NONE | NONE |
| MIPITX_L1N | MIPI Output Lane 1 Negative | NONE | NONE |
| MIPITX_L1P | MIPI Output Lane 1 Positive | NONE | NONE |
| MIPITX_L2N | MIPI Output Lane 2 Negative | NONE | NONE |
| MIPITX_L2P | MIPI Output Lane 2 Positive | NONE | NONE |
| MIPITX_L3N | MIPI Output Lane 3 Negative | NONE | NONE |
| MIPITX_L3P | MIPI Output Lane 3 Positive | NONE | NONE |
| MIPITX_L4N | MIPI Output Lane 4 Negative | NONE | NONE |
| MIPITX_L4P | MIPI Output Lane 4 Positive | NONE | NONE |
| MIPIRX_DN0 | MIPI Input DN Lane 0 | NONE | NONE |
| MIPIRX_DN1 | MIPI Input DN Lane 1 | NONE | NONE |
| MIPIRX_DN2 | MIPI Input DN Lane 2 | NONE | NONE |
| MIPIRX_DN3 | MIPI Input DN Lane 3 | NONE | NONE |
| MIPIRX_DN4 | MIPI Input DN Lane 4 | NONE | NONE |
| MIPIRX_DN5 | MIPI Input DN Lane 5 | NONE | NONE |
| MIPIRX_DP0 | MIPI Input DP Lane 0 | NONE | NONE |
| MIPIRX_DP1 | MIPI Input DP Lane 1 | NONE | NONE |
| MIPIRX_DP2 | MIPI Input DP Lane 2 | NONE | NONE |
| MIPIRX_DP3 | MIPI Input DP Lane 3 | NONE | NONE |
| MIPIRX_DP4 | MIPI Input DP Lane 4 | NONE | NONE |
| MIPIRX_DP5 | MIPI Input DP Lane 5 | NONE | NONE |
| PCIE0_CKREFN | PCIE0 Clock Reference Negative | NONE | NONE |
| PCIE0_CKREFP | PCIE0 Clock Reference Positive | NONE | NONE |
| PCIE0_RXN | PCIE0 Input Negative | NONE | NONE |
| PCIE0_RXP | PCIE0 Input Positive | NONE | NONE |
| PCIE0_TXN | PCIE0 Output Negative | NONE | NONE |
| PCIE0_TXP | PCIE0 Output Positive | NONE | NONE |
| PCIE1_CKREFN | PCIE1 Clock Reference Negative | NONE | NONE |
| PCIE1_CKREFP | PCIE1 Clock Reference Positive | NONE | NONE |
| PCIE1_RXN | PCIE1 Input Negative | NONE | NONE |
| PCIE1_RXP | PCIE1 Input Positive | NONE | NONE |
| PCIE1_TXN | PCIE1 Output Negative | NONE | NONE |
| PCIE1_TXP | PCIE1 Output Positive | NONE | NONE |
| USB_DM | USB Device Management | NONE | NONE |
| USB_DP | USB DP | NONE | NONE |
| USB_ID | USB ID | NONE | NONE |
| USB_RREF | USB_RREF | NONE | NONE |
| USB_VBUS | USB_VBUS | NONE | NONE |
| ANA18_TEMP_VCAL | Analog 18 Temperature VCAL | NONE | NONE |
| ANA18_TEMP_VSS | Analog 18 Temperature VSS | NONE | NONE |
| ANA18_TEMP_TEST1 | Analog 18 Temperature Test 1 | NONE | NONE |
| ANA18_TEMP_TEST0 | Analog 18 Temperature Test 0 | NONE | NONE |