Boot Stages
This topic describes each boot stage in details.
BootROM Stage
Location: 0x2A00_0000 (hard-coded in ROM)
The BootROM is the first code executed after power-on. It performs the following:
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Read AON_RGPIO[1,0] ( 0x1702002C ) to determine the boot source.
Table 1. How BootROM loads boot sources RGPIO1 RGPIO0 Boot Source Behavior 0x0 0x0 Quad SPI NOR flash memory Read SPL from Sector 0 of the QSPI NOR Flash
0x1 0x1 UART0 Enter Xmodem Receiver Mode. You can then import recovery programs in Xmodem mode using serial cable connections. After the files are confirmed with transmission complete, BootROM runs the recovery programs automatically. Note: Thespl_toolutility can modify the backup boot address in the SPL header, enabling alternative recovery configurations. -
Load SPL from the selected medium into SRAM (0x0800_0000).
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Jump to SPL entry point.
SPL Stage
Execution address: SRAM 0x0800_0000
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Initialize DDR: Configure DDR controller and PHY to bring up main memory.
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Load firmware payload: Read fw_payload.img from QSPI Flash offset 0x100000 into DDR at 0x4000_0000.
The fw_payload.img is a single image that bundles OpenSBI (fw_payload.bin) and the full U-Boot binary.
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Jump to the loaded fw_payload.img entry point.
OpenSBI Stage
Execution address: DDR 0x4000_0000
fw_payload.bin output file. It performances
actions including:-
SBI calls: Standard supervisor binary interface for Linux kernel (timer, IPI, console I/O, and so on).
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Privilege mode transition: Switches the hart from M-mode (Machine) to S-mode (Supervisor).
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Payload jump: Transfers execution to U-Boot at DDR 0x4020_0000.
U-Boot
Execution address: DDR 0x4020_0000
Privilege mode: S-mode
U-Boot is the final boot-stage firmware.
It contains basic file system and commonly used peripheral drivers (such as GMAC, UART, QSPI, SDIO, etc.). U-Boot can load the kernel image through ETH (Network), UART, QSPI, SDIO or NVMe (SSD).