Function Description

The following table lists the full multiplexing functions of the IO pins.
Important: JH-7110 GPIO supports full multiplexing. This means that a GPIO pin can be configured to any function listed from Function 1 to Function 2 in the following table.
Important: Function 0 is the default function of an IO. The columns from Function 1 to Function 2 are just used to categorize example functions, you can configure any of the following function to an IO.
Table 1. GPIO Function Description
IOPAD Function 0 Function 0 Description Function 1 Function 1 Description Function 2 Function 2 Description
GPIO0 SYS_GPIO0 The test reset input line for JTAG, Negative
GPIO1 SYS_GPIO1 The test clock input line for JTAG
GPIO2 SYS_GPIO2 The Test Data Input (TDI) line for JTAG certification
GPIO3 SYS_GPIO3 The Test Data Output (TDO) line for JTAG certification
GPIO4 SYS_GPIO4 The Test Mode Selection (TMS) line for JTAG certification
GPIO5 SYS_GPIO5 The Transmit Data (TXD) line of UART
GPIO6 SYS_GPIO6 The Receive Data (RXD) line of UART DVP_CLK DVP clock
GPIO7 SYS_GPIO7 GPIO7 LCD_CLK LCD data output DVP_VSYNC DVP vertical synchronization
GPIO8 SYS_GPIO8 GPIO8 LCD_VSYNC LCD vertical synchronization DVP_HSYNC DVP horizontal synchronization
GPIO9 SYS_GPIO9 The test clock input line for JTAG on HIFI4 (Audio DSP) LCD_HSYNC LCD horizontal synchronization DVP_DATA[0] DVP data lane
GPIO10 SYS_GPIO10 The Test Data Input (TDI) line for JTAG on HIFI4 (Audio DSP) LCD_DE LCD Data Enable (DE) mode DVP_DATA[1] DVP data lane
GPIO11 SYS_GPIO11 The Test Data Output (TDO) line for JTAG on HIFI4 (Audio DSP) LCD_DATAOUT[0] LCD data output DVP_DATA[2] DVP data lane
GPIO12 SYS_GPIO12 The Test Mode Selection (TMS) line for JTAG on HIFI4 (Audio DSP) LCD_DATAOUT[1] LCD data output DVP_DATA[3] DVP data lane
GPIO13 SYS_GPIO13 The test reset input line for JTAG on HIFI4 (Audio DSP), Negative LCD_DATAOUT[2] LCD data output DVP_DATA[4] DVP data lane
GPIO14 SYS_GPIO14 GPIO14 LCD_DATAOUT[3] LCD data output DVP_DATA[5] DVP data lane
GPIO15 SYS_GPIO15 GPIO15 LCD_DATAOUT[4] LCD data output DVP_DATA[6] DVP data lane
GPIO16 SYS_GPIO16 GPIO16 LCD_DATAOUT[5] LCD data output DVP_DATA[7] DVP data lane
GPIO17 SYS_GPIO17 GPIO17 LCD_DATAOUT[6] LCD data output DVP_DATA[8] DVP data lane
GPIO18 SYS_GPIO18 The Transmit Data (TXD) line of UART LCD_DATAOUT[7] LCD data output DVP_DATA[9] DVP data lane
GPIO19 SYS_GPIO19 The Receive Data (RXD) line of UART LCD_DATAOUT[8] LCD data output DVP_DATA[10] DVP data lane
GPIO20 SYS_GPIO20 GPIO20 LCD_DATAOUT[9] LCD data output DVP_DATA[11] DVP data lane
GPIO21 SYS_GPIO21 GPIO21 LCD_DATAOUT[10] LCD data output DVP_CLK DVP clock
GPIO22 SYS_GPIO22 GPIO22 LCD_DATAOUT[11] LCD data output DVP_VSYNC DVP vertical synchronization
GPIO23 SYS_GPIO23 GPIO23 LCD_DATAOUT[12] LCD data output DVP_HSYNC DVP horizontal synchronization
GPIO24 SYS_GPIO24 GPIO24 LCD_DATAOUT[13] LCD data output DVP_DATA[0] DVP data lane
GPIO25 SYS_GPIO25 GPIO25 LCD_DATAOUT[14] LCD data output DVP_DATA[1] DVP data lane
GPIO26 SYS_GPIO26 GPIO26 LCD_DATAOUT[15] LCD data output DVP_DATA[2] DVP data lane
GPIO27 SYS_GPIO27 GPIO27 LCD_DATAOUT[16] LCD data output DVP_DATA[3] DVP data lane
GPIO28 SYS_GPIO28 GPIO28 LCD_DATAOUT[17] LCD data output DVP_DATA[4] DVP data lane
GPIO29 SYS_GPIO29 GPIO29 LCD_DATAOUT[18] LCD data output DVP_DATA[5] DVP data lane
GPIO30 SYS_GPIO30 GPIO30 LCD_DATAOUT[19] LCD data output DVP_DATA[6] DVP data lane
GPIO31 SYS_GPIO31 GPIO31 LCD_DATAOUT[20] LCD data output DVP_DATA[7] DVP data lane
GPIO32 SYS_GPIO32 GPIO32 LCD_DATAOUT[21] LCD data output DVP_DATA[8] DVP data lane
GPIO33 SYS_GPIO33 GPIO33 LCD_DATAOUT[22] LCD data output DVP_DATA[9] DVP data lane
GPIO34 SYS_GPIO34 GPIO34 LCD_DATAOUT[23] LCD data output DVP_DATA[10] DVP data lane
GPIO35 SYS_GPIO35 The reset output line of WDT DVP_DATA[11] DVP data lane
GPIO36 SYS_GPIO36 The SCL signal trace of I2C LCD_CLK LCD data output DVP_VSYNC DVP vertical synchronization
GPIO37 SYS_GPIO37 The SDA signal trace of I2C LCD_VSYNC LCD vertical synchronization DVP_HSYNC DVP horizontal synchronization
GPIO38 SYS_GPIO38 The SCL signal trace of I2C LCD_HSYNC LCD horizontal synchronization DVP_DATA[0] DVP data lane
GPIO39 SYS_GPIO39 The SDA signal trace of I2C LCD_DE LCD Data Enable (DE) mode DVP_DATA[1] DVP data lane
GPIO40 SYS_GPIO40 The Receive Data (RXD) line of UART LCD_DATAOUT[0] LCD data output DVP_DATA[2] DVP data lane
GPIO41 SYS_GPIO41 The Transmit Data (TXD) line of UART LCD_DATAOUT[1] LCD data output DVP_DATA[3] DVP data lane
GPIO42 SYS_GPIO42 The modem control Request To Send (RTS) output line of UART, Negative LCD_DATAOUT[2] LCD data output DVP_DATA[4] DVP data lane
GPIO43 SYS_GPIO43 The Clear To Send (CTS) modem status of UART, Negative LCD_DATAOUT[3] LCD data output DVP_DATA[5] DVP data lane
GPIO44 SYS_GPIO44 The Receive Data (RXD) line of UART LCD_DATAOUT[4] LCD data output DVP_DATA[6] DVP data lane
GPIO45 SYS_GPIO45 The Transmit Data (TXD) line of UART LCD_DATAOUT[5] LCD data output DVP_DATA[7] DVP data lane
GPIO46 SYS_GPIO46 The modem control Request To Send (RTS) output line of UART, Negative LCD_DATAOUT[6] LCD data output DVP_DATA[8] DVP data lane
GPIO47 SYS_GPIO47 The Clear To Send (CTS) modem status of UART, Negative LCD_DATAOUT[7] LCD data output DVP_DATA[9] DVP data lane
GPIO48 SYS_GPIO48 The chip select line of SPI, Negative LCD_DATAOUT[8] LCD data output DVP_DATA[10] DVP data lane
GPIO49 SYS_GPIO49 The series clock line of SPI LCD_DATAOUT[9] LCD data output DVP_DATA[11] DVP data lane
GPIO50 SYS_GPIO50 The Receive Data (RXD) line of SPI LCD_DATAOUT[10] LCD data output
GPIO51 SYS_GPIO51 The Transmit Data (TXD) line of SPI LCD_DATAOUT[11] LCD data output
GPIO52 SYS_GPIO52 The chip select line of SPI, Negative LCD_DATAOUT[12] LCD data output
GPIO53 SYS_GPIO53 The series clock line of SPI LCD_DATAOUT[13] LCD data output
GPIO54 SYS_GPIO54 The Receive Data (RXD) line of SPI LCD_DATAOUT[14] LCD data output
GPIO55 SYS_GPIO55 The Transmit Data (TXD) line of SPI LCD_DATAOUT[15] LCD data output
GPIO56 SYS_GPIO56 The chip select line of SPI, Negative LCD_DATAOUT[16] LCD data output
GPIO57 SYS_GPIO57 The series clock line of SPI LCD_DATAOUT[17] LCD data output
GPIO58 SYS_GPIO58 The Receive Data (RXD) line of SPI LCD_DATAOUT[18] LCD data output
GPIO59 SYS_GPIO59 The Transmit Data (TXD) line of SPI LCD_DATAOUT[19] LCD data output
GPIO60 SYS_GPIO60 The chip select line of SPI, Negative LCD_DATAOUT[20] LCD data output
GPIO61 SYS_GPIO61 The series clock line of SPI LCD_DATAOUT[21] LCD data output
GPIO62 SYS_GPIO62 The Receive Data (RXD) line of SPI LCD_DATAOUT[22] LCD data output
GPIO63 SYS_GPIO63 The Transmit Data (TXD) line of SPI LCD_DATAOUT[23] LCD data output