CRG

The CRG of ISP RGB has the following registers.

clk_dom4_apb_func

Table 1. clk_dom4_apb_func Register Description
Offset Address: 16'h0
Access: RW
Bit Name Default Description
[31] Reserved 0 Reserved
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] clk_divcfg 24'h6 Clock divider coefficient:
  • Max: 15
  • Default: 6
  • Min: 6
  • Typical: 6

clk_mipi_rx0_pxl

Table 2. clk_mipi_rx0_pxl Register Description
Offset Address: 16'h4
Access: RW
Bit Name Default Description
[31] Reserved 0 Reserved
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] clk_divcfg 24'h3 Clock divider coefficient:
  • Max: 8
  • Default: 3
  • Min: 2
  • Typical: 3

clk_dvp_inv

Table 3. clk_dvp_inv Register Description
Offset Address: 16'h8
Access: RW
Bit Name Default Description
[31] Reserved 0 Reserved
[30] clk_polarity 1
  • 1: clock inverter
  • 0: clock buffer
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

clk_u0_m31dphy_cfgclk_in

Table 4. clk_u0_m31dphy_cfgclk_in Register Description
Offset Address: 16'hc
Access: RW
Bit Name Default Description
[31] Reserved 0 Reserved
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] clk_divcfg 24'h6 Clock divider coefficient:
  • Max: 16
  • Default: 6
  • Min: 4
  • Typical: 6

clk_u0_m31dphy_refclk_in

Table 5. clk_u0_m31dphy_refclk_in Register Description
Offset Address: 16'h10
Access: RW
Bit Name Default Description
[31] Reserved 0 Reserved
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] clk_divcfg 24'h12 Clock divider coefficient:
  • Max: 16
  • Default: 12
  • Min: 6
  • Typical: 12

clk_u0_m31dphy_txclkesc_lan0

Table 6. clk_u0_m31dphy_refclk_in Register Description
Offset Address: 16'h14
Access: RW
Bit Name Default Description
[31] Reserved 0 Reserved
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] clk_divcfg 24'h30 Clock divider coefficient:
  • Max: 60
  • Default: 30
  • Min: 15
  • Typical: 30

clk_u0_vin_pclk

Table 7. clk_u0_vin_pclk Register Description
Offset Address: 16'h18
Access: RW
Bit Name Default Description
[31] clk_icg 1
  • 1: Clock enable
  • 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

clk_u0_vin_sys_clk

Table 8. clk_u0_vin_sys_clk Register Description
Offset Address: 16'h1c
Access: RW
Bit Name Default Description
[31] Reserved 0 Reserved
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] clk_divcfg 24'h2 Clock divider coefficient:
  • Max: 8
  • Default: 2
  • Min: 1
  • Typical: 2

clk_u0_vin_pixel_clk_if0

Table 9. clk_u0_vin_pixel_clk_if0 Register Description
Offset Address: 16'h20
Access: RW
Bit Name Default Description
[31] clk_icg 1
  • 1: Clock enable
  • 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

clk_u0_vin_pixel_clk_if1

Table 10. clk_u0_vin_pixel_clk_if1 Register Description
Offset Address: 16'h24
Access: RW
Bit Name Default Description
[31] clk_icg 1
  • 1: Clock enable
  • 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

clk_u0_vin_pixel_clk_if2

Table 11. clk_u0_vin_pixel_clk_if2 Register Description
Offset Address: 16'h28
Access: RW
Bit Name Default Description
[31] clk_icg 1
  • 1: Clock enable
  • 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

clk_u0_vin_pixel_clk_if3

Table 12. clk_u0_vin_pixel_clk_if3 Register Description
Offset Address: 16'h2c
Access: RW
Bit Name Default Description
[31] clk_icg 1
  • 1: Clock enable
  • 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

clk_u0_vin_clk_p_axiwr

Table 13. clk_u0_vin_clk_p_axiwr Register Description
Offset Address: 16'h30
Access: RW
Bit Name Default Description
[31] Reserved 0 Reserved
[30] Reserved 0 Reserved
[24:29] clk_mux_sel 6"h0 Clock multiplexing selector:
  • clk_mipi_rx0_pxl
  • clk_dvp_inv
[0:23] Reserved 0 Reserved

clk_u0_ispv2_top_wrapper_clk_c

Table 14. clk_u0_ispv2_top_wrapper_clk_c Register Description
Offset Address: 16'h34
Access: RW
Bit Name Default Description
[31] clk_icg 1
  • 1: Clock enable
  • 0: Clock disable
[30] Reserved 0 Reserved
[24:29] clk_mux_sel 6"h0 Clock multiplexing selector:
  • clk_mipi_rx0_pxl
  • clk_dvp_inv
[0:23] Reserved 0 Reserved

Software_RESET_assert0_addr_assert_sel

Table 15. Software_RESET_assert0_addr_assert_sel Register Description
Offset Address: 16'h38
Access: RW
Bit Name Default Description
[0] rst_u0_ispv2_top_wrapper_rst_p 1
  • 1: Assert reset
  • 0: De-assert reset
[1] rst_u0_ispv2_top_wrapper_rst_c 1
  • 1: Assert reset
  • 0: De-assert reset
[2] rstn_u0_m31dphy_hw_rstn 1
  • 1: Assert reset
  • 0: De-assert reset
[3] rstn_u0_m31dphy_RSTB09_ALWAYS_ON 1
  • 1: Assert reset
  • 0: De-assert reset
[4] rstn_u0_vin_rst_n_pclk 1
  • 1: Assert reset
  • 0: De-assert reset
[5] rstn_u0_vin_rst_n_pixel_clk_if0 1
  • 1: Assert reset
  • 0: De-assert reset
[6] rstn_u0_vin_rst_n_pixel_clk_if1 1
  • 1: Assert reset
  • 0: De-assert reset
[7] rstn_u0_vin_rst_n_pixel_clk_if2 1
  • 1: Assert reset
  • 0: De-assert reset
[8] rstn_u0_vin_rst_n_pixel_clk_if3 1
  • 1: Assert reset
  • 0: De-assert reset
[9] rstn_u0_vin_rst_n_sys_clk 1
  • 1: Assert reset
  • 0: De-assert reset
[10] rstn_u0_vin_rst_p_axird 1
  • 1: Assert reset
  • 0: De-assert reset
[11] rstn_u0_vin_rst_p_axiwr 1
  • 1: Assert reset
  • 0: De-assert reset
[31:12] Reserved 0 Reserved

ISPCRG_RESET_STATUS

Table 16. ISPCRG_RESET_STATUS Register Description
Offset Address: 16'h3c
Access: RW
Bit Name Default Description
[0] rst_u0_ispv2_top_wrapper_rst_p 1
  • 1: Assert reset
  • 0: De-assert reset
[1] rst_u0_ispv2_top_wrapper_rst_c 1
  • 1: Assert reset
  • 0: De-assert reset
[2] rstn_u0_m31dphy_hw_rstn 1
  • 1: Assert reset
  • 0: De-assert reset
[3] rstn_u0_m31dphy_RSTB09_ALWAYS_ON 1
  • 1: Assert reset
  • 0: De-assert reset
[4] rstn_u0_vin_rst_n_pclk 1
  • 1: Assert reset
  • 0: De-assert reset
[5] rstn_u0_vin_rst_n_pixel_clk_if0 1
  • 1: Assert reset
  • 0: De-assert reset
[6] rstn_u0_vin_rst_n_pixel_clk_if1 1
  • 1: Assert reset
  • 0: De-assert reset
[7] rstn_u0_vin_rst_n_pixel_clk_if2 1
  • 1: Assert reset
  • 0: De-assert reset
[8] rstn_u0_vin_rst_n_pixel_clk_if3 1
  • 1: Assert reset
  • 0: De-assert reset
[9] rstn_u0_vin_rst_n_sys_clk 1
  • 1: Assert reset
  • 0: De-assert reset
[10] rstn_u0_vin_rst_p_axird 1
  • 1: Assert reset
  • 0: De-assert reset
[11] rstn_u0_vin_rst_p_axiwr 1
  • 1: Assert reset
  • 0: De-assert reset
[31:12] Reserved 0 Reserved