SYSCON

The SYSCON of ISP RGB has the following registers.

SYSCONSAIF__SYSCFG_0

Table 1. SYSCONSAIF__SYSCFG_0 Register Description
Offset Address: 0x0
Default: 0x0
Bit Name Access Default Description
[1:0] u0_vin_SCFG_sram_config RW 0x0 Reserved
[2] u0_vin_cnfg_axi_dvp_en RW 0x0

  • 0: Output to AXI is DVP.

  • 1: Output to AXI is MIPI.

[13:3] u0_vin_cnfg_axird_axi_cnt_end RW 0x0 The valid pixel of the AXI image. (1 pixel equals to 64 bit.)
[31:14] Reserved None 0x0 Reserved

SYSCONSAIF__SYSCFG_4

Table 2. SYSCONSAIF__SYSCFG_4 Register Description
Offset Address: 0x4
Access: RW
Bit Name Access Default Description
[0:31] u0_vin_cnfg_axird_end_addr RW 0x0 The start address of the next frame.

SYSCONSAIF__SYSCFG_8

Table 3. SYSCONSAIF__SYSCFG_8 Register Description
Offset Address: 0x8
Default: 0x0
Bit Name Access Default Description
[0] u0_vin_cnfg_axird_intr_clean RW 0x0 Use this bit to clean the AXI output interrupt. Write 1 then write 0 to execute the cleaning.
[1] u0_vin_cnfg_axird_intr_mask RW 0x0 Use this bit to mask the AXI output interrupt.
[13:2] u0_vin_cnfg_axird_line_cnt_end RW 0x0

This bit represents the valid end pixel of the AXI input test image line.

[25:14] u0_vin_cnfg_axird_line_cnt_start RW 0x0

This bit represents the valid start pixel of the AXI input test image line.

[31:26] Reserved None 0x0 Reserved

SYSCONSAIF__SYSCFG_12

Table 4. SYSCONSAIF__SYSCFG_12 Register Description
Offset Address: 0xc
Default: 0x0
Bit Name Access Default Description
[12:0] u0_vin_cnfg_axird_pix_cnt_end RW 0x0

This bit represents the valid end pixel of the AXI input test image line.

[25:13] u0_vin_cnfg_axird_pix_cnt_start RW 0x0

This bit represents the valid start pixel of the AXI input test image line.

[27:26] u0_vin_cnfg_axird_pix_ct RW 0x0

  • 00: 1 64-bit equals to 2 pixels

  • 01: 1 64-bit equals to 4 pixels

  • 10: 1 64-bit equals to 8 pixels
[31:28] Reserved None 0x0 Reserved

SYSCONSAIF__SYSCFG_16

Table 5. SYSCONSAIF__SYSCFG_16 Register Description
Offset Address: 0x10
Default: 0x0
Bit Name Access Default Description
[0:31] u0_vin_cnfg_axird_start_addr RW 0x0 This bit represents the valid start address of the AXI input test image's first line.

SYSCONSAIF__SYSCFG_20

Table 6. SYSCONSAIF__SYSCFG_20 Register Description
Offset Address: 0x14
Default: 0x0
Bit Name Access Default Description
[0:3] u0_vin_cnfg_axiwr0_channel_sel RW 0x0 Select 1 channel output of the 8 MIPI channels
[4] u0_vin_cnfg_axiwr0_en RW 0x0 Set this bit to 1 to enable the image output to AXI.
[31:5] Reserved None 0x0 Reserved

SYSCONSAIF__SYSCFG_24

Table 7. SYSCONSAIF__SYSCFG_24 Register Description
Offset Address: 0x18
Default: 0x0
Bit Name Access Default Description
[0:31] u0_vin_cnfg_axiwr0_end_addr RW 0x0 This bit represents the start address of the next frame.

SYSCONSAIF__SYSCFG_28

Table 8. SYSCONSAIF__SYSCFG_28 Register Description
Offset Address: 0x1c
Default: 0x0
Bit Name Access Default Description
[0] u0_vin_cnfg_axiwr0_intr_clean RW 0x0 Use this bit to clean the AXI output interrupt. Write 1 then write 0 to execute the cleaning.
[1] u0_vin_cnfg_axiwr0_intr_mask RW 0x0 Use this bit to mask the AXI output interrupt.
[12:2] u0_vin_cnfg_axiwr0_pix_cnt_end RW 0x0

This bit represents the valid end pixel of the AXI input test image line.

[14:13] u0_vin_cnfg_axiwr0_pix_ct RW 0x0

  • 00: 1 64-bit equals to 2 pixels

  • 01: 1 64-bit equals to 4 pixels

  • 10: 1 64-bit equals to 8 pixels
[16:15] u0_vin_cnfg_axiwr0_pixel_high_bit_sel RW 0x0 When you configure the above bit as "10" - 1 64-bit equals to 8 pixels, the 8 pixels will use some of the RAW data:

  • 00: pix_data[7:0]

  • 01: pix_data[9:2]

  • 10: pix_data[11:4]

  • 11: pix_data[13:6]
[31:17] Reserved None 0x0 Reserved

SYSCONSAIF__SYSCFG_32

Table 9. SYSCONSAIF__SYSCFG_32 Register Description
Offset Address: 0x20
Default: 0x0
Bit Name Access Default Description
[0:31] u0_vin_cnfg_axiwr0_start_addr RW 0x0 This bit represents the start address of the AXI output image.

SYSCONSAIF__SYSCFG_36

Table 10. SYSCONSAIF__SYSCFG_36 Register Description
Offset Address: 0x24
Default: 0x0
Bit Name Access Default Description
[0] u0_vin_cnfg_color_bar_en RW 0x0 Set this bit to 1 to use the color bar for test.
[1] u0_vin_cnfg_dvp_hs_pos RW 0x0 Use DVP to AXI
  • 1: HS is high valid.
  • 0: HS is low valid.
[2] u0_vin_cnfg_dvp_swap_en RW 0x0 Set this bit to 1 to enable DVP swap.
[3] u0_vin_cnfg_dvp_vs_pos RW 0x0 Use DVP to AXI
  • 1: VS is high valid.
  • 0: VS is low valid.
[4] u0_vin_cnfg_gen_en_axird RW 0x0 Set this bit to use AXI input for ISP and generate the test image.
[5] u0_vin_cnfg_isp_dvp_en0 RW 0x0 Set this bit to use DVP input for ISP.
[6:7] u0_vin_cnfg_mipi_byte_en_isp0 RW 0x0 Set this bit to 1 for dvp_clk_inv, the DVP clock inverter register.
[11:8] u0_vin_cnfg_mipi_channel_sel0 RW 0x0 Select 1 channel output of the 8 MIPI channels
[12] u0_vin_cnfg_p_i_mipi_header_en0 RW 0x0 Set this bit to 1 to add 10 bits to bit 2, so 1 pixel equals to 12 bits.
[16:13] u0_vin_cnfg_pix_num RW 0x0 VIN AXI to ISP MIPI port, 12-bit data configuration:
  • 2b'00: axi_data[11:0]
  • 2b'01: {axi_data[9:0], 2b'0}
  • 2b'10: {axi_data[7:0], 4b'0}
  • 2b'11: {axi_data[5:0], 6b'0}
[26:17] u0_vin_generic_sp RO 0x0 This configuration is not used by JH-7110.
[31:27] Reserved None 0x0 Reserved

SYSCONSAIF__SYSCFG_40

Table 11. SYSCONSAIF__SYSCFG_40 Register Description
Offset Address: 0x28
Default: 0x0
Bit Name Access Default Description
[15:0] u0_vin_test_generic_ctrl RO 0x0 This configuration is not used by JH-7110.
[31:16] u0_vin_test_generic_status RW 0x0 This configuration is not used by JH-7110.