Reference Header

The following code block shows the headers that can be referenced in GPIO configuration.

//GPO SYS_IOMUX
#define GPO_SYS_IOMUX_U0_WAVE511_O_UART_TXSOUT 2
#define GPO_SYS_IOMUX_U0_CAN_CTRL_STBY 3
#define GPO_SYS_IOMUX_U0_CAN_CTRL_TST_NEXT_BIT 4
#define GPO_SYS_IOMUX_U0_CAN_CTRL_TST_SAMPLE_POINT 5
#define GPO_SYS_IOMUX_U0_CAN_CTRL_TXD 6
#define GPO_SYS_IOMUX_U0_CDN_USB_DRIVE_VBUS_IO 7
#define GPO_SYS_IOMUX_U0_CDNS_QSPI_CSN1 8
#define GPO_SYS_IOMUX_U0_CDNS_SPDIF_SPDIFO 9
#define GPO_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_OUT 10
#define GPO_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_OUT 11
#define GPO_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_OUT 12
#define GPO_SYS_IOMUX_U0_DSKIT_WDT_WDOGRES 13
#define GPO_SYS_IOMUX_U0_DW_I2C_IC_CLK_OUT_A 14
#define GPO_SYS_IOMUX_U0_DW_I2C_IC_DATA_OUT_A 15
#define GPO_SYS_IOMUX_U0_DW_SDIO_BACK_END_POWER 16
#define GPO_SYS_IOMUX_U0_DW_SDIO_CARD_POWER_EN 17
#define GPO_SYS_IOMUX_U0_DW_SDIO_CCMD_OD_PULLUP_EN_N 18
#define GPO_SYS_IOMUX_U0_DW_SDIO_RST_N 19
#define GPO_SYS_IOMUX_U0_DW_UART_SOUT 20
#define GPO_SYS_IOMUX_U0_HIFI4_JTDO 21
#define GPO_SYS_IOMUX_U0_JTAG_CERTIFICATION_TDO 22
#define GPO_SYS_IOMUX_U0_PDM_4MIC_DMIC_MCLK 23
#define GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_0 24
#define GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_1 25
#define GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_2 26
#define GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_3 27
#define GPO_SYS_IOMUX_U0_PWMDAC_PWMDAC_LEFT_OUTPUT 28
#define GPO_SYS_IOMUX_U0_PWMDAC_PWMDAC_RIGHT_OUTPUT 29
#define GPO_SYS_IOMUX_U0_SSP_SPI_SSPCLKOUT 30
#define GPO_SYS_IOMUX_U0_SSP_SPI_SSPFSSOUT 31
#define GPO_SYS_IOMUX_U0_SSP_SPI_SSPTXD 32
#define GPO_SYS_IOMUX_U0_SYS_CRG_CLK_GMAC_PHY 33
#define GPO_SYS_IOMUX_U0_SYS_CRG_I2SRX_BCLK_MST 34
#define GPO_SYS_IOMUX_U0_SYS_CRG_I2SRX_LRCK_MST 35
#define GPO_SYS_IOMUX_U0_SYS_CRG_I2STX_BCLK_MST 36
#define GPO_SYS_IOMUX_U0_SYS_CRG_I2STX_LRCK_MST 37
#define GPO_SYS_IOMUX_U0_SYS_CRG_MCLK_OUT 38
#define GPO_SYS_IOMUX_U0_SYS_CRG_TDM_CLK_MST 39
#define GPO_SYS_IOMUX_U0_TDM16SLOT_PCM_SYNCOUT 40
#define GPO_SYS_IOMUX_U0_TDM16SLOT_PCM_TXD 41
#define GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_0 42
#define GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_1 43
#define GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_2 44
#define GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_3 45
#define GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TREF 46
#define GPO_SYS_IOMUX_U1_CAN_CTRL_STBY 47
#define GPO_SYS_IOMUX_U1_CAN_CTRL_TST_NEXT_BIT 48
#define GPO_SYS_IOMUX_U1_CAN_CTRL_TST_SAMPLE_POINT 49
#define GPO_SYS_IOMUX_U1_CAN_CTRL_TXD 50
#define GPO_SYS_IOMUX_U1_DW_I2C_IC_CLK_OUT_A 51
#define GPO_SYS_IOMUX_U1_DW_I2C_IC_DATA_OUT_A 52
#define GPO_SYS_IOMUX_U1_DW_SDIO_BACK_END_POWER 53
#define GPO_SYS_IOMUX_U1_DW_SDIO_CARD_POWER_EN 54
#define GPO_SYS_IOMUX_U1_DW_SDIO_CCLK_OUT 55
#define GPO_SYS_IOMUX_U1_DW_SDIO_CCMD_OD_PULLUP_EN_N 56
#define GPO_SYS_IOMUX_U1_DW_SDIO_CCMD_OUT 57
#define GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_0 58
#define GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_1 59
#define GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_2 60
#define GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_3 61
#define GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_4 62
#define GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_5 63
#define GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_6 64
#define GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_7 65
#define GPO_SYS_IOMUX_U1_DW_SDIO_RST_N 66
#define GPO_SYS_IOMUX_U1_DW_UART_RTS_N 67
#define GPO_SYS_IOMUX_U1_DW_UART_SOUT 68
#define GPO_SYS_IOMUX_U1_I2STX_4CH_SDO0 69
#define GPO_SYS_IOMUX_U1_I2STX_4CH_SDO1 70
#define GPO_SYS_IOMUX_U1_I2STX_4CH_SDO2 71
#define GPO_SYS_IOMUX_U1_I2STX_4CH_SDO3 72
#define GPO_SYS_IOMUX_U1_SSP_SPI_SSPCLKOUT 73
#define GPO_SYS_IOMUX_U1_SSP_SPI_SSPFSSOUT 74
#define GPO_SYS_IOMUX_U1_SSP_SPI_SSPTXD 75
#define GPO_SYS_IOMUX_U2_DW_I2C_IC_CLK_OUT_A 76
#define GPO_SYS_IOMUX_U2_DW_I2C_IC_DATA_OUT_A 77
#define GPO_SYS_IOMUX_U2_DW_UART_RTS_N 78
#define GPO_SYS_IOMUX_U2_DW_UART_SOUT 79
#define GPO_SYS_IOMUX_U2_SSP_SPI_SSPCLKOUT 80
#define GPO_SYS_IOMUX_U2_SSP_SPI_SSPFSSOUT 81
#define GPO_SYS_IOMUX_U2_SSP_SPI_SSPTXD 82
#define GPO_SYS_IOMUX_U3_DW_I2C_IC_CLK_OUT_A 83
#define GPO_SYS_IOMUX_U3_DW_I2C_IC_DATA_OUT_A 84
#define GPO_SYS_IOMUX_U3_DW_UART_SOUT 85
#define GPO_SYS_IOMUX_U3_SSP_SPI_SSPCLKOUT 86
#define GPO_SYS_IOMUX_U3_SSP_SPI_SSPFSSOUT 87
#define GPO_SYS_IOMUX_U3_SSP_SPI_SSPTXD 88
#define GPO_SYS_IOMUX_U4_DW_I2C_IC_CLK_OUT_A 89
#define GPO_SYS_IOMUX_U4_DW_I2C_IC_DATA_OUT_A 90
#define GPO_SYS_IOMUX_U4_DW_UART_RTS_N 91
#define GPO_SYS_IOMUX_U4_DW_UART_SOUT 92
#define GPO_SYS_IOMUX_U4_SSP_SPI_SSPCLKOUT 93
#define GPO_SYS_IOMUX_U4_SSP_SPI_SSPFSSOUT 94
#define GPO_SYS_IOMUX_U4_SSP_SPI_SSPTXD 95
#define GPO_SYS_IOMUX_U5_DW_I2C_IC_CLK_OUT_A 96
#define GPO_SYS_IOMUX_U5_DW_I2C_IC_DATA_OUT_A 97
#define GPO_SYS_IOMUX_U5_DW_UART_RTS_N 98
#define GPO_SYS_IOMUX_U5_DW_UART_SOUT 99
#define GPO_SYS_IOMUX_U5_SSP_SPI_SSPCLKOUT 100
#define GPO_SYS_IOMUX_U5_SSP_SPI_SSPFSSOUT 101
#define GPO_SYS_IOMUX_U5_SSP_SPI_SSPTXD 102
#define GPO_SYS_IOMUX_U6_DW_I2C_IC_CLK_OUT_A 103
#define GPO_SYS_IOMUX_U6_DW_I2C_IC_DATA_OUT_A 104
#define GPO_SYS_IOMUX_U6_SSP_SPI_SSPCLKOUT 105
#define GPO_SYS_IOMUX_U6_SSP_SPI_SSPFSSOUT 106
#define GPO_SYS_IOMUX_U6_SSP_SPI_SSPTXD 107

//GPEN SYS_IOMUX
#define GPEN_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_OEN 2
#define GPEN_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_OEN 3
#define GPEN_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_OEN 4
#define GPEN_SYS_IOMUX_U0_DW_I2C_IC_CLK_OE 5
#define GPEN_SYS_IOMUX_U0_DW_I2C_IC_DATA_OE 6
#define GPEN_SYS_IOMUX_U0_HIFI4_JTDOEN 7
#define GPEN_SYS_IOMUX_U0_JTAG_CERTIFICATION_TDO_OE 8
#define GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_0 9
#define GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_1 10
#define GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_2 11
#define GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_3 12
#define GPEN_SYS_IOMUX_U0_SSP_SPI_NSSPCTLOE 13
#define GPEN_SYS_IOMUX_U0_SSP_SPI_NSSPOE 14
#define GPEN_SYS_IOMUX_U0_TDM16SLOT_NPCM_SYNCOE 15
#define GPEN_SYS_IOMUX_U0_TDM16SLOT_NPCM_TXDOE 16
#define GPEN_SYS_IOMUX_U1_DW_I2C_IC_CLK_OE 17
#define GPEN_SYS_IOMUX_U1_DW_I2C_IC_DATA_OE 18
#define GPEN_SYS_IOMUX_U1_DW_SDIO_CCMD_OUT_EN 19
#define GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_0 20
#define GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_1 21
#define GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_2 22
#define GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_3 23
#define GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_4 24
#define GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_5 25
#define GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_6 26
#define GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_7 27
#define GPEN_SYS_IOMUX_U1_SSP_SPI_NSSPCTLOE 28
#define GPEN_SYS_IOMUX_U1_SSP_SPI_NSSPOE 29
#define GPEN_SYS_IOMUX_U2_DW_I2C_IC_CLK_OE 30
#define GPEN_SYS_IOMUX_U2_DW_I2C_IC_DATA_OE 31
#define GPEN_SYS_IOMUX_U2_SSP_SPI_NSSPCTLOE 32
#define GPEN_SYS_IOMUX_U2_SSP_SPI_NSSPOE 33
#define GPEN_SYS_IOMUX_U3_DW_I2C_IC_CLK_OE 34
#define GPEN_SYS_IOMUX_U3_DW_I2C_IC_DATA_OE 35
#define GPEN_SYS_IOMUX_U3_SSP_SPI_NSSPCTLOE 36
#define GPEN_SYS_IOMUX_U3_SSP_SPI_NSSPOE 37
#define GPEN_SYS_IOMUX_U4_DW_I2C_IC_CLK_OE 38
#define GPEN_SYS_IOMUX_U4_DW_I2C_IC_DATA_OE 39
#define GPEN_SYS_IOMUX_U4_SSP_SPI_NSSPCTLOE 40
#define GPEN_SYS_IOMUX_U4_SSP_SPI_NSSPOE 41
#define GPEN_SYS_IOMUX_U5_DW_I2C_IC_CLK_OE 42
#define GPEN_SYS_IOMUX_U5_DW_I2C_IC_DATA_OE 43
#define GPEN_SYS_IOMUX_U5_SSP_SPI_NSSPCTLOE 44
#define GPEN_SYS_IOMUX_U5_SSP_SPI_NSSPOE 45
#define GPEN_SYS_IOMUX_U6_DW_I2C_IC_CLK_OE 46
#define GPEN_SYS_IOMUX_U6_DW_I2C_IC_DATA_OE 47
#define GPEN_SYS_IOMUX_U6_SSP_SPI_NSSPCTLOE 48
#define GPEN_SYS_IOMUX_U6_SSP_SPI_NSSPOE 49

//GPI SYS_IOMUX
#define GPI_SYS_IOMUX_U0_WAVE511_I_UART_RXSIN 0
#define GPI_SYS_IOMUX_U0_CAN_CTRL_RXD 1
#define GPI_SYS_IOMUX_U0_CDN_USB_OVERCURRENT_N_IO 2
#define GPI_SYS_IOMUX_U0_CDNS_SPDIF_SPDIFI 3
#define GPI_SYS_IOMUX_U0_CLKRST_SRC_BYPASS_JTAG_TRSTN 4
#define GPI_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_IN 5
#define GPI_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_IN 6
#define GPI_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_IN 7
#define GPI_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_HPD 8
#define GPI_SYS_IOMUX_U0_DW_I2C_IC_CLK_IN_A 9
#define GPI_SYS_IOMUX_U0_DW_I2C_IC_DATA_IN_A 10
#define GPI_SYS_IOMUX_U0_DW_SDIO_CARD_DETECT_N 11
#define GPI_SYS_IOMUX_U0_DW_SDIO_CARD_INT_N 12
#define GPI_SYS_IOMUX_U0_DW_SDIO_CARD_WRITE_PRT 13
#define GPI_SYS_IOMUX_U0_DW_UART_SIN 14
#define GPI_SYS_IOMUX_U0_HIFI4_JTCK 15
#define GPI_SYS_IOMUX_U0_HIFI4_JTDI 16
#define GPI_SYS_IOMUX_U0_HIFI4_JTMS 17
#define GPI_SYS_IOMUX_U0_HIFI4_JTRSTN 18
#define GPI_SYS_IOMUX_U0_JTAG_CERTIFICATION_TDI 19
#define GPI_SYS_IOMUX_U0_JTAG_CERTIFICATION_TMS 20
#define GPI_SYS_IOMUX_U0_PDM_4MIC_DMIC0_DIN 21
#define GPI_SYS_IOMUX_U0_PDM_4MIC_DMIC1_DIN 22
#define GPI_SYS_IOMUX_U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN0 23
#define GPI_SYS_IOMUX_U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN1 24
#define GPI_SYS_IOMUX_U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN2 25
#define GPI_SYS_IOMUX_U0_SSP_SPI_SSPCLKIN 26
#define GPI_SYS_IOMUX_U0_SSP_SPI_SSPFSSIN 27
#define GPI_SYS_IOMUX_U0_SSP_SPI_SSPRXD 28
#define GPI_SYS_IOMUX_U0_SYS_CRG_CLK_JTAG_TCK 29
#define GPI_SYS_IOMUX_U0_SYS_CRG_EXT_MCLK 30
#define GPI_SYS_IOMUX_U0_SYS_CRG_I2SRX_BCLK_SLV 31
#define GPI_SYS_IOMUX_U0_SYS_CRG_I2SRX_LRCK_SLV 32
#define GPI_SYS_IOMUX_U0_SYS_CRG_I2STX_BCLK_SLV 33
#define GPI_SYS_IOMUX_U0_SYS_CRG_I2STX_LRCK_SLV 34
#define GPI_SYS_IOMUX_U0_SYS_CRG_TDM_CLK_SLV 35
#define GPI_SYS_IOMUX_U0_TDM16SLOT_PCM_RXD 36
#define GPI_SYS_IOMUX_U0_TDM16SLOT_PCM_SYNCIN 37
#define GPI_SYS_IOMUX_U1_CAN_CTRL_RXD 38
#define GPI_SYS_IOMUX_U1_DW_I2C_IC_CLK_IN_A 39
#define GPI_SYS_IOMUX_U1_DW_I2C_IC_DATA_IN_A 40
#define GPI_SYS_IOMUX_U1_DW_SDIO_CARD_DETECT_N 41
#define GPI_SYS_IOMUX_U1_DW_SDIO_CARD_INT_N 42
#define GPI_SYS_IOMUX_U1_DW_SDIO_CARD_WRITE_PRT 43
#define GPI_SYS_IOMUX_U1_DW_SDIO_CCMD_IN 44
#define GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_0 45
#define GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_1 46
#define GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_2 47
#define GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_3 48
#define GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_4 49
#define GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_5 50
#define GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_6 51
#define GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_7 52
#define GPI_SYS_IOMUX_U1_DW_SDIO_DATA_STROBE 53
#define GPI_SYS_IOMUX_U1_DW_UART_CTS_N 54
#define GPI_SYS_IOMUX_U1_DW_UART_SIN 55
#define GPI_SYS_IOMUX_U1_SSP_SPI_SSPCLKIN 56
#define GPI_SYS_IOMUX_U1_SSP_SPI_SSPFSSIN 57
#define GPI_SYS_IOMUX_U1_SSP_SPI_SSPRXD 58
#define GPI_SYS_IOMUX_U2_DW_I2C_IC_CLK_IN_A 59
#define GPI_SYS_IOMUX_U2_DW_I2C_IC_DATA_IN_A 60
#define GPI_SYS_IOMUX_U2_DW_UART_CTS_N 61
#define GPI_SYS_IOMUX_U2_DW_UART_SIN 62
#define GPI_SYS_IOMUX_U2_SSP_SPI_SSPCLKIN 63
#define GPI_SYS_IOMUX_U2_SSP_SPI_SSPFSSIN 64
#define GPI_SYS_IOMUX_U2_SSP_SPI_SSPRXD 65
#define GPI_SYS_IOMUX_U3_DW_I2C_IC_CLK_IN_A 66
#define GPI_SYS_IOMUX_U3_DW_I2C_IC_DATA_IN_A 67
#define GPI_SYS_IOMUX_U3_DW_UART_SIN 68
#define GPI_SYS_IOMUX_U3_SSP_SPI_SSPCLKIN 69
#define GPI_SYS_IOMUX_U3_SSP_SPI_SSPFSSIN 70
#define GPI_SYS_IOMUX_U3_SSP_SPI_SSPRXD 71
#define GPI_SYS_IOMUX_U4_DW_I2C_IC_CLK_IN_A 72
#define GPI_SYS_IOMUX_U4_DW_I2C_IC_DATA_IN_A 73
#define GPI_SYS_IOMUX_U4_DW_UART_CTS_N 74
#define GPI_SYS_IOMUX_U4_DW_UART_SIN 75
#define GPI_SYS_IOMUX_U4_SSP_SPI_SSPCLKIN 76
#define GPI_SYS_IOMUX_U4_SSP_SPI_SSPFSSIN 77
#define GPI_SYS_IOMUX_U4_SSP_SPI_SSPRXD 78
#define GPI_SYS_IOMUX_U5_DW_I2C_IC_CLK_IN_A 79
#define GPI_SYS_IOMUX_U5_DW_I2C_IC_DATA_IN_A 80
#define GPI_SYS_IOMUX_U5_DW_UART_CTS_N 81
#define GPI_SYS_IOMUX_U5_DW_UART_SIN 82
#define GPI_SYS_IOMUX_U5_SSP_SPI_SSPCLKIN 83
#define GPI_SYS_IOMUX_U5_SSP_SPI_SSPFSSIN 84
#define GPI_SYS_IOMUX_U5_SSP_SPI_SSPRXD 85
#define GPI_SYS_IOMUX_U6_DW_I2C_IC_CLK_IN_A 86
#define GPI_SYS_IOMUX_U6_DW_I2C_IC_DATA_IN_A 87
#define GPI_SYS_IOMUX_U6_SSP_SPI_SSPCLKIN 88
#define GPI_SYS_IOMUX_U6_SSP_SPI_SSPFSSIN 89
#define GPI_SYS_IOMUX_U6_SSP_SPI_SSPRXD 90

//GPO AON_IOMUX
#define GPO_AON_IOMUX_U0_AON_CRG_CLK_32K_OUT 2
#define GPO_AON_IOMUX_U0_PWM_8CH_PTC_PWM_4 3
#define GPO_AON_IOMUX_U0_PWM_8CH_PTC_PWM_5 4
#define GPO_AON_IOMUX_U0_PWM_8CH_PTC_PWM_6 5
#define GPO_AON_IOMUX_U0_PWM_8CH_PTC_PWM_7 6
#define GPO_AON_IOMUX_U0_SYS_CRG_CLK_GCLK0 7
#define GPO_AON_IOMUX_U0_SYS_CRG_CLK_GCLK1 8
#define GPO_AON_IOMUX_U0_SYS_CRG_CLK_GCLK2 9

//GPEN AON_IOMUX
#define GPEN_AON_IOMUX_U0_PWM_8CH_PTC_OE_N_4 2
#define GPEN_AON_IOMUX_U0_PWM_8CH_PTC_OE_N_5 3
#define GPEN_AON_IOMUX_U0_PWM_8CH_PTC_OE_N_6 4
#define GPEN_AON_IOMUX_U0_PWM_8CH_PTC_OE_N_7 5

//GPI AON_IOMUX
#define GPI_AON_IOMUX_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_0 0
#define GPI_AON_IOMUX_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_1 1
#define GPI_AON_IOMUX_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_2 2
#define GPI_AON_IOMUX_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_3 3