Ethernet MAC Layout Requirements
To work around the issue that JH-7110 only supports RGMII mode for Ethernet MAC connections, StarFive offers the layout recommendations depending on your need.
1,000 M Mode
If you want the 1,000 M mode support only, follow the layout design requirements
below:
- The RX/TX trace length cannot exceed 6,000 mil.
- Match the RXD[3:0] signal group and the RX_CTL and RX_CLK signals with trace length to within 100 mil. Match the TXD[3:0] signal group and the TX_CTL and TX_CLK group trace length to within 100 mil.
- The routing of data and clock lanes should keep a complete reference plane
10/100/1,000 M Mode Auto-negotiation
If you want support for 10/100/1,000 M mode auto-negotiation, be aware of the following limitations, and then you can design the layout following the requirements below.
Limitations: Only the following PHY models are supported. Additionally, you need to
connect the RX_CLK of the PHY to its TX_CLK as shown by the orange lines in the
following diagram.
- YT8521DH/DC
- YT8531DH/DC
Layout Requirements for GMAC0
- The trace length from TX_CLK to RX_CLK cannot exceed 500 mil.
- The RX and TX trace length cannot exceed 4,300 mil.
- Match the RXD[3:0] signal group and the RX_CTL and RX_CLK signals with trace length to within 100 mil.
- Match the TXD[3:0] signal group and the TX_CTL and RX_CLK signals with trace length to within 100 mil.
- The routing of data and clock lanes should keep a complete reference plane.
Layout Requirements for GMAC1
- The trace length from TX_CLK to RX_CLK cannot exceed 500 mil.
- The RX_CLK trace length cannot exceed 4,000 mil. Match the RXD[3:0] signal group and the RX_CTL and RX_CLK signals with trace length to within 100 mil.
- The TX_CLK trace length is 2,000 mil longer than that of the RX_CLK. Match the TXD[3:0] signal group and the TX_CTL and RX_CLK signals with trace length to within 100 mil.
- The routing of data and clock lanes should keep a complete reference plane.