U74 Memory Map

The following table shows the memory map of U74 Core Complex.

Table 1. U74 Memory Map
Start Address End Address Size Attribute Device
0x00_0000_0000 0x00_0000_00FF Debug
0x00_0000_0100 0x00_0000_2FFF Reserved
0x00_0000_3000 0x00_0000_3FFF RWX A Error Device
0x00_0000_4000 0x00_015F_FFFF Reserved
0x00_0110_1000 0x00_0110_1FFF 8KB RWX A S7 Hart0 DTIM
0x00_0170_0000 0x00_0170_0FFF RW A S7 Hart0 Bus-Error Unit
0x00_0170_1000 0x00_0170_1FFF RW A U7 Hart1 Bus-Error Unit
0x00_0170_2000 0x00_0170_2FFF RW A U7 Hart2 Bus-Error Unit
0x00_0170_3000 0x00_0170_3FFF RW A U7 Hart3 Bus-Error Unit
0x00_0170_4000 0x00_0170_4FFF RW A U7 Hart3 Bus-Error Unit
0x00_0170_5000 0x00_01FF_FFFF Reserved
0x00_0200_0000 0x00_0200_FFFF RW A CLINT
0x00_0201_0000 0x00_0201_3FFF RW A L2 Cache controller
0x00_0201_4000 0x00_0203_1FFF Reserved
0x00_0203_2000 0x00_0203_3FFF RW A U7 Hart1 L2 Prefetcher
0x00_0203_4000 0x00_0203_5FFF RW A U7 Hart2 L2 Prefetcher
0x00_0203_6000 0x00_0203_7FFF RW A U7 Hart3 L2 Prefetcher
0x00_0203_8000 0x00_0203_9FFF RW A U7 Hart4 L2 Prefetcher
0x00_0203_A000 0x00_07FF_FFFF Reserved
0x00_0800_0000 0x00_081F_FFFF RWX A L2 LIM
0x00_0820_0000 0x00_09FF_FFFF RW A Reserved
0x00_0A00_0000 0x00_0A1F_FFFF RWX I A L2 Zero Device
0x00_0A20_0000 0x00_0BFF_FFFF Reserved
0x00_0C00_0000 0x00_0FFF_FFFF RW A PLIC
0x00_0000_0000 0x00_0FFF_FFFF U74 internal
0x00_1000_0000 0x00_1FFF_FFFF 256MB Peripheral port
0x00_2000_0000 0x00_3FFF_FFFF 512MB RWX A System port
0x00_4000_0000 0x04_3FFF_FFFF 16GB Memory port
0x04_4000_0000 0x08_3FFF_FFFF 16GB RW A System port
0x09_0000_0000 0x09_7FFF_FFFF 2GB RWX A System port
0x09_8000_0000 0x09_FFFF_FFFF 2GB RWX A PCIE configuration space + memory space