DOM VOUT CRG

The Control Registers of dom_vout_crg are described in the following tables.

clk_apb

Table 1. clk_apb Register Description
Offset Address: 16'h0
Access: RW
Bit Name Default Description
[31] Reserved 0 Reserved
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] clk_divcfg 24'h4 Clock divider coefficient:
  • Max: 8
  • Default: 4
  • Min: 4
  • Typical: 4

clk_dc8200_pix0

Table 2. clk_dc8200_pix0 Register Description
Offset Address: 16'h4
Access: RW
Bit Name Default Description
[31] Reserved 0 Reserved
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] clk_divcfg 24'h4 Clock divider coefficient:
  • Max: 63
  • Default: 4
  • Min: 4
  • Typical: 4

clk_dsi_sys

Table 3. clk_dsi_sys Register Description
Offset Address: 16'h8
Access: RW
Bit Name Default Description
[31] Reserved 0 Reserved
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] clk_divcfg 24'h4 Clock divider coefficient:
  • Max: 31
  • Default: 4
  • Min: 4
  • Typical: 4

clk_tx_esc

Table 4. clk_tx_esc Register Description
Offset Address: 16'hc
Access: RW
Bit Name Default Description
[31] Reserved 0 Reserved
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] clk_divcfg 24'h12 Clock divider coefficient:
  • Max: 31
  • Default: 12
  • Min: 10
  • Typical: 12

clk_u0_dc8200_clk_axi

Table 5. clk_u0_dc8200_clk_axi Register Description
Offset Address: 16'h10
Access: RW
Bit Name Default Description
[31] clk_icg 0
  • 1: Clock enable
  • 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

clk_u0_dc8200_clk_core

Table 6. clk_u0_dc8200_clk_core Register Description
Offset Address: 16'h14
Access: RW
Bit Name Default Description
[31] clk_icg 0
  • 1: Clock enable
  • 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

clk_u0_dc8200_clk_ahb

Table 7. clk_u0_dc8200_clk_ahb Register Description
Offset Address: 16'h18
Access: RW
Bit Name Default Description
[31] clk_icg 0
  • 1: clock enable
  • 0: clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

clk_u0_dc8200_clk_pix0

Table 8. clk_u0_dc8200_clk_pix0 Register Description
Offset Address: 16'h1c
Access: RW
Bit Name Default Description
[31] clk_icg 0
  • 1: Clock enable
  • 0: Clock disable
[30] Reserved 0 Reserved
[24:29] clk_mux_sel 6"h0 Clock multiplexing selector:
  • clk_dc8200_pix0
  • clk_hdmitx0_pixelclk
[0:23] Reserved 0 Reserved

clk_u0_dc8200_clk_pix1

Table 9. clk_u0_dc8200_clk_pix1 Register Description
Offset Address: 16'h20
Access: RW
Bit Name Default Description
[31] clk_icg 0
  • 1: Clock enable
  • 0: Clock disable
[30] Reserved 0 Reserved
[24:29] clk_mux_sel 6"h0 Clock multiplexing selector:
  • clk_dc8200_pix0
  • clk_hdmitx0_pixelclk
[0:23] Reserved 0 Reserved

clk_dom_vout_top_lcd_clk

Table 10. clk_dom_vout_top_lcd_clk Register Description
Offset Address: 16'h24
Access: RW
Bit Name Default Description
[31] clk_icg 0
  • 1: Clock enable
  • 0: Clock disable
[30] Reserved 0 Reserved
[24:29] clk_mux_sel 6"h0 Clock multiplexing selector:
  • u0_dc8200.clk_pix0_out
  • u0_dc8200.clk_pix1_out
[0:23] Reserved 0 Reserved

clk_u0_cdns_dsiTx_clk_apb

Table 11. clk_u0_cdns_dsiTx_clk_apb Register Description
Offset Address: 16'h28
Access: RW
Bit Name Default Description
[31] clk_icg 0
  • 1: Clock enable
  • 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

clk_u0_cdns_dsiTx_clk_sys

Table 12. clk_u0_cdns_dsiTx_clk_sys Register Description
Offset Address: 16'h2c
Access: RW
Bit Name Default Description
[31] clk_icg 0
  • 1: Clock enable
  • 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

clk_u0_cdns_dsiTx_clk_dpi

Table 13. clk_u0_cdns_dsiTx_clk_dpi Register Description
Offset Address: 16"30
Access: RW
Bit Name Default Description
[31] clk_icg 0
  • 1: Clock enable
  • 0: Clock disable
[30] Reserved 0 Reserved
[24:29] clk_mux_sel 6"h0 Clock multiplexing selector:
  • clk_dc8200_pix0
  • clk_hdmitx0_pixelclk
[0:23] Reserved 0 Reserved

clk_u0_cdns_dsiTx_clk_txesc

Table 14. clk_u0_cdns_dsiTx_clk_txesc Register Description
Offset Address: 16'h34
Access: RW
Bit Name Default Description
[31] clk_icg 0
  • 1: Clock enable
  • 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

clk_u0_mipitx_dphy_clk_txesc

Table 15. clk_u0_cdns_dsiTx_clk_txesc Register Description
Offset Address: 16'h38
Access: RW
Bit Name Default Description
[31] clk_icg 0
  • 1: Clock enable
  • 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

clk_u0_hdmi_tx_clk_mclk

Table 16. clk_u0_hdmi_tx_clk_mclk Register Description
Offset Address: 16'h3c
Access: RW
Bit Name Default Description
[31] clk_icg 0
  • 1: Clock enable
  • 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

clk_u0_hdmi_tx_clk_bclk

Table 17. clk_u0_hdmi_tx_clk_bclk Register Description
Offset Address: 16'h40
Access: RW
Bit Name Default Description
[31] clk_icg 0
  • 1: Clock enable
  • 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

clk_u0_hdmi_tx_clk_sys

Table 18. clk_u0_hdmi_tx_clk_sys Register Description
Offset Address: 16'h44
Access: RW
Bit Name Default Description
[31] clk_icg 0
  • 1: Clock enable
  • 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

Software_RESET_assert0_addr_assert_sel

Table 19. Software_RESET_assert0_addr_assert_sel Register Description
Offset Address: 16'h38
Access: RW
Bit Name Default Description
[0] rstn_u0_dc8200_rstn_axi 1
  • 1: Assert reset
  • 0: De-assert reset
[1] rstn_u0_dc8200_rstn_ahb 1
  • 1: Assert reset
  • 0: De-assert reset
[2] rstn_u0_dc8200_rstn_core 1
  • 1: Assert reset
  • 0: De-assert reset
[3] rstn_u0_cdns_dsiTx_rstn_dpi 1
  • 1: Assert reset
  • 0: De-assert reset
[4] rstn_u0_cdns_dsiTx_rstn_apb 1
  • 1: Assert reset
  • 0: De-assert reset
[5] rstn_u0_cdns_dsiTx_rstn_rxesc 1
  • 1: Assert reset
  • 0: De-assert reset
[6] rstn_u0_cdns_dsiTx_rstn_sys 1
  • 1: Assert reset
  • 0: De-assert reset
[7] rstn_u0_cdns_dsiTx_rstn_txbytehs 1
  • 1: Assert reset
  • 0: De-assert reset
[8] rstn_u0_cdns_dsiTx_rstn_txesc 1
  • 1: Assert reset
  • 0: De-assert reset
[9] rstn_u0_hdmi_tx_rstn_hdmi 1
  • 1: Assert reset
  • 0: De-assert reset
[10] rstn_u0_mipitx_dphy_rstn_sys 1
  • 1: Assert reset
  • 0: De-assert reset
[11] rstn_u0_mipitx_dphy_rstn_txbytehs 1
  • 1: Assert reset
  • 0: De-assert reset
[31:12] Reserved 0 Reserved

VOUTCRG_RESET_STATUS

Table 20. VOUTCRG_RESET_STATUS Register Description
Offset Address: 16'h4c
Access: RW
Bit Name Default Description
[0] rstn_u0_dc8200_rstn_axi 1
  • 1: Assert reset
  • 0: De-assert reset
[1] rstn_u0_dc8200_rstn_ahb 1
  • 1: Assert reset
  • 0: De-assert reset
[2] rstn_u0_dc8200_rstn_core 1
  • 1: Assert reset
  • 0: De-assert reset
[3] rstn_u0_cdns_dsiTx_rstn_dpi 1
  • 1: Assert reset
  • 0: De-assert reset
[4] rstn_u0_cdns_dsiTx_rstn_apb 1
  • 1: Assert reset
  • 0: De-assert reset
[5] rstn_u0_cdns_dsiTx_rstn_rxesc 1
  • 1: Assert reset
  • 0: De-assert reset
[6] rstn_u0_cdns_dsiTx_rstn_sys 1
  • 1: Assert reset
  • 0: De-assert reset
[7] rstn_u0_cdns_dsiTx_rstn_txbytehs 1
  • 1: Assert reset
  • 0: De-assert reset
[8] rstn_u0_cdns_dsiTx_rstn_txesc 1
  • 1: Assert reset
  • 0: De-assert reset
[9] rstn_u0_hdmi_tx_rstn_hdmi 1
  • 1: Assert reset
  • 0: De-assert reset
[10] rstn_u0_mipitx_dphy_rstn_sys 1
  • 1: Assert reset
  • 0: De-assert reset
[11] rstn_u0_mipitx_dphy_rstn_txbytehs 1
  • 1: Assert reset
  • 0: De-assert reset
[31:12] Reserved 0 Reserved