DOM VOUT SYSCON

The Control Registers of dom_vout_syscon are described in the following tables.

DOM_VOUT_SYSCONSAIF__SYSCFG_0

Table 1. DOM_VOUT_SYSCONSAIF__SYSCFG_0 Register Description
Offset Address: 0x0
Default: 0x0
Bit Name Access Default Description
[7:0] u0_cdns_dsiTx_SCFG_sram_config WR 0x0 SRAM configuration:
  • [0]: SD, shut down enable, high active.
  • [1]: SLP, sleep enable, high active.
[23:8] u0_cdns_dsiTx_dsi_test_generic_ctrl RO 0x0
[31:24] Reserved None 0x0 Reserved

DOM_VOUT_SYSCONSAIF__SYSCFG_4

Table 2. DOM_VOUT_SYSCONSAIF__SYSCFG_4 Register Description
Offset Address: 0x4
Default: 0x80000
Bit Name Access Default Description
[15:0] u0_cdns_dsiTx_dsi_test_generic_status WR 0x0
[16] u0_dc8200_CACTIVE RO 0x0
[17] u0_dc8200_CSYSACK RO 0x0
[18] u0_dc8200_CSYSREQ WR 0x0
[19] u0_dc8200_disableRamClockGating WR 0x1
[20] u0_display_panel_mux_panel_sel WR 0x0 DC8200 panel:

  • 0 - Panel 0

  • 1 - Panel 1
[23:21] u0_dsiTx_data_mapping_dp_mode WR 0x0
DP color mode:
  • 0 - YUV420 CFG1
  • 1 - YUV420 CFG3
  • 2 - YUV422 CFG1 (Reserved)
  • 3 - RGB888
  • 4 - RGB101010/RGB666
  • 5 - RGB565
[24] u0_dsiTx_data_mapping_dpi_dp_sel WR 0x0
DC8200 DP/DPI interface for dsiTx:
  • 0 - DPI
  • 1 - DP
[25] u0_hdmi_data_mapping_dp_bit_depth WR 0x0
DP bit depth:
  • 0 - 8 bit
  • 1 - 10 bit
[27:26] u0_hdmi_data_mapping_dp_yuv_mode WR 0x0
DP YUV mode:
  • 0 - YUV420
  • 1 - YUV422
  • 2 - YUV444
  • 3 - RGB
[29:28] u0_hdmi_data_mapping_dpi_bit_depth WR 0x0
DPI bit depth:
  • 0 - 8 bit
  • 1 - 10 bit
  • 2 - 6 bit CFG1 in DC8200
  • 3 - RGB565 CFG1 in DC8200
[30] u0_hdmi_data_mapping_dpi_dp_sel WR 0x0
DC8200 DP/DPI interface:
  • 0 - DPI
  • 1 - DP
[31] Reserved None 0x0 Reserved

DOM_VOUT_SYSCONSAIF__SYSCFG_8

Table 3. DOM_VOUT_SYSCONSAIF__SYSCFG_8 Register Description
Offset Address: 0x8
Default: 0x0
Bit Name Access Default Description
[1:0] u0_lcd_data_mapping_dp_rgb_fmt WR 0x0 RGB format in DP data:
  • 0 - RGB888
  • 1 - RGB666
  • 2 - RGB565
[2] u0_lcd_data_mapping_dpi_dp_sel WR 0x0 DPI or DP:
  • 0 - DPI
  • 1 - DP
[3] u1_display_panel_mux_panel_sel WR 0x0 DC8200 panel:
  • 0 - Panel 0
  • 1 - Panel 1
[4] u2_display_panel_mux_panel_sel WR 0x0 DC8200 panel:
  • 0 - Panel 0
  • 1 - Panel 1
[31:5] Reserved None 0x0 Reserved

DOM_VOUT_SYSCONSAIF__SYSCFG_12

Table 4. DOM_VOUT_SYSCONSAIF__SYSCFG_12 Register Description
Offset Address: 0xc
Default: 0x0
Bit Name Access Default Description
[0:31] vout_test_reg0 WR 0x0

DOM_VOUT_SYSCONSAIF__SYSCFG_16

Table 5. DOM_VOUT_SYSCONSAIF__SYSCFG_16 Register Description
Offset Address: 0x10
Default: 0x0
Bit Name Access Default Description
[0:31] vout_test_reg1 WR 0x0

DOM_VOUT_SYSCONSAIF__SYSCFG_20

Table 6. DOM_VOUT_SYSCONSAIF__SYSCFG_20 Register Description
Offset Address: 0x14
Default: 0x0
Bit Name Access Default Description
[0:31] vout_test_reg2 WR 0x0

DOM_VOUT_SYSCONSAIF__SYSCFG_24

Table 7. DOM_VOUT_SYSCONSAIF__SYSCFG_24 Register Description
Offset Address: 0x18
Default: 0x0
Bit Name Access Default Description
[0:31] vout_test_reg3 WR 0x0