MIPITX APBIF

The Control Registers of mipitx_apbif are described in the following tables.

MIPITX_APBIFSAIF__SYSCFG_0

Table 1. MIPITX_APBIFSAIF__SYSCFG_0 Register Description
Offset Address: 0x0
Default: 0x111a021
Bit Name Access Default Description
[0] u0_mipitx_dphy_AON_POWER_READY_N WR 0x1
[5:1] u0_mipitx_dphy_CFG_CKLANE_SET WR 0x10
[6] u0_mipitx_dphy_CFG_DATABUS16_SEL WR 0x0
[11:7] u0_mipitx_dphy_CFG_DPDN_SWAP WR 0x0
[14:12] u0_mipitx_dphy_CFG_L0_SWAP_SEL WR 0x2
[17:15] u0_mipitx_dphy_CFG_L1_SWAP_SEL WR 0x3
[20:18] u0_mipitx_dphy_CFG_L2_SWAP_SEL WR 0x4
[23:21] u0_mipitx_dphy_CFG_L3_SWAP_SEL WR 0x0
[26:24] u0_mipitx_dphy_CFG_L4_SWAP_SEL WR 0x1
[31:27] Reserved None 0x0 Reserved

MIPITX_APBIFSAIF__SYSCFG_4

Table 2. MIPITX_APBIFSAIF__SYSCFG_4 Register Description
Offset Address: 0x4
Default: 0x0
Bit Name Access Default Description
[0:31] u0_mipitx_dphy_MPOSV_31_0_ RO 0x0

MIPITX_APBIFSAIF__SYSCFG_8

Table 3. MIPITX_APBIFSAIF__SYSCFG_8 Register Description
Offset Address: 0x8
Default: 0x10800000
Bit Name Access Default Description
[14:0] u0_mipitx_dphy_MPOSV_46_32_ RO 0x0
[15] u0_mipitx_dphy_RGS_CDTX_PLL_FM_CPLT RO 0x0
[16] u0_mipitx_dphy_RGS_CDTX_PLL_FM_OVER RO 0x0
[17] u0_mipitx_dphy_RGS_CDTX_PLL_FM_UNDER RO 0x0
[18] u0_mipitx_dphy_RGS_CDTX_PLL_UNLOCK RO 0x0
[23:19] u0_mipitx_dphy_RG_CDTX_L0N_HSTX_RES WR 0x10
[28:24] u0_mipitx_dphy_RG_CDTX_L0P_HSTX_RES WR 0x10
[31:29] Reserved None 0x0 Reserved

MIPITX_APBIFSAIF__SYSCFG_12

Table 4. MIPITX_APBIFSAIF__SYSCFG_12 Register Description
Offset Address: 0xc
Default: 0x21084210
Bit Name Access Default Description
[4:0] u0_mipitx_dphy_RG_CDTX_L1N_HSTX_RES WR 0x10
[9:5] u0_mipitx_dphy_RG_CDTX_L1P_HSTX_RES WR 0x10
[14:10] u0_mipitx_dphy_RG_CDTX_L2N_HSTX_RES WR 0x10
[19:15] u0_mipitx_dphy_RG_CDTX_L2P_HSTX_RES WR 0x10
[24:20] u0_mipitx_dphy_RG_CDTX_L3N_HSTX_RES WR 0x10
[29:25] u0_mipitx_dphy_RG_CDTX_L3P_HSTX_RES WR 0x10
[30:31] Reserved None 0x0 Reserved

MIPITX_APBIFSAIF__SYSCFG_16

Table 5. MIPITX_APBIFSAIF__SYSCFG_16 Register Description
Offset Address: 0x10
Default: 0x210
Bit Name Access Default Description
[4:0] u0_mipitx_dphy_RG_CDTX_L4N_HSTX_RES WR 0x10
[9:5] u0_mipitx_dphy_RG_CDTX_L4P_HSTX_RES WR 0x10
[10:31] Reserved None 0x0 Reserved

MIPITX_APBIFSAIF__SYSCFG_20

Table 6. MIPITX_APBIFSAIF__SYSCFG_20 Register Description
Offset Address: 0x14
Default: 0x0
Bit Name Access Default Description
[0:23] u0_mipitx_dphy_RG_CDTX_PLL_FBK_FRA WR 0x0
[31:24] Reserved None 0x0 Reserved

MIPITX_APBIFSAIF__SYSCFG_24

Table 7. MIPITX_APBIFSAIF__SYSCFG_24 Register Description
Offset Address: 0x18
Default: 0x864
Bit Name Access Default Description
[8:0] u0_mipitx_dphy_RG_CDTX_PLL_FBK_INT WR 0x64
[9] u0_mipitx_dphy_RG_CDTX_PLL_FM_EN WR 0x0
[10] u0_mipitx_dphy_RG_CDTX_PLL_LDO_STB_X2_EN WR 0x0
[12:11] u0_mipitx_dphy_RG_CDTX_PLL_PRE_DIV WR 0x1
[30:13] u0_mipitx_dphy_RG_CDTX_PLL_SSC_DELTA WR 0x0
[31] Reserved None 0x0 Reserved

MIPITX_APBIFSAIF__SYSCFG_28

Table 8. MIPITX_APBIFSAIF__SYSCFG_28 Register Description
Offset Address: 0x1c
Default: 0x0
Bit Name Access Default Description
[17:0] u0_mipitx_dphy_RG_CDTX_PLL_SSC_DELTA_INIT WR 0x0
[18] u0_mipitx_dphy_RG_CDTX_PLL_SSC_EN WR 0x0
[28:19] u0_mipitx_dphy_RG_CDTX_PLL_SSC_PRD WR 0x0
[31:29] Reserved None 0x0 Reserved

MIPITX_APBIFSAIF__SYSCFG_32

Table 9. MIPITX_APBIFSAIF__SYSCFG_32 Register Description
Offset Address: 0x20
Default: 0x530b0000
Bit Name Access Default Description
[7:0] u0_mipitx_dphy_RG_CLANE_HS_CLK_POST_TIME WR 0x0
[15:8] u0_mipitx_dphy_RG_CLANE_HS_CLK_PRE_TIME WR 0x0
[23:16] u0_mipitx_dphy_RG_CLANE_HS_PRE_TIME WR 0xb
[31:24] u0_mipitx_dphy_RG_CLANE_HS_TRAIL_TIME WR 0x53

MIPITX_APBIFSAIF__SYSCFG_36

Table 10. MIPITX_APBIFSAIF__SYSCFG_36 Register Description
Offset Address: 0x24
Default: 0x21160e16
Bit Name Access Default Description
[7:0] u0_mipitx_dphy_RG_CLANE_HS_ZERO_TIME WR 0x16
[15:8] u0_mipitx_dphy_RG_DLANE_HS_PRE_TIME WR 0xe
[23:16] u0_mipitx_dphy_RG_DLANE_HS_TRAIL_TIME WR 0x16
[31:24] u0_mipitx_dphy_RG_DLANE_HS_ZERO_TIME WR 0x21

MIPITX_APBIFSAIF__SYSCFG_40

Table 11. MIPITX_APBIFSAIF__SYSCFG_40 Register Description
Offset Address: 0x28
Default: 0x0
Bit Name Access Default Description
[2:0] u0_mipitx_dphy_RG_EXTD_CYCLE_SEL WR 0x0
[31:3] Reserved None 0x0 Reserved

MIPITX_APBIFSAIF__SYSCFG_44

Table 12. MIPITX_APBIFSAIF__SYSCFG_44 Register Description
Offset Address: 0x2c
Default: 0x0
Bit Name Access Default Description
31:0] u0_mipitx_dphy_SCFG_c_hs_pre_zero_time WR 0x0

MIPITX_APBIFSAIF__SYSCFG_48

Table 13. MIPITX_APBIFSAIF__SYSCFG_48 Register Description
Offset Address: 0x30
Default: 0x0
Bit Name Access Default Description
[0] u0_mipitx_dphy_SCFG_dphy_src_sel WR 0x0
[1:2] u0_mipitx_dphy_SCFG_dsi_txready_esc_sel WR 0x0
[4:3] u0_mipitx_dphy_SCFG_ppi_c_ready_sel WR 0x0
[9:5] u0_mipitx_dphy_VCONTROL WR 0x0
[10:31] Reserved None 0x0 Reserved

MIPITX_APBIFSAIF__SYSCFG_52

Table 14. MIPITX_APBIFSAIF__SYSCFG_52 Register Description
Offset Address: 0x34
Default: 0x87654321
Bit Name Access Default Description
[0:31] u0_mipitx_dphy_XCFGI_DW00 WR 0x87654321

MIPITX_APBIFSAIF__SYSCFG_56

Table 15. MIPITX_APBIFSAIF__SYSCFG_56 Register Description
Offset Address: 0x38
Default: 0xfedcba9
Bit Name Access Default Description
[0:31] u0_mipitx_dphy_XCFGI_DW01 WR 0xfedcba9

MIPITX_APBIFSAIF__SYSCFG_60

Table 16. MIPITX_APBIFSAIF__SYSCFG_60 Register Description
Offset Address: 0x3c
Default: 0x0
Bit Name Access Default Description
[0:31] u0_mipitx_dphy_XCFGI_DW02 WR 0x0

MIPITX_APBIFSAIF__SYSCFG_64

Table 17. MIPITX_APBIFSAIF__SYSCFG_64 Register Description
Offset Address: 0x40
Default: 0x0
Bit Name Access Default Description
[0:31] u0_mipitx_dphy_XCFGI_DW03 WR 0x0

MIPITX_APBIFSAIF__SYSCFG_68

Table 18. MIPITX_APBIFSAIF__SYSCFG_68 Register Description
Offset Address: 0x44
Default: 0x0
Bit Name Access Default Description
[0:31] u0_mipitx_dphy_XCFGI_DW04 WR 0x0

MIPITX_APBIFSAIF__SYSCFG_72

Table 19. MIPITX_APBIFSAIF__SYSCFG_72 Register Description
Offset Address: 0x48
Default: 0x0
Bit Name Access Default Description
[0:31] u0_mipitx_dphy_XCFGI_DW05 WR 0x0

MIPITX_APBIFSAIF__SYSCFG_76

Table 20. MIPITX_APBIFSAIF__SYSCFG_76 Register Description
Offset Address: 0x4c
Default: 0x0
Bit Name Access Default Description
[0:31] u0_mipitx_dphy_XCFGI_DW06 WR 0x0

MIPITX_APBIFSAIF__SYSCFG_80

Table 21. MIPITX_APBIFSAIF__SYSCFG_80 Register Description
Offset Address: 0x50
Default: 0x21084210
Bit Name Access Default Description
[0:31] u0_mipitx_dphy_XCFGI_DW07 WR 0x21084210

MIPITX_APBIFSAIF__SYSCFG_84

Table 22. MIPITX_APBIFSAIF__SYSCFG_84 Register Description
Offset Address: 0x54
Default: 0x84210
Bit Name Access Default Description
[0:31] u0_mipitx_dphy_XCFGI_DW08 WR 0x84210

MIPITX_APBIFSAIF__SYSCFG_88

Table 23. MIPITX_APBIFSAIF__SYSCFG_88 Register Description
Offset Address: 0x58
Default: 0x0
Bit Name Access Default Description
[0:31] u0_mipitx_dphy_XCFGI_DW09 WR 0x0

MIPITX_APBIFSAIF__SYSCFG_92

Table 24. MIPITX_APBIFSAIF__SYSCFG_92 Register Description
Offset Address: 0x5c
Default: 0x0
Bit Name Access Default Description
[0:31] u0_mipitx_dphy_XCFGI_DW0A WR 0x0

MIPITX_APBIFSAIF__SYSCFG_96

Table 25. MIPITX_APBIFSAIF__SYSCFG_96 Register Description
Offset Address: 0x60
Default: 0x0
Bit Name Access Default Description
[0:31] u0_mipitx_dphy_XCFGI_DW0B WR 0x0

MIPITX_APBIFSAIF__SYSCFG_100

Table 26. MIPITX_APBIFSAIF__SYSCFG_100 Register Description
Offset Address: 0x64
Default: 0x0
Bit Name Access Default Description
[7:0] u0_mipitx_dphy_dbg1_mux_dout RO 0x0
[12:8] u0_mipitx_dphy_dbg1_mux_sel WR 0x0
[20:13] u0_mipitx_dphy_dbg2_mux_dout RO 0x0
[25:21] u0_mipitx_dphy_dbg2_mux_sel WR 0x0
[28:26] u0_mipitx_dphy_refclk_in_sel WR 0x0
[29] u0_mipitx_dphy_resetb WR 0x0
[30:31] Reserved None 0x0 Reserved