Perform the following processes to reset the JH-7110 system.
| Block |
Function |
| reset_ctrl |
- Use this block to add a reset source and then sync it using
rstn_sync.
- Use this block to delay the reset for PLL lock, clock
stabilization or other purposes. The delay time is configurable.
- Use this block to release the reset for CPU, bus, a certain
peripheral, or other modules. In this case, the block is used to
release the reset and output core_rstn to
rstGen. So,
core_rstn is used to reset the whole
digital logic module.
|
| rstgen |
Use this block to control the software reset and synchronize the
rstn added by hardware reset and software
reset. |
