Reset Sequence
Follow the sequence below to reset the JH-7110 system.
| Sequence | Description |
|---|---|
| 1 | Powering up the chip, resetting the pad to active, and then latching the boot selection signals. The reset sequence starts after pad is reset to high. |
| 2 | 5us delay, release the always-on domain reset, and clocks generated in always-on domain. And release the reset source on dom_sys_top. |
| 3 | Power down the PLL with 2us time interval |
| 4 | After the PLL power-down has been finished, wait 200us for PLL locking. |
| 5 | 64 cycles of oscillator clock delay, release the system Clock and Reset Generator (CRG)'s reset to prepare the clock for system |
| 6 | 64 cycles of oscillator clock delay, and release the system bus reset |
| 7 | Release CPU core reset after 32 cycles of oscillator clock delay has been completed. And CPU will boot from the boot vector. |