AON CRG

The JH-7110 system provides the following AON CRG Always-ON (AON) control registers.

Oscillator Clock

Table 1. Oscillator Clock Register Description
Offset 16’h0
Access RW
Bit Name Default Description
[31] Reserved 0 Reserved
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] clk_divcfg 24’d4 Clock divider coefficient:
  • Max: 4
  • Default: 4
  • Min: 4
  • Typical: 4

AON APB Function Clock

Table 2. AON APB Function Clock Register Description
Offset 16’h4
Access RW
Bit Name Default Description
[31] Reserved 0 Reserved
[30] Reserved 0 Reserved
[24:29] clk_mux_sel 6’d0 Clock multiplexing selector:
  • clk_osc_div4
  • clk_osc
[0:23] Reserved 0 Reserved

AHB GMAC5 Clock

Table 3. AHB GMAC5 Clock Register Description
Offset 16’h8
Access RW
Bit Name Default Description
[31] clk_icg 0 1: Clock enable / 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

AXI GMAC5 Clock

Table 4. AXI GMAC5 Clock Register Description
Offset 16’hc
Access RW
Bit Name Default Description
[31] clk_icg 0 1: Clock enable / 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

GMAC0 RMII RTX Clock

Table 5. GMAC0 RMII RTX Clock Register Description
Offset 16’h10
Access RW
Bit Name Default Description
[31] Reserved 0 Reserved
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] clk_divcfg 24’d2 Clock divider coefficient:
  • Max: 30
  • Default: 2
  • Min: 2
  • Typical: 2

GMAC5 AXI64 Clock Transmitter

Table 6. GMAC5 AXI64 Clock Transmitter Register Description
Offset 16’h14
Access RW
Bit Name Default Description
[31] clk_icg 0 1: Clock enable / 0: Clock disable
[30] Reserved 0 Reserved
[24:29] clk_mux_sel 6’d0 Clock multiplexing selector:
  • u0_sys_crg.clk_gmac0_gtxclk
  • clk_gmac0_rmii_rtx
[0:23] Reserved 0 Reserved

GMAC5 AXI64 Clock Transmission Inverter

Table 7. GMAC5 AXI64 Clock Transmission Inverter Register Description
Offset 16’h18
Access RW
Bit Name Default Description
[31] Reserved 0 Reserved
[30] clk_polarity 1 1: Clock inverter / 0: Clock buffer
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

GMAC5 AXI64 Clock Receiver

Table 8. GMAC5 AXI64 Clock Receiver Register Description
Offset 16’h1c
Access RW
Bit Name Default Description
[31:24] reserverd 0x0 Reserved
[23: 0] dly_chain_sel 0x0 Selector delay chain stage number, totally 32 stages, -50ps each stage.

The register value indicates the delay chain stage number. For example, dly_chain_sel=1 means to delay 1 stage.

GMAC5 AXI64 Clock Receiving Inverter

Table 9. GMAC5 AXI64 Clock Receiving Inverter Register Description
Offset 16’h20
Access RW
Bit Name Default Description
[31] Reserved 0 Reserved
[30] clk_polarity 1 1: Clock inverter / 0: Clock buffer
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

OPTC APB Clock

Table 10. OPTC APB Clock Register Description
Offset 16’h24
Access RW
Bit Name Default Description
[31] clk_icg 1 1: Clock enable / 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

RTC HMS APB Clock

Table 11. RTC HMS APB Clock Register Description
Offset 16’h28
Access RW
Bit Name Default Description
[31] clk_icg 1 1: Clock enable / 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

RTC Internal Clock

Table 12. RTC Internal Clock Register Description
Offset 16’h2c
Access RW
Bit Name Default Description
[31] Reserved 0 Reserved
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] clk_divcfg 24’d750 Clock divider coefficient:
  • Max: 1,022
  • Default: 750
  • Min: 750
  • Typical: 750

RTC HMS Clock Oscillator 32K

Table 13. RTC HMS Clock Oscillator 32K Register Description
Offset 16’h30
Access RW
Bit Name Default Description
[31] Reserved 0 Reserved
[30] Reserved 0 Reserved
[24:29] clk_mux_sel 6’d0 Clock multiplexing selector:
  • clk_rtc
  • clk_rtc_internal
[0:23] Reserved 0 Reserved

RTC HMS Clock Calculator

Table 14. RTC HMS Clock Calculator Register Description
Offset 16’h34
Access RW
Bit Name Default Description
[31] clk_icg 0 1: Clock enable / 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

Software RESET Address Selector

Table 15. Software RESET Address Selector Register Description
Offset 16’h38
Access RW
Bit Name Default Description
[0] gmac5_axi64_rstn_axi 1
  • 1: Assert reset
  • 0: De-assert reset
[1] gmac5_axi64_rstn_ahb 1
  • 1: Assert reset
  • 0: De-assert reset
[2] aon_iomux_presetn 0
  • 1: Assert reset
  • 0: De-assert reset
[3] pmu_rstn_apb 0
  • 1: Assert reset
  • 0: De-assert reset
[4] pmu_rstn_wkup 0
  • 1: Assert reset
  • 0: De-assert reset
[5] rtc_hms_rstn_apb 1
  • 1: Assert reset
  • 0: De-assert reset
[6] rtc_hms_rstn_cal 1
  • 1: Assert reset
  • 0: De-assert reset
[7] rtc_hms_rstn_osc32k 1
  • 1: Assert reset
  • 0: De-assert reset
[8:31] Reserved 0 Reserved

AONCRG Reset Status

Table 16. AONCRG Reset Status Register Description
Offset 16’h3c
Access RW
Bit Name Default Description
[0] gmac5_axi64_rstn_axi 1
  • 1: Assert reset
  • 0: De-assert reset
[1] gmac5_axi64_rstn_ahb 1
  • 1: Assert reset
  • 0: De-assert reset
[2] aon_iomux_presetn 0
  • 1: Assert reset
  • 0: De-assert reset
[3] pmu_rstn_apb 0
  • 1: Assert reset
  • 0: De-assert reset
[4] pmu_rstn_wkup 0
  • 1: Assert reset
  • 0: De-assert reset
[5] rtc_hms_rstn_apb 1
  • 1: Assert reset
  • 0: De-assert reset
[6] rtc_hms_rstn_cal 1
  • 1: Assert reset
  • 0: De-assert reset
[7] rtc_hms_rstn_osc32k 1
  • 1: Assert reset
  • 0: De-assert reset
[8:31] Reserved 0 Reserved