AON IOMUX CFG

AON IOMUX CFGSAIF SYSCFG FMUX 0

The register can be used to configure the selected (Output Enable) OEN signal for GPIO0 - GPIO3.

Table 1. AON_SYSCONSAIF__SYSCFG_0 Register Description
Offset	0x0
Default	0x1010101
Bit	Name	Access	Default	Description
[2:0]	aon_iomux_gpo0_doen_cfg	WR	0x1	The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See GPIO OEN List for AON_IOMUX for more information.
[7:3]	Reserved	None	0x0	Reserved
[10:8]	aon_iomux_gpo1_doen_cfg	WR	0x1	The selected OEN signal for GPIO1. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See GPIO OEN List for AON_IOMUX for more information.
[15:11]	Reserved	None	0x0	Reserved
[18:16]	aon_iomux_gpo2_doen_cfg	WR	0x1	The selected OEN signal for GPIO2. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See GPIO OEN List for AON_IOMUX for more information.
[23:19]	Reserved	None	0x0	Reserved
[26:24]	aon_iomux_gpo3_doen_cfg	WR	0x1	The selected OEN signal for GPIO3. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See GPIO OEN List for AON_IOMUX for more information.
[31:27]	Reserved	None	0x0	Reserved

AON IOMUX CFGSAIF SYSCFG FMUX 1

The register can be used to configure the selected (Output Enable) OEN signal for GPIO0 - GPIO3.

Table 2. AON IOMUX CFGSAIF SYSCFG FMUX 1 Register Description
Offset	0x4
Default	0x0
Bit	Name	Access	Default	Description
[0:3]	aon_iomux_gpo0_dout_cfg	WR	0x0	The selected OEN signal for GPIO0. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-9. See GPIO OEN List for AON_IOMUX for more information.
[4:7]	Reserved	None	0x0	Reserved
[11:8]	aon_iomux_gpo1_dout_cfg	WR	0x0	The selected OEN signal for GPIO1. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-9. See GPIO OEN List for AON_IOMUX for more information.
[15:12]	Reserved	None	0x0	Reserved
[19:16]	aon_iomux_gpo2_dout_cfg	WR	0x0	The selected OEN signal for GPIO2. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-9. See GPIO OEN List for AON_IOMUX for more information.
[23:20]	Reserved	None	0x0	Reserved
[27:24]	aon_iomux_gpo3_dout_cfg	WR	0x0	The selected OEN signal for GPIO3. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-9. See GPIO OEN List for AON_IOMUX for more information.
[31:28]	Reserved	None	0x0	Reserved

AON IOMUX CFGSAIF SYSCFG FMUX 2

The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "sys_iomux_gpi_u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals for a complete list of the input GPIO signals.

Table 3. AON IOMUX CFGSAIF SYSCFG FMUX 2 Register Description
Offset	0x8
Default	0x5040302
Bit	Name	Access	Default	Description
[2:0]	aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_0_cfg	WR	0x2	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[7:3]	Reserved	None	0x0	Reserved
[10:8]	aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_1_cfg	WR	0x3	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[15:11]	Reserved	None	0x0	Reserved
[18:16]	aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_2_cfg	WR	0x4	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[23:19]	Reserved	None	0x0	Reserved
[26:24]	aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_3_cfg	WR	0x5	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[31:27]	Reserved	None	0x0	Reserved

AON IOMUX CFGSAIF SYSCFG FMUX 3

Table 4. AON IOMUX CFGSAIF SYSCFG IOIRQ 3 Register Description
Offset	0xc
Default	0x0
Bit	Name	Access	Default	Description
[0]	aon_gpioen_0_reg	WR	0x0	Enable GPIO IRQ function
[1:31]	Reserved	None	0x0	Reserved

AON IOMUX CFGSAIF SYSCFG IOIRQ 4

Table 5. AON IOMUX CFGSAIF SYSCFG IOIRQ 4 Register Description
Offset	0x10
Default	0x0
Bit	Name	Access	Default	Description
[0:3]	aon_gpiois_0_reg	WR	0x0	1: Edge trigger 0: Level trigger
[4:31]	Reserved	None	0x0	Reserved

AON IOMUX CFGSAIF SYSCFG IOIRQ 5

Table 6. AON IOMUX CFGSAIF SYSCFG IOIRQ 5 Register Description
Offset	0x14
Default	0x0
Bit	Name	Access	Default	Description
[0:3]	aon_gpioic_0_reg	WR	0x0	1: Do not clear the register 0: Clear the register
[4:31]	Reserved	None	0x0	Reserved

Note: You can write 0 and 1 in aon_gpioic_0_reg sequentially to clear edge IRQ.

AON IOMUX CFGSAIF SYSCFG IOIRQ 6

Table 7. AON IOMUX CFGSAIF SYSCFG IOIRQ 6 Register Description
Offset	0x18
Default	0x0
Bit	Name	Access	Default	Description
[0:3]	aon_gpioibe_0_reg	WR	0x0	1: Trigger on both edges 0: Trigger on a single edge
[4:31]	Reserved	None	0x0	Reserved

AON IOMUX CFGSAIF SYSCFG IOIRQ 7

Table 8. AON IOMUX CFGSAIF SYSCFG IOIRQ 7 Register Description
Offset	0x1c
Default	0x0
Bit	Name	Access	Default	Description
[0:3]	aon_gpioiev_0_reg	WR	0x0	1: Positive/Low 0: Negative/High
[4:31]	Reserved	None	0x0	Reserved

AON IOMUX CFGSAIF SYSCFG IOIRQ 8

Table 9. AON IOMUX CFGSAIF SYSCFG IOIRQ 8 Register Description
Offset	0x20
Default	0x0
Bit	Name	Access	Default	Description
[0:3]	aon_gpioie_0_reg	WR	0x0	1: Unmask 0: Mask
[4:31]	Reserved	None	0x0	Reserved

AON IOMUX CFGSAIF SYSCFG IOIRQ 9

Table 10. AON IOMUX CFGSAIF SYSCFG IOIRQ 9 Register Description
Offset	0x24
Default	0x0
Bit	Name	Access	Default	Description
[0:3]	aon_gpioris_0_reg	RO	0x0	Status of the edge trigger,can be cleared by writing gpioic
[4:31]	Reserved	None	0x0	Reserved

AON IOMUX CFGSAIF SYSCFG IOIRQ 10

Table 11. AON IOMUX CFGSAIF SYSCFG IOIRQ 10 Register Description
Offset	0x28
Default	0x0
Bit	Name	Access	Default	Description
[0:3]	aon_gpiomis_0_reg	RO	0x0	The masked GPIO IRQ status
[4:31]	Reserved	None	0x0	Reserved

AON IOMUX CFGSAIF SYSCFG IOIRQ 11

Table 12. AON IOMUX CFGSAIF SYSCFG IOIRQ 11 Register Description
Offset	0x2c
Default	0x0
Bit	Name	Access	Default	Description
[0:3]	aon_gpio_in_sync2_0_reg	RO	0x0	Status of gpio_in after synchronization
[4:31]	Reserved	None	0x0	Reserved

AON IOMUX CFG SAIF SYSCFG 48

Table 13. AON IOMUX CFG SAIF SYSCFG 48 Register Description
Offset	0x30
Default	0x0
Bit	Name	Access	Default	Description
[0]	PADCFG_PAD_TESTEN_POS	WR	0x0	Power-on-Start (POS) enabler: 1: Enable active pull down for loss of core power 0: Active pull-down capability disabled
[1:31]	Reserved	None	0x0	Reserved

AON IOMUX CFG SAIF SYSCFG 52

The register can be used to configure the core settings of system signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, "PADCFG_PAD_GPIO0_IE" indicates the attribute "IE" of the signal "GPIO0". See Signal Description for a complete list of the system signals.

Table 14. AON IOMUX CFG SAIF SYSCFG 52 Register Description
Offset	0x34
Default	0x1
Bit	Name	Access	Default	Description
[0]	PADCFG_PAD_RGPIO0_IE	WR	0x1	Input Enable (IE) Controller: 1: Enable the receiver 0: Disable the receiver
[1:2]	PADCFG_PAD_RGPIO0_DS	WR	0x0	Output Drive Strength (DS): 00: The rated drive strength is 2 mA. 01: The rated drive strength is 4 mA. 10: The rated drive strength is 8 mA. 01: The rated drive strength is 12 mA.
[3]	PADCFG_PAD_RGPIO0_PU	WR	0x0	Pull-Up (PU) settings: 1: Yes 0: No
[4]	PADCFG_PAD_RGPIO0_PD	WR	0x0	Pull-Down (PD) settings: 1: Yes 0: No
[5]	PADCFG_PAD_RGPIO0_SLEW	WR	0x0	Slew Rate Control: 0: Slow (Half frequency) 1: Fast
[6]	PADCFG_PAD_RGPIO0_SMT	WR	0x0	Active high Schmitt (SMT) trigger selector: 0: No hysteresis 1: Schmitt trigger enabled
[7]	PADCFG_PAD_RGPIO0_POS	WR	0x0	Power-on-Start (POS) enabler: 1: Enable active pull down for loss of core power 0: Active pull-down capability disabled
[8:31]	Reserved	None	0x0	Reserved

AON IOMUX CFG SAIF SYSCFG 56

The register can be used to configure the core settings of system signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, "PADCFG_PAD_GPIO0_IE" indicates the attribute "IE" of the signal "GPIO0". See Signal Description for a complete list of the system signals.

Table 15. AON IOMUX CFG SAIF SYSCFG 56 Register Description
Offset	0x38
Default	0x1
Bit	Name	Access	Default	Description
[0]	PADCFG_PAD_RGPIO1_IE	WR	0x1	Input Enable (IE) Controller: 1: Enable the receiver 0: Disable the receiver
[1:2]	PADCFG_PAD_RGPIO1_DS	WR	0x0	Output Drive Strength (DS): 00: The rated drive strength is 2 mA. 01: The rated drive strength is 4 mA. 10: The rated drive strength is 8 mA. 01: The rated drive strength is 12 mA.
[3]	PADCFG_PAD_RGPIO1_PU	WR	0x0	Pull-Up (PU) settings: 1: Yes 0: No
[4]	PADCFG_PAD_RGPIO1_PD	WR	0x0	Pull-Down (PD) settings: 1: Yes 0: No
[5]	PADCFG_PAD_RGPIO1_SLEW	WR	0x0	Slew Rate Control: 0: Slow (Half frequency) 1: Fast
[6]	PADCFG_PAD_RGPIO1_SMT	WR	0x0	Active high Schmitt (SMT) trigger selector: 0: No hysteresis 1: Schmitt trigger enabled
[7]	PADCFG_PAD_RGPIO1_POS	WR	0x0	Power-on-Start (POS) enabler: 1: Enable active pull down for loss of core power 0: Active pull-down capability disabled
[8:31]	Reserved	None	0x0	Reserved

AON IOMUX CFG SAIF SYSCFG 60

The register can be used to configure the core settings of system signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, "PADCFG_PAD_GPIO0_IE" indicates the attribute "IE" of the signal "GPIO0". See Signal Description for a complete list of the system signals.

Table 16. AON IOMUX CFG SAIF SYSCFG 60 Register Description
Offset	0x3c
Default	0x1
Bit	Name	Access	Default	Description
[0]	PADCFG_PAD_RGPIO2_IE	WR	0x1	Input Enable (IE) Controller: 1: Enable the receiver 0: Disable the receiver
[1:2]	PADCFG_PAD_RGPIO2_DS	WR	0x0	Output Drive Strength (DS): 00: The rated drive strength is 2 mA. 01: The rated drive strength is 4 mA. 10: The rated drive strength is 8 mA. 01: The rated drive strength is 12 mA.
[3]	PADCFG_PAD_RGPIO2_PU	WR	0x0	Pull-Up (PU) settings: 1: Yes 0: No
[4]	PADCFG_PAD_RGPIO2_PD	WR	0x0	Pull-Down (PD) settings: 1: Yes 0: No
[5]	PADCFG_PAD_RGPIO2_SLEW	WR	0x0	Slew Rate Control: 0: Slow (Half frequency) 1: Fast
[6]	PADCFG_PAD_RGPIO2_SMT	WR	0x0	Active high Schmitt (SMT) trigger selector: 0: No hysteresis 1: Schmitt trigger enabled
[7]	PADCFG_PAD_RGPIO2_POS	WR	0x0	Power-on-Start (POS) enabler: 1: Enable active pull down for loss of core power 0: Active pull-down capability disabled
[8:31]	Reserved	None	0x0	Reserved

AON IOMUX CFG SAIF SYSCFG 64

The register can be used to configure the core settings of system signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, "PADCFG_PAD_GPIO0_IE" indicates the attribute "IE" of the signal "GPIO0". See Signal Description for a complete list of the system signals.

Table 17. AON IOMUX CFG SAIF SYSCFG 64 Register Description
Offset	0x40
Default	0x11
Bit	Name	Access	Default	Description
[0]	PADCFG_PAD_RGPIO3_IE	WR	0x1	Input Enable (IE) Controller: 1: Enable the receiver 0: Disable the receiver
[1:2]	PADCFG_PAD_RGPIO3_DS	WR	0x0	Output Drive Strength (DS): 00: The rated drive strength is 2 mA. 01: The rated drive strength is 4 mA. 10: The rated drive strength is 8 mA. 01: The rated drive strength is 12 mA.
[3]	PADCFG_PAD_RGPIO3_PU	WR	0x0	Pull-Up (PU) settings: 1: Yes 0: No
[4]	PADCFG_PAD_RGPIO3_PD	WR	0x1	Pull-Down (PD) settings: 1: Yes 0: No
[5]	PADCFG_PAD_RGPIO3_SLEW	WR	0x0	Slew Rate Control: 0: Slow (Half frequency) 1: Fast
[6]	PADCFG_PAD_RGPIO3_SMT	WR	0x0	Active high Schmitt (SMT) trigger selector: 0: No hysteresis 1: Schmitt trigger enabled
[7]	PADCFG_PAD_RGPIO3_POS	WR	0x0	Power-on-Start (POS) enabler: 1: Enable active pull down for loss of core power 0: Active pull-down capability disabled
[8:31]	Reserved	None	0x0	Reserved

AON IOMUX CFG SAIF SYSCFG 68

Table 18. AON IOMUX CFG SAIF SYSCFG 68 Register Description
Offset	0x44
Default	0x1
Bit	Name	Access	Default	Description
[0]	PADCFG_PAD_RSTN_SMT	WR	0x1	Active high Schmitt (SMT) trigger selector: 0: No hysteresis 1: Schmitt trigger enabled
[1]	PADCFG_PAD_RSTN_POS	WR	0x0	Power-on-Start (POS) enabler: 1: Enable active pull down for loss of core power 0: Active pull-down capability disabled
[2:31]	Reserved	None	0x0	Reserved

AON IOMUX CFG SAIF SYSCFG 76

Table 19. AON IOMUX CFG SAIF SYSCFG 76 Register Description
Offset	0x4c
Default	0x2
Bit	Name	Access	Default	Description
[1:0]	PADCFG_PAD_RTC_DS	WR	0x2	Output Drive Strength (DS): 00: The rated drive strength is 2 mA. 01: The rated drive strength is 4 mA. 10: The rated drive strength is 8 mA. 01: The rated drive strength is 12 mA.
[2:31]	Reserved	None	0x0	Reserved

AON IOMUX CFG SAIF SYSCFG 84

Table 20. AON IOMUX CFG SAIF SYSCFG 84 Register Description
Offset	0x54
Default	0x2
Bit	Name	Access	Default	Description
[1:0]	PADCFG_PAD_OSC_DS	WR	0x2	Output Drive Strength (DS): 00: The rated drive strength is 2 mA. 01: The rated drive strength is 4 mA. 10: The rated drive strength is 8 mA. 01: The rated drive strength is 12 mA.
[2:31]	Reserved	None	0x0	Reserved

AON IOMUX CFG SAIF SYSCFG 88

Table 21. AON IOMUX CFG SAIF SYSCFG 88 Register Description
Offset	0x58
Default	0x2
Bit	Name	Access	Default	Description
[1:0]	PADCFG_PAD_GMAC0_MDC_syscon	WR	0x2
[2:31]	Reserved	None	0x0	Reserved

AON IOMUX CFG SAIF SYSCFG 92

Table 22. AON IOMUX CFG SAIF SYSCFG 92 Register Description
Offset	0x5c
Default	0x2
Bit	Name	Access	Default	Description
[1:0]	PADCFG_PAD_GMAC0_MDIO_syscon	WR	0x2
[2:31]	Reserved	None	0x0	Reserved

AON IOMUX CFG SAIF SYSCFG 96

Table 23. AON IOMUX CFG SAIF SYSCFG 96 Register Description
Offset	0x60
Default	0x2
Bit	Name	Access	Default	Description
[1:0]	PADCFG_PAD_GMAC0_RXD0_syscon	WR	0x2	[1:0] = 0 : GMAC0 IO voltage select 3.3 V [1:0] = 1: GMAC0 IO voltage select 2.5 V [1:0] = 2: GMAC0 IO voltage select 1.8 V
[2:31]	Reserved	None	0x0	Reserved

AON IOMUX CFG SAIF SYSCFG 100

Table 24. AON IOMUX CFG SAIF SYSCFG 100 Register Description
Offset	0x64
Default	0x2
Bit	Name	Access	Default	Description
[1:0]	PADCFG_PAD_GMAC0_RXD1_syscon	WR	0x2
[2:31]	Reserved	None	0x0	Reserved

AON IOMUX CFG SAIF SYSCFG 104

Table 25. AON IOMUX CFG SAIF SYSCFG 104 Register Description
Offset	0x68
Default	0x2
Bit	Name	Access	Default	Description
[1:0]	PADCFG_PAD_GMAC0_RXD2_syscon	WR	0x2
[2:31]	Reserved	None	0x0	Reserved

AON IOMUX CFG SAIF SYSCFG 108

Table 26. AON IOMUX CFG SAIF SYSCFG 108 Register Description
Offset	0x6c
Default	0x2
Bit	Name	Access	Default	Description
[1:0]	PADCFG_PAD_GMAC0_RXD3_syscon	WR	0x2
[2:31]	Reserved	None	0x0	Reserved

AON IOMUX CFG SAIF SYSCFG 112

Table 27. AON IOMUX CFG SAIF SYSCFG 112 Register Description
Offset	0x70
Default	0x2
Bit	Name	Access	Default	Description
[1:0]	PADCFG_PAD_GMAC0_RXDV_syscon	WR	0x2
[2:31]	Reserved	None	0x0	Reserved

AON IOMUX CFG SAIF SYSCFG 116

Table 28. AON IOMUX CFG SAIF SYSCFG 116 Register Description
Offset	0x74
Default	0x2
Bit	Name	Access	Default	Description
[1:0]	PADCFG_PAD_GMAC0_RXC_syscon	WR	0x2
[2:31]	Reserved	None	0x0	Reserved

AON IOMUX CFG SAIF SYSCFG 120

Table 29. AON IOMUX CFG SAIF SYSCFG 120 Register Description
Offset	0x78
Default	0x2
Bit	Name	Access	Default	Description
[1:0]	PADCFG_PAD_GMAC0_TXD0_syscon	WR	0x2
[2:31]	Reserved	None	0x0	Reserved

AON IOMUX CFG SAIF SYSCFG 124

Table 30. AON IOMUX CFG SAIF SYSCFG 124 Register Description
Offset	0x7c
Default	0x2
Bit	Name	Access	Default	Description
[1:0]	PADCFG_PAD_GMAC0_TXD1_syscon	WR	0x2
[2:31]	Reserved	None	0x0	Reserved

AON IOMUX CFG SAIF SYSCFG 128

Table 31. AON IOMUX CFG SAIF SYSCFG 128 Register Description
Offset	0x80
Default	0x2
Bit	Name	Access	Default	Description
[1:0]	PADCFG_PAD_GMAC0_TXD2_syscon	WR	0x2
[2:31]	Reserved	None	0x0	Reserved

AON IOMUX CFG SAIF SYSCFG 132

Table 32. AON IOMUX CFG SAIF SYSCFG 132 Register Description
Offset	0x84
Default	0x2
Bit	Name	Access	Default	Description
[1:0]	PADCFG_PAD_GMAC0_TXD3_syscon	WR	0x2
[2:31]	Reserved	None	0x0	Reserved

AON IOMUX CFG SAIF SYSCFG 136

Table 33. AON IOMUX CFG SAIF SYSCFG 136 Register Description
Offset	0x88
Default	0x2
Bit	Name	Access	Default	Description
[1:0]	PADCFG_PAD_GMAC0_TXEN_syscon	WR	0x2
[2:31]	Reserved	None	0x0	Reserved

AON IOMUX CFG SAIF SYSCFG 140

Table 34. AON IOMUX CFG SAIF SYSCFG 140 Register Description
Offset	0x8c
Default	0x2
Bit	Name	Access	Default	Description
[1:0]	PADCFG_PAD_GMAC0_TXC_syscon	WR	0x2
[2:31]	Reserved	None	0x0	Reserved

AON IOMUX CFGSAIF SYSCFG 144

Table 35. AON IOMUX CFGSAIF SYSCFG 144 Register Description
Offset	0x90
Default	0x0
Bit	Name	Access	Default	Description
[1:0]	PAD_GMAC0_RXC_func_sel	WR	0x0	Function selector of GMAC0_RXC: Function 0: u0_aon_crg.clk_gmac0_rgmii_rx Function 1: u0_aon_crg.clk_gmac0_rmii_ref Function 2: None Function 3: None
[2:31]	Reserved	None	0x0	Reserved