AON SYSCON

The JH-7110 system provides the following AON SYSCON Always-ON (AON) control registers which provides clock and reset signals to interfaces with master and/or slave signals.

AON SYSCONSAIF SYSCFG 0

Table 1. AON SYSCONSAIF SYSCFG 0 Register Description
Offset 0x0
Default 0x0
Bit Name Access Default Description
[0:31] aon_gp_reg WR 0x0

AON SYSCONSAIF SYSCFG 4

Table 2. AON SYSCONSAIF SYSCFG 4 Register Description
Offset 0x4
Default 0x0
Bit Name Access Default Description
[0:3] u0_boot_ctrl_boot_status RO 0x0
[4:31] Reserved None 0x0 Reserved

AON SYSCONSAIF SYSCFG 8

Table 3. AON SYSCONSAIF SYSCFG 8 Register Description
Offset 0x8
Default 0x0
Bit Name Access Default Description
[0:31] u0_boot_ctrl_boot_vector_31_0_ RO 0x0

AON SYSCONSAIF SYSCFG 12

Table 4. AON SYSCONSAIF SYSCFG 12 Register Description
Offset 0xc
Default 0x4d540
Bit Name Access Default Description
[0:3] u0_boot_ctrl_boot_vector_35_32_ RO 0x0
[15:4] gmac5_axi64_SCFG_ram_cfg WR 0xd54 SRAM/ROM configuration.
  • [4]: SLP, sleep enable, high active, default is low.
  • [5]: SD, shutdown enable, high active, default is low.
  • [6:7]: RTSEL, timing setting for debug purpose, default is 2’b01
  • [8:9]: PTSEL, timing setting for debug purpose, default is 2’b01
  • [11:10]: TRB, timing setting for debug purpose, default is 2’b01
  • [13:12]: WTSEL, timing setting for debug purpose, default is 2’b01
  • [14]: VS, timing setting for debug purpose, default is 1’b1
  • [15]: VG, timing setting for debug purpose, default is 1’b1
[17:16] gmac5_axi64_mac_speed_o RO 0x0
[20:18] gmac5_axi64_phy_intf_sel_i WR 0x1

Active PHY Selected

When you have multiple GMAC PHY interfaces in your configuration, this field indicates the sampled value of the PHY selector during reset de-assertion.

Values:

  • 0x0(GMII_MII): GMII or MII
  • 0x1(RGMII): RGMII
  • 0x2(SGMII): SGMII
  • 0x3(TBI): TBI
  • 0x4(RMII): RMII
  • 0x5(RTBI): RTBI
  • 0x6(SMII): SMII
  • 0x7(REVMIII): RevMII
[31:21] Reserved None 0x0 Reserved

AON SYSCONSAIF SYSCFG 16

Table 5. AON SYSCONSAIF SYSCFG 16 Register Description
Offset 0x10
Default 0x0
Bit Name Access Default Description
[0:31] gmac5_axi64_ptp_timestamp_o_31_0_ RO 0x0

AON SYSCONSAIF SYSCFG 20

Table 6. AON SYSCONSAIF SYSCFG 20 Register Description
Offset 0x14
Default 0x0
Bit Name Access Default Description
[0:31] gmac5_axi64_ptp_timestamp_o_63_32_ RO 0x0

AON SYSCONSAIF SYSCFG 24

Table 7. AON SYSCONSAIF SYSCFG 24 Register Description
Offset 0x18
Default 0x0
Bit Name Access Default Description
[0] u0_otpc_chip_mode RO 0x0
[1] u0_otpc_crc_pass RO 0x0
[2] u0_otpc_dbg_enable RO 0x0
[31:3] Reserved None 0x0 Reserved

AON SYSCONSAIF SYSCFG 28

Table 8. AON SYSCONSAIF SYSCFG 28 Register Description
Offset 0x1c
Default 0x0
Bit Name Access Default Description
[0:31] u0_otpc_fl_func_lock RO 0x0

AON SYSCONSAIF SYSCFG 32

Table 9. AON SYSCONSAIF SYSCFG 32 Register Description
Offset 0x20
Default 0x0
Bit Name Access Default Description
[0:31] u0_otpc_fl_pll0_lock RO 0x0

AON SYSCONSAIF SYSCFG 36

Table 10. AON SYSCONSAIF SYSCFG 36 Register Description
Offset 0x24
Default 0x0
Bit Name Access Default Description
[0:31] u0_otpc_fl_pll1_lock RO 0x0

AON SYSCONSAIF SYSCFG 40

Table 11. AON SYSCONSAIF SYSCFG 40 Register Description
Offset 0x28
Default 0x20
Bit Name Access Default Description
[0] u0_otpc_fl_sec_boot_lmt RO 0x0
[1] u0_otpc_fl_xip RO 0x0
[2] u0_otpc_load_busy RO 0x0
[3] u0_reset_ctrl_clr_reset_status WR 0x0
[4] u0_reset_ctrl_pll_timecnt_finish RO 0x0
[5] u0_reset_ctrl_rstn_sw WR 0x1
[9:6] u0_reset_ctrl_sys_reset_status RO 0x0
[10:31] Reserved None 0x0 Reserved