SYS IOMUX CFG

SYS IOMUX CFGSAIF SYSCFG FMUX 0

The register can be used to configure the selected (Output Enable) OEN signal for GPIO0 - GPIO3.

Table 1. SYS IOMUX CFGSAIF SYSCFG FMUX 0 Register Description
Offset	0x0
Default	0x8010101
Bit	Name	Access	Default	Description
[5:0]	sys_iomux_gpo0_doen_cfg	WR	0x1	The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[6:7]	Reserved	None	0x0	Reserved
[13:8]	sys_iomux_gpo1_doen_cfg	WR	0x1	The selected OEN signal for GPIO1. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[15:14]	Reserved	None	0x0	Reserved
[21:16]	sys_iomux_gpo2_doen_cfg	WR	0x1	The selected OEN signal for GPIO2. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[23:22]	Reserved	None	0x0	Reserved
[24:29]	sys_iomux_gpo3_doen_cfg	WR	0x8	The selected OEN signal for GPIO3. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[30:31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 1

The register can be used to configure the selected (Output Enable) OEN signal for GPIO4 - GPIO7.

Table 2. SYS IOMUX CFGSAIF SYSCFG FMUX 1 Register Description
Offset	0x4
Default	0x10001
Bit	Name	Access	Default	Description
[5:0]	sys_iomux_gpo4_doen_cfg	WR	0x1	The selected OEN signal for GPIO4. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[6:7]	Reserved	None	0x0	Reserved
[13:8]	sys_iomux_gpo5_doen_cfg	WR	0x0	The selected OEN signal for GPIO5. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[15:14]	Reserved	None	0x0	Reserved
[21:16]	sys_iomux_gpo6_doen_cfg	WR	0x1	The selected OEN signal for GPIO6. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[23:22]	Reserved	None	0x0	Reserved
[24:29]	sys_iomux_gpo7_doen_cfg	WR	0x0	The selected OEN signal for GPIO7. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[30:31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 2

The register can be used to configure the selected (Output Enable) OEN signal for GPIO8 - GPIO11.

Table 3. SYS IOMUX CFGSAIF SYSCFG FMUX 2 Register Description
Offset	0x8
Default	0x7010100
Bit	Name	Access	Default	Description
[5:0]	sys_iomux_gpo8_doen_cfg	WR	0x0	The selected OEN signal for GPIO8. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[6:7]	Reserved	None	0x0	Reserved
[13:8]	sys_iomux_gpo9_doen_cfg	WR	0x1	The selected OEN signal for GPIO9. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[15:14]	Reserved	None	0x0	Reserved
[21:16]	sys_iomux_gpo10_doen_cfg	WR	0x1	The selected OEN signal for GPIO10. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[23:22]	Reserved	None	0x0	Reserved
[24:29]	sys_iomux_gpo11_doen_cfg	WR	0x7	The selected OEN signal for GPIO11. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[30:31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 3

The register can be used to configure the selected (Output Enable) OEN signal for GPIO12 - GPIO15.

Table 4. SYS IOMUX CFGSAIF SYSCFG FMUX 3 Register Description
Offset	0xc
Default	0x101
Bit	Name	Access	Default	Description
[5:0]	sys_iomux_gpo12_doen_cfg	WR	0x1	The selected OEN signal for GPIO12. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[6:7]	Reserved	None	0x0	Reserved
[13:8]	sys_iomux_gpo13_doen_cfg	WR	0x1	The selected OEN signal for GPIO13. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[15:14]	Reserved	None	0x0	Reserved
[21:16]	sys_iomux_gpo14_doen_cfg	WR	0x0	The selected OEN signal for GPIO14. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[23:22]	Reserved	None	0x0	Reserved
[24:29]	sys_iomux_gpo15_doen_cfg	WR	0x0	The selected OEN signal for GPIO15. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[30:31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 4

The register can be used to configure the selected (Output Enable) OEN signal for GPIO16 - GPIO19.

Table 5. SYS IOMUX CFGSAIF SYSCFG FMUX 4 Register Description
Offset	0x10
Default	0x1000000
Bit	Name	Access	Default	Description
[5:0]	sys_iomux_gpo16_doen_cfg	WR	0x0	The selected OEN signal for GPIO16. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[6:7]	Reserved	None	0x0	Reserved
[13:8]	sys_iomux_gpo17_doen_cfg	WR	0x0	The selected OEN signal for GPIO17. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[15:14]	Reserved	None	0x0	Reserved
[21:16]	sys_iomux_gpo18_doen_cfg	WR	0x0	The selected OEN signal for GPIO18. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[23:22]	Reserved	None	0x0	Reserved
[24:29]	sys_iomux_gpo19_doen_cfg	WR	0x1	The selected OEN signal for GPIO19. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[30:31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 5

The register can be used to configure the selected (Output Enable) OEN signal for GPIO20 - GPIO23.

Table 6. SYS IOMUX CFGSAIF SYSCFG FMUX 5 Register Description
Offset	0x14
Default	0x0
Bit	Name	Access	Default	Description
[5:0]	sys_iomux_gpo20_doen_cfg	WR	0x0	The selected OEN signal for GPIO20. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[6:7]	Reserved	None	0x0	Reserved
[13:8]	sys_iomux_gpo21_doen_cfg	WR	0x0	The selected OEN signal for GPIO21. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[15:14]	Reserved	None	0x0	Reserved
[21:16]	sys_iomux_gpo22_doen_cfg	WR	0x0	The selected OEN signal for GPIO22. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[23:22]	Reserved	None	0x0	Reserved
[24:29]	sys_iomux_gpo23_doen_cfg	WR	0x0	The selected OEN signal for GPIO23. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[30:31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 6

The register can be used to configure the selected (Output Enable) OEN signal for GPIO24 - GPIO27.

Table 7. SYS IOMUX CFGSAIF SYSCFG FMUX 6 Register Description
Offset	0x18
Default	0x0
Bit	Name	Access	Default	Description
[5:0]	sys_iomux_gpo24_doen_cfg	WR	0x0	The selected OEN signal for GPIO24. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[6:7]	Reserved	None	0x0	Reserved
[13:8]	sys_iomux_gpo25_doen_cfg	WR	0x0	The selected OEN signal for GPIO25. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[15:14]	Reserved	None	0x0	Reserved
[21:16]	sys_iomux_gpo26_doen_cfg	WR	0x0	The selected OEN signal for GPIO26. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[23:22]	Reserved	None	0x0	Reserved
[24:29]	sys_iomux_gpo27_doen_cfg	WR	0x0	The selected OEN signal for GPIO27. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[30:31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 7

The register can be used to configure the selected (Output Enable) OEN signal for GPIO28 - GPIO31.

Table 8. SYS IOMUX CFGSAIF SYSCFG FMUX 7 Register Description
Offset	0x1c
Default	0x0
Bit	Name	Access	Default	Description
[5:0]	sys_iomux_gpo28_doen_cfg	WR	0x0	The selected OEN signal for GPIO28. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[6:7]	Reserved	None	0x0	Reserved
[13:8]	sys_iomux_gpo29_doen_cfg	WR	0x0	The selected OEN signal for GPIO29. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[15:14]	Reserved	None	0x0	Reserved
[21:16]	sys_iomux_gpo30_doen_cfg	WR	0x0	The selected OEN signal for GPIO30. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[23:22]	Reserved	None	0x0	Reserved
[24:29]	sys_iomux_gpo31_doen_cfg	WR	0x0	The selected OEN signal for GPIO31. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[30:31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 8

The register can be used to configure the selected (Output Enable) OEN signal for GPIO32 - GPIO35.

Table 9. SYS IOMUX CFGSAIF SYSCFG FMUX 8 Register Description
Offset	0x20
Default	0x0
Bit	Name	Access	Default	Description
[5:0]	sys_iomux_gpo32_doen_cfg	WR	0x0	The selected OEN signal for GPIO32. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[6:7]	Reserved	None	0x0	Reserved
[13:8]	sys_iomux_gpo33_doen_cfg	WR	0x0	The selected OEN signal for GPIO33. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[15:14]	Reserved	None	0x0	Reserved
[21:16]	sys_iomux_gpo34_doen_cfg	WR	0x0	The selected OEN signal for GPIO34. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[23:22]	Reserved	None	0x0	Reserved
[24:29]	sys_iomux_gpo35_doen_cfg	WR	0x0	The selected OEN signal for GPIO35. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[30:31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 9

The register can be used to configure the selected (Output Enable) OEN signal for GPIO36 - GPIO39.

Table 10. SYS IOMUX CFGSAIF SYSCFG FMUX 9 Register Description
Offset	0x24
Default	0x23220605
Bit	Name	Access	Default	Description
[5:0]	sys_iomux_gpo36_doen_cfg	WR	0x5	The selected OEN signal for GPIO36. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[6:7]	Reserved	None	0x0	Reserved
[13:8]	sys_iomux_gpo37_doen_cfg	WR	0x6	The selected OEN signal for GPIO37. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[15:14]	Reserved	None	0x0	Reserved
[21:16]	sys_iomux_gpo38_doen_cfg	WR	0x22	The selected OEN signal for GPIO38. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[23:22]	Reserved	None	0x0	Reserved
[24:29]	sys_iomux_gpo39_doen_cfg	WR	0x23	The selected OEN signal for GPIO39. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[30:31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 10

The register can be used to configure the selected (Output Enable) OEN signal for GPIO40 - GPIO43.

Table 11. SYS IOMUX CFGSAIF SYSCFG FMUX 10 Register Description
Offset	0x28
Default	0x1000001
Bit	Name	Access	Default	Description
[5:0]	sys_iomux_gpo40_doen_cfg	WR	0x1	The selected OEN signal for GPIO40. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[6:7]	Reserved	None	0x0	Reserved
[13:8]	sys_iomux_gpo41_doen_cfg	WR	0x0	The selected OEN signal for GPIO41. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[15:14]	Reserved	None	0x0	Reserved
[21:16]	sys_iomux_gpo42_doen_cfg	WR	0x0	The selected OEN signal for GPIO42. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[23:22]	Reserved	None	0x0	Reserved
[24:29]	sys_iomux_gpo43_doen_cfg	WR	0x1	The selected OEN signal for GPIO43. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[30:31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 11

The register can be used to configure the selected (Output Enable) OEN signal for GPIO44 - GPIO47.

Table 12. SYS IOMUX CFGSAIF SYSCFG FMUX 11 Register Description
Offset	0x2c
Default	0x1000001
Bit	Name	Access	Default	Description
[5:0]	sys_iomux_gpo44_doen_cfg	WR	0x1	The selected OEN signal for GPIO44. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[6:7]	Reserved	None	0x0	Reserved
[13:8]	sys_iomux_gpo45_doen_cfg	WR	0x0	The selected OEN signal for GPIO45. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[15:14]	Reserved	None	0x0	Reserved
[21:16]	sys_iomux_gpo46_doen_cfg	WR	0x0	The selected OEN signal for GPIO46. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[23:22]	Reserved	None	0x0	Reserved
[24:29]	sys_iomux_gpo47_doen_cfg	WR	0x1	The selected OEN signal for GPIO47. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[30:31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 12

The register can be used to configure the selected (Output Enable) OEN signal for GPIO48 - GPIO51.

Table 13. SYS IOMUX CFGSAIF SYSCFG FMUX 12 Register Description
Offset	0x30
Default	0xe010d0d
Bit	Name	Access	Default	Description
[5:0]	sys_iomux_gpo48_doen_cfg	WR	0xd	The selected OEN signal for GPIO48. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[6:7]	Reserved	None	0x0	Reserved
[13:8]	sys_iomux_gpo49_doen_cfg	WR	0xd	The selected OEN signal for GPIO49. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[15:14]	Reserved	None	0x0	Reserved
[21:16]	sys_iomux_gpo50_doen_cfg	WR	0x1	The selected OEN signal for GPIO50. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[23:22]	Reserved	None	0x0	Reserved
[24:29]	sys_iomux_gpo51_doen_cfg	WR	0xe	The selected OEN signal for GPIO51. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[30:31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 13

The register can be used to configure the selected (Output Enable) OEN signal for GPIO52 - GPIO55.

Table 14. SYS IOMUX CFGSAIF SYSCFG FMUX 13 Register Description
Offset	0x34
Default	0x1d011c1c
Bit	Name	Access	Default	Description
[5:0]	sys_iomux_gpo52_doen_cfg	WR	0x1c	The selected OEN signal for GPIO52. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[6:7]	Reserved	None	0x0	Reserved
[13:8]	sys_iomux_gpo53_doen_cfg	WR	0x1c	The selected OEN signal for GPIO53. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[15:14]	Reserved	None	0x0	Reserved
[21:16]	sys_iomux_gpo54_doen_cfg	WR	0x1	The selected OEN signal for GPIO54. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[23:22]	Reserved	None	0x0	Reserved
[24:29]	sys_iomux_gpo55_doen_cfg	WR	0x1d	The selected OEN signal for GPIO55. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[30:31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 14

The register can be used to configure the selected (Output Enable) OEN signal for GPIO56 - GPIO59.

Table 15. SYS IOMUX CFGSAIF SYSCFG FMUX 14 Register Description
Offset	0x38
Default	0x25012424
Bit	Name	Access	Default	Description
5:0]	sys_iomux_gpo56_doen_cfg	WR	0x24	The selected OEN signal for GPIO56. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[6:7]	Reserved	None	0x0	Reserved
[13:8]	sys_iomux_gpo57_doen_cfg	WR	0x24	The selected OEN signal for GPIO57. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[15:14]	Reserved	None	0x0	Reserved
[21:16]	sys_iomux_gpo58_doen_cfg	WR	0x1	The selected OEN signal for GPIO58. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[23:22]	Reserved	None	0x0	Reserved
[24:29]	sys_iomux_gpo59_doen_cfg	WR	0x25	The selected OEN signal for GPIO59. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[30:31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 15

The register can be used to configure the selected (Output Enable) OEN signal for GPIO60 - GPIO63.

Table 16. SYS IOMUX CFGSAIF SYSCFG FMUX 15 Register Description
Offset	0x3c
Default	0x29012828
Bit	Name	Access	Default	Description
[5:0]	sys_iomux_gpo60_doen_cfg	WR	0x28	The selected OEN signal for GPIO60. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[6:7]	Reserved	None	0x0	Reserved
[13:8]	sys_iomux_gpo61_doen_cfg	WR	0x28	The selected OEN signal for GPIO61. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[15:14]	Reserved	None	0x0	Reserved
[21:16]	sys_iomux_gpo62_doen_cfg	WR	0x1	The selected OEN signal for GPIO62. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[23:22]	Reserved	None	0x0	Reserved
[24:29]	sys_iomux_gpo63_doen_cfg	WR	0x29	The selected OEN signal for GPIO63. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See GPIO OEN List for SYS_IOMUX for more information.
[30:31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 16

The register can be used to configure the selected output signal for GPIO0 - GPIO3.

Table 17. SYS IOMUX CFGSAIF SYSCFG FMUX 16 Register Description
Offset	0x40
Default	0x16000000
Bit	Name	Access	Default	Description
[6:0]	sys_iomux_gpo0_dout_cfg	WR	0x0	The selected output signal for GPIO0. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[7]	Reserved	None	0x0	Reserved
[14:8]	sys_iomux_gpo1_dout_cfg	WR	0x0	The selected output signal for GPIO1. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[15]	Reserved	None	0x0	Reserved
[22:16]	sys_iomux_gpo2_dout_cfg	WR	0x0	The selected output signal for GPIO2. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[23]	Reserved	None	0x0	Reserved
[30:24]	sys_iomux_gpo3_dout_cfg	WR	0x16	The selected output signal for GPIO3. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 17

The register can be used to configure the selected output signal for GPIO4 - GPIO7.

Table 18. SYS IOMUX CFGSAIF SYSCFG FMUX 17 Register Description
Offset	0x44
Default	0x1400
Bit	Name	Access	Default	Description
[6:0]	sys_iomux_gpo4_dout_cfg	WR	0x0	The selected output signal for GPIO4. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[7]	Reserved	None	0x0	Reserved
[14:8]	sys_iomux_gpo5_dout_cfg	WR	0x14	The selected output signal for GPIO5. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[15]	Reserved	None	0x0	Reserved
[22:16]	sys_iomux_gpo6_dout_cfg	WR	0x0	The selected output signal for GPIO6. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[23]	Reserved	None	0x0	Reserved
[30:24]	sys_iomux_gpo7_dout_cfg	WR	0x0	The selected output signal for GPIO7. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 18

The register can be used to configure the selected output signal for GPIO8 - GPIO11.

Table 19. SYS IOMUX CFGSAIF SYSCFG FMUX 18 Register Description
Offset	0x48
Default	0x15000000
Bit	Name	Access	Default	Description
[6:0]	sys_iomux_gpo8_dout_cfg	WR	0x0	The selected output signal for GPIO8. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[7]	Reserved	None	0x0	Reserved
[14:8]	sys_iomux_gpo9_dout_cfg	WR	0x0	The selected output signal for GPIO9. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[15]	Reserved	None	0x0	Reserved
[22:16]	sys_iomux_gpo10_dout_cfg	WR	0x0	The selected output signal for GPIO10. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[23]	Reserved	None	0x0	Reserved
[30:24]	sys_iomux_gpo11_dout_cfg	WR	0x15	The selected output signal for GPIO11. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 19

The register can be used to configure the selected output signal for GPIO12 - GPIO15.

Table 20. SYS IOMUX CFGSAIF SYSCFG FMUX 19 Register Description
Offset	0x4c
Default	0x0
Bit	Name	Access	Default	Description
[6:0]	sys_iomux_gpo12_dout_cfg	WR	0x0	The selected output signal for GPIO12. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[7]	Reserved	None	0x0	Reserved
[14:8]	sys_iomux_gpo13_dout_cfg	WR	0x0	The selected output signal for GPIO13. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[15]	Reserved	None	0x0	Reserved
[22:16]	sys_iomux_gpo14_dout_cfg	WR	0x0	The selected output signal for GPIO14. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[23]	Reserved	None	0x0	Reserved
[30:24]	sys_iomux_gpo15_dout_cfg	WR	0x0	The selected output signal for GPIO15. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 20

The register can be used to configure the selected output signal for GPIO16 - GPIO19.

Table 21. SYS IOMUX CFGSAIF SYSCFG FMUX 20 Register Description
Offset	0x50
Default	0x550000
Bit	Name	Access	Default	Description
[6:0]	sys_iomux_gpo16_dout_cfg	WR	0x0	The selected output signal for GPIO16. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[7]	Reserved	None	0x0	Reserved
[14:8]	sys_iomux_gpo17_dout_cfg	WR	0x0	The selected output signal for GPIO17. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[15]	Reserved	None	0x0	Reserved
[22:16]	sys_iomux_gpo18_dout_cfg	WR	0x55	The selected output signal for GPIO18. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[23]	Reserved	None	0x0	Reserved
[30:24]	sys_iomux_gpo19_dout_cfg	WR	0x0	The selected output signal for GPIO19. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 21

The register can be used to configure the selected output signal for GPIO20 - GPIO23.

Table 22. SYS IOMUX CFGSAIF SYSCFG FMUX 21 Register Description
Offset	0x54
Default	0x0
Bit	Name	Access	Default	Description
[6:0]	sys_iomux_gpo20_dout_cfg	WR	0x0	The selected output signal for GPIO20. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[7]	Reserved	None	0x0	Reserved
[14:8]	sys_iomux_gpo21_dout_cfg	WR	0x0	The selected output signal for GPIO21. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[15]	Reserved	None	0x0	Reserved
[22:16]	sys_iomux_gpo22_dout_cfg	WR	0x0	The selected output signal for GPIO22. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[23]	Reserved	None	0x0	Reserved
[30:24]	sys_iomux_gpo23_dout_cfg	WR	0x0	The selected output signal for GPIO23. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 22

The register can be used to configure the selected output signal for GPIO24 - GPIO27.

Table 23. SYS IOMUX CFGSAIF SYSCFG FMUX 22 Register Description
Offset	0x58
Default	0x0
Bit	Name	Access	Default	Description
[6:0]	sys_iomux_gpo24_dout_cfg	WR	0x0	The selected output signal for GPIO24. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[7]	Reserved	None	0x0	Reserved
[14:8]	sys_iomux_gpo25_dout_cfg	WR	0x0	The selected output signal for GPIO25. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[15]	Reserved	None	0x0	Reserved
[22:16]	sys_iomux_gpo26_dout_cfg	WR	0x0	The selected output signal for GPIO26. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[23]	Reserved	None	0x0	Reserved
[30:24]	sys_iomux_gpo27_dout_cfg	WR	0x0	The selected output signal for GPIO27. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 23

The register can be used to configure the selected output signal for GPIO28 - GPIO31.

Table 24. SYS IOMUX CFGSAIF SYSCFG FMUX 23 Register Description
Offset	0x5c
Default	0x0
Bit	Name	Access	Default	Description
[6:0]	sys_iomux_gpo28_dout_cfg	WR	0x0	The selected output signal for GPIO28. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[7]	Reserved	None	0x0	Reserved
[14:8]	sys_iomux_gpo29_dout_cfg	WR	0x0	The selected output signal for GPIO29. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[15]	Reserved	None	0x0	Reserved
[22:16]	sys_iomux_gpo30_dout_cfg	WR	0x0	The selected output signal for GPIO30. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[23]	Reserved	None	0x0	Reserved
[30:24]	sys_iomux_gpo31_dout_cfg	WR	0x0	The selected output signal for GPIO31. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 24

The register can be used to configure the selected output signal for GPIO32 - GPIO35.

Table 25. SYS IOMUX CFGSAIF SYSCFG FMUX 24 Register Description
Offset	0x60
Default	0xd000000
Bit	Name	Access	Default	Description
[6:0]	sys_iomux_gpo32_dout_cfg	WR	0x0	The selected output signal for GPIO32. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[7]	Reserved	None	0x0	Reserved
[14:8]	sys_iomux_gpo33_dout_cfg	WR	0x0	The selected output signal for GPIO33. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[15]	Reserved	None	0x0	Reserved
[22:16]	sys_iomux_gpo34_dout_cfg	WR	0x0	The selected output signal for GPIO34. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[23]	Reserved	None	0x0	Reserved
[30:24]	sys_iomux_gpo35_dout_cfg	WR	0xd	The selected output signal for GPIO35. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 25

The register can be used to configure the selected output signal for GPIO36 - GPIO39.

Table 26. SYS IOMUX CFGSAIF SYSCFG FMUX 25 Register Description
Offset	0x64
Default	0x54530f0e
Bit	Name	Access	Default	Description
[6:0]	sys_iomux_gpo36_dout_cfg	WR	0xe	The selected output signal for GPIO36. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[7]	Reserved	None	0x0	Reserved
[14:8]	sys_iomux_gpo37_dout_cfg	WR	0xf	The selected output signal for GPIO37. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[15]	Reserved	None	0x0	Reserved
[22:16]	sys_iomux_gpo38_dout_cfg	WR	0x53	The selected output signal for GPIO38. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[23]	Reserved	None	0x0	Reserved
[30:24]	sys_iomux_gpo39_dout_cfg	WR	0x54	The selected output signal for GPIO39. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 26

The register can be used to configure the selected output signal for GPIO40 - GPIO43.

Table 27. SYS IOMUX CFGSAIF SYSCFG FMUX 26 Register Description
Offset	0x68
Default	0x4e4f00
Bit	Name	Access	Default	Description
[6:0]	sys_iomux_gpo40_dout_cfg	WR	0x0	The selected output signal for GPIO40. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[7]	Reserved	None	0x0	Reserved
[14:8]	sys_iomux_gpo41_dout_cfg	WR	0x4f	The selected output signal for GPIO41. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[15]	Reserved	None	0x0	Reserved
[22:16]	sys_iomux_gpo42_dout_cfg	WR	0x4e	The selected output signal for GPIO42. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[23]	Reserved	None	0x0	Reserved
[30:24]	sys_iomux_gpo43_dout_cfg	WR	0x0	The selected output signal for GPIO43. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 27

The register can be used to configure the selected output signal for GPIO44 - GPIO47.

Table 28. SYS IOMUX CFGSAIF SYSCFG FMUX 27 Register Description
Offset	0x6c
Default	0x5b5c00
Bit	Name	Access	Default	Description
[6:0]	sys_iomux_gpo44_dout_cfg	WR	0x0	The selected output signal for GPIO44. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[7]	Reserved	None	0x0	Reserved
[14:8]	sys_iomux_gpo45_dout_cfg	WR	0x5c	The selected output signal for GPIO45. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[15]	Reserved	None	0x0	Reserved
[22:16]	sys_iomux_gpo46_dout_cfg	WR	0x5b	The selected output signal for GPIO46. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[23]	Reserved	None	0x0	Reserved
[30:24]	sys_iomux_gpo47_dout_cfg	WR	0x0	The selected output signal for GPIO47. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 28

The register can be used to configure the selected output signal for GPIO48 - GPIO51.

Table 29. SYS IOMUX CFGSAIF SYSCFG FMUX 28 Register Description
Offset	0x70
Default	0x20001e1f
Bit	Name	Access	Default	Description
[6:0]	sys_iomux_gpo48_dout_cfg	WR	0x1f	The selected output signal for GPIO48. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[7]	Reserved	None	0x0	Reserved
[14:8]	sys_iomux_gpo49_dout_cfg	WR	0x1e	The selected output signal for GPIO49. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[15]	Reserved	None	0x0	Reserved
[22:16]	sys_iomux_gpo50_dout_cfg	WR	0x0	The selected output signal for GPIO50. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[23]	Reserved	None	0x0	Reserved
[30:24]	sys_iomux_gpo51_dout_cfg	WR	0x20	The selected output signal for GPIO51. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 29

The register can be used to configure the selected output signal for GPIO52 - GPIO55.

Table 30. SYS IOMUX CFGSAIF SYSCFG FMUX 29 Register Description
Offset	0x74
Default	0x4b00494a
Bit	Name	Access	Default	Description
[6:0]	sys_iomux_gpo52_dout_cfg	WR	0x4a	The selected output signal for GPIO52. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[7]	Reserved	None	0x0	Reserved
[14:8]	sys_iomux_gpo53_dout_cfg	WR	0x49	The selected output signal for GPIO53. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[15]	Reserved	None	0x0	Reserved
[22:16]	sys_iomux_gpo54_dout_cfg	WR	0x0	The selected output signal for GPIO54. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[23]	Reserved	None	0x0	Reserved
[30:24]	sys_iomux_gpo55_dout_cfg	WR	0x4b	The selected output signal for GPIO55. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 30

The register can be used to configure the selected output signal for GPIO56 - GPIO59.

Table 31. SYS IOMUX CFGSAIF SYSCFG FMUX 30 Register Description
Offset	0x78
Default	0x58005657
Bit	Name	Access	Default	Description
[6:0]	sys_iomux_gpo56_dout_cfg	WR	0x57	The selected output signal for GPIO56. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[7]	Reserved	None	0x0	Reserved
[14:8]	sys_iomux_gpo57_dout_cfg	WR	0x56	The selected output signal for GPIO57. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[15]	Reserved	None	0x0	Reserved
[22:16]	sys_iomux_gpo58_dout_cfg	WR	0x0	The selected output signal for GPIO58. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[23]	Reserved	None	0x0	Reserved
[30:24]	sys_iomux_gpo59_dout_cfg	WR	0x58	The selected output signal for GPIO59. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 31

The register can be used to configure the selected output signal for GPIO60 - GPIO63.

Table 32. SYS IOMUX CFGSAIF SYSCFG FMUX 31 Register Description
Offset	0x7c
Default	0x5f005d5e
Bit	Name	Access	Default	Description
[6:0]	sys_iomux_gpo60_dout_cfg	WR	0x5e	The selected output signal for GPIO60. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[7]	Reserved	None	0x0	Reserved
[14:8]	sys_iomux_gpo61_dout_cfg	WR	0x5d	The selected output signal for GPIO61. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[15]	Reserved	None	0x0	Reserved
[22:16]	sys_iomux_gpo62_dout_cfg	WR	0x0	The selected output signal for GPIO62. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[23]	Reserved	None	0x0	Reserved
[30:24]	sys_iomux_gpo63_dout_cfg	WR	0x5f	The selected output signal for GPIO63. The register value indicates the selected GPIO output signal index from GPIO output signal list 0-107. See GPIO OEN List for SYS_IOMUX for more information.
[31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 32

The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "sys_iomux_gpi_u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals for a complete list of the input GPIO signals.

Table 33. SYS IOMUX CFGSAIF SYSCFG FMUX 32 Register Description
Offset	0x80
Default	0x0
Bit	Name	Access	Default	Description
[6:0]	sys_iomux_gpi_u0_WAVE511_i_uart_rxsin_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[7]	Reserved	None	0x0	Reserved
[14:8]	sys_iomux_gpi_u0_can_ctrl_rxd_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[15]	Reserved	None	0x0	Reserved
[22:16]	sys_iomux_gpi_u0_cdn_usb_overcurrent_n_io_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[23]	Reserved	None	0x0	Reserved
[30:24]	sys_iomux_gpi_u0_cdns_spdif_spdifi_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 33

The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "sys_iomux_gpi_u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals for a complete list of the input GPIO signals.

Table 34. SYS IOMUX CFGSAIF SYSCFG FMUX 33 Register Description
Offset	0x84
Default	0x2
Bit	Name	Access	Default	Description
[6:0]	sys_iomux_gpi_u0_clkrst_src_bypass_jtag_trstn_cfg	WR	0x2	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[7]	Reserved	None	0x0	Reserved
[14:8]	sys_iomux_gpi_u0_dom_vout_top_u0_hdmi_tx_pin_cec_sda_in_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[15]	Reserved	None	0x0	Reserved
[22:16]	sys_iomux_gpi_u0_dom_vout_top_u0_hdmi_tx_pin_ddc_scl_in_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[23]	Reserved	None	0x0	Reserved
[30:24]	sys_iomux_gpi_u0_dom_vout_top_u0_hdmi_tx_pin_ddc_sda_in_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 34

The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "sys_iomux_gpi_u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals for a complete list of the input GPIO signals.

Table 35. SYS IOMUX CFGSAIF SYSCFG FMUX 34 Register Description
Offset	0x88
Default	0x272600
Bit	Name	Access	Default	Description
[6:0]	sys_iomux_gpi_u0_dom_vout_top_u0_hdmi_tx_pin_hpd_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[7]	Reserved	None	0x0	Reserved
[14:8]	sys_iomux_gpi_u0_i2c_ic_clk_in_a_cfg	WR	0x26	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[15]	Reserved	None	0x0	Reserved
[22:16]	sys_iomux_gpi_u0_i2c_ic_data_in_a_cfg	WR	0x27	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[23]	Reserved	None	0x0	Reserved
[30:24]	sys_iomux_gpi_u0_sdio_card_detect_n_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 35

The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "sys_iomux_gpi_u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals for a complete list of the input GPIO signals.

Table 36. SYS IOMUX CFGSAIF SYSCFG FMUX 35 Register Description
Offset	0x8c
Default	0xb080000
Bit	Name	Access	Default	Description
[6:0]	sys_iomux_gpi_u0_sdio_card_int_n_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[7]	Reserved	None	0x0	Reserved
[14:8]	sys_iomux_gpi_u0_sdio_card_write_prt_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[15]	Reserved	None	0x0	Reserved
[22:16]	sys_iomux_gpi_u0_uart_sin_cfg	WR	0x8	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[23]	Reserved	None	0x0	Reserved
[30:24]	sys_iomux_gpi_u0_hifi4_JTCK_cfg	WR	0xb	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 36

The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "sys_iomux_gpi_u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals for a complete list of the input GPIO signals.

Table 37. SYS IOMUX CFGSAIF SYSCFG FMUX 36 Register Description
Offset	0x90
Default	0x40f0e0c
Bit	Name	Access	Default	Description
[6:0]	sys_iomux_gpi_u0_hifi4_JTDI_cfg	WR	0xc	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[7]	Reserved	None	0x0	Reserved
[14:8]	sys_iomux_gpi_u0_hifi4_JTMS_cfg	WR	0xe	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[15]	Reserved	None	0x0	Reserved
[22:16]	sys_iomux_gpi_u0_hifi4_JTRSTn_cfg	WR	0xf	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[23]	Reserved	None	0x0	Reserved
[30:24]	sys_iomux_gpi_u0_jtag_certification_tdi_cfg	WR	0x4	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 37

The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "sys_iomux_gpi_u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals for a complete list of the input GPIO signals.

Table 38. SYS IOMUX CFGSAIF SYSCFG FMUX 37 Register Description
Offset	0x94
Default	0x6
Bit	Name	Access	Default	Description
[6:0]	sys_iomux_gpi_u0_jtag_certification_tms_cfg	WR	0x6	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[7]	Reserved	None	0x0	Reserved
[14:8]	sys_iomux_gpi_u0_pdm_4mic_dmic0_din_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[15]	Reserved	None	0x0	Reserved
[22:16]	sys_iomux_gpi_u0_pdm_4mic_dmic1_din_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[23]	Reserved	None	0x0	Reserved
[30:24]	sys_iomux_gpi_u0_saif_audio_sdin_mux_i2srx_ext_sdin0_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 38

The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "sys_iomux_gpi_u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals for a complete list of the input GPIO signals.

Table 39. SYS IOMUX CFGSAIF SYSCFG FMUX 38 Register Description
Offset	0x98
Default	0x32330000
Bit	Name	Access	Default	Description
[6:0]	sys_iomux_gpi_u0_saif_audio_sdin_mux_i2srx_ext_sdin1_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[7]	Reserved	None	0x0	Reserved
[14:8]	sys_iomux_gpi_u0_saif_audio_sdin_mux_i2srx_ext_sdin2_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[15]	Reserved	None	0x0	Reserved
[22:16]	sys_iomux_gpi_u0_ssp_spi_SSPCLKIN_cfg	WR	0x33	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[23]	Reserved	None	0x0	Reserved
[30:24]	sys_iomux_gpi_u0_ssp_spi_SSPFSSIN_cfg	WR	0x32	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 39

The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "sys_iomux_gpi_u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals for a complete list of the input GPIO signals.

Table 40. SYS IOMUX CFGSAIF SYSCFG FMUX 39 Register Description
Offset	0x9c
Default	0x334
Bit	Name	Access	Default	Description
[6:0]	sys_iomux_gpi_u0_ssp_spi_SSPRXD_cfg	WR	0x34	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[7]	Reserved	None	0x0	Reserved
[14:8]	sys_iomux_gpi_u0_sys_crg_clk_jtag_tck_cfg	WR	0x3	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[15]	Reserved	None	0x0	Reserved
[22:16]	sys_iomux_gpi_u0_sys_crg_ext_mclk_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[23]	Reserved	None	0x0	Reserved
[30:24]	sys_iomux_gpi_u0_sys_crg_i2srx_bclk_slv_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 40

The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "sys_iomux_gpi_u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals for a complete list of the input GPIO signals.

Table 41. SYS IOMUX CFGSAIF SYSCFG FMUX 40 Register Description
Offset	0xa0
Default	0x0
Bit	Name	Access	Default	Description
[6:0]	sys_iomux_gpi_u0_sys_crg_i2srx_lrck_slv_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[7]	Reserved	None	0x0	Reserved
[14:8]	sys_iomux_gpi_u0_sys_crg_i2stx_bclk_slv_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[15]	Reserved	None	0x0	Reserved
[22:16]	sys_iomux_gpi_u0_sys_crg_i2stx_lrck_slv_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[23]	Reserved	None	0x0	Reserved
[30:24]	sys_iomux_gpi_u0_sys_crg_tdm_clk_slv_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 41

The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "sys_iomux_gpi_u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals for a complete list of the input GPIO signals.

Table 42. SYS IOMUX CFGSAIF SYSCFG FMUX 41 Register Description
Offset	0xa4
Default	0x0
Bit	Name	Access	Default	Description
[6:0]	sys_iomux_gpi_u0_tdm16slot_PCM_RXD_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[7]	Reserved	None	0x0	Reserved
[14:8]	sys_iomux_gpi_u0_tdm16slot_PCM_SYNCIN_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[15]	Reserved	None	0x0	Reserved
[22:16]	sys_iomux_gpi_u1_can_ctrl_rxd_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[23]	Reserved	None	0x0	Reserved
[30:24]	sys_iomux_gpi_u1_i2c_ic_clk_in_a_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 42

The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "sys_iomux_gpi_u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals for a complete list of the input GPIO signals.

Table 43. SYS IOMUX CFGSAIF SYSCFG FMUX 42 Register Description
Offset	0xa8
Default	0x0
Bit	Name	Access	Default	Description
[6:0]	sys_iomux_gpi_u1_i2c_ic_data_in_a_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[7]	Reserved	None	0x0	Reserved
[14:8]	sys_iomux_gpi_u1_sdio_card_detect_n_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[15]	Reserved	None	0x0	Reserved
[22:16]	sys_iomux_gpi_u1_sdio_card_int_n_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[23]	Reserved	None	0x0	Reserved
[30:24]	sys_iomux_gpi_u1_sdio_card_write_prt_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 43

The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "sys_iomux_gpi_u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals for a complete list of the input GPIO signals.

Table 44. SYS IOMUX CFGSAIF SYSCFG FMUX 43 Register Description
Offset	0xac
Default	0x0
Bit	Name	Access	Default	Description
[6:0]	sys_iomux_gpi_u1_sdio_ccmd_in_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[7]	Reserved	None	0x0	Reserved
[14:8]	sys_iomux_gpi_u1_sdio_cdata_in_0_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[15]	Reserved	None	0x0	Reserved
[22:16]	sys_iomux_gpi_u1_sdio_cdata_in_1_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[23]	Reserved	None	0x0	Reserved
[30:24]	sys_iomux_gpi_u1_sdio_cdata_in_2_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 44

The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "sys_iomux_gpi_u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals for a complete list of the input GPIO signals.

Table 45. SYS IOMUX CFGSAIF SYSCFG FMUX 44 Register Description
Offset	0xb0
Default	0x0
Bit	Name	Access	Default	Description
[6:0]	sys_iomux_gpi_u1_sdio_cdata_in_3_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[7]	Reserved	None	0x0	Reserved
[14:8]	sys_iomux_gpi_u1_sdio_cdata_in_4_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[15]	Reserved	None	0x0	Reserved
[22:16]	sys_iomux_gpi_u1_sdio_cdata_in_5_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[23]	Reserved	None	0x0	Reserved
[30:24]	sys_iomux_gpi_u1_sdio_cdata_in_6_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 45

The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "sys_iomux_gpi_u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals for a complete list of the input GPIO signals.

Table 46. SYS IOMUX CFGSAIF SYSCFG FMUX 45 Register Description
Offset	0xb4
Default	0x0
Bit	Name	Access	Default	Description
[6:0]	sys_iomux_gpi_u1_sdio_cdata_in_7_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[7]	Reserved	None	0x0	Reserved
[14:8]	sys_iomux_gpi_u1_sdio_data_strobe_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[15]	Reserved	None	0x0	Reserved
[22:16]	sys_iomux_gpi_u1_uart_cts_n_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[23]	Reserved	None	0x0	Reserved
[30:24]	sys_iomux_gpi_u1_uart_sin_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 46

The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "sys_iomux_gpi_u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals for a complete list of the input GPIO signals.

Table 47. SYS IOMUX CFGSAIF SYSCFG FMUX 46 Register Description
Offset	0xb8
Default	0x383637
Bit	Name	Access	Default	Description
[6:0]	sys_iomux_gpi_u1_ssp_spi_SSPCLKIN_cfg	WR	0x37	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[7]	Reserved	None	0x0	Reserved
[14:8]	sys_iomux_gpi_u1_ssp_spi_SSPFSSIN_cfg	WR	0x36	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[15]	Reserved	None	0x0	Reserved
[22:16]	sys_iomux_gpi_u1_ssp_spi_SSPRXD_cfg	WR	0x38	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[23]	Reserved	None	0x0	Reserved
[30:24]	sys_iomux_gpi_u2_i2c_ic_clk_in_a_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 47

The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "sys_iomux_gpi_u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals for a complete list of the input GPIO signals.

Table 48. SYS IOMUX CFGSAIF SYSCFG FMUX 47 Register Description
Offset	0xbc
Default	0x2a2d00
Bit	Name	Access	Default	Description
[6:0]	sys_iomux_gpi_u2_i2c_ic_data_in_a_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[7]	Reserved	None	0x0	Reserved
[14:8]	sys_iomux_gpi_u2_uart_cts_n_cfg	WR	0x2d	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[15]	Reserved	None	0x0	Reserved
[22:16]	sys_iomux_gpi_u2_uart_sin_cfg	WR	0x2a	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[23]	Reserved	None	0x0	Reserved
[30:24]	sys_iomux_gpi_u2_ssp_spi_SSPCLKIN_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 48

The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "sys_iomux_gpi_u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals for a complete list of the input GPIO signals.

Table 49. SYS IOMUX CFGSAIF SYSCFG FMUX 48 Register Description
Offset	0xc0
Default	0x29280000
Bit	Name	Access	Default	Description
[6:0]	sys_iomux_gpi_u2_ssp_spi_SSPFSSIN_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[7]	Reserved	None	0x0	Reserved
[14:8]	sys_iomux_gpi_u2_ssp_spi_SSPRXD_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[15]	Reserved	None	0x0	Reserved
[22:16]	sys_iomux_gpi_u3_i2c_ic_clk_in_a_cfg	WR	0x28	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[23]	Reserved	None	0x0	Reserved
[30:24]	sys_iomux_gpi_u3_i2c_ic_data_in_a_cfg	WR	0x29	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 49

The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "sys_iomux_gpi_u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals for a complete list of the input GPIO signals.

Table 50. SYS IOMUX CFGSAIF SYSCFG FMUX 49 Register Description
Offset	0xc4
Default	0x3c3a3b15
Bit	Name	Access	Default	Description
[6:0]	sys_iomux_gpi_u3_uart_sin_cfg	WR	0x15	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[7]	Reserved	None	0x0	Reserved
[14:8]	sys_iomux_gpi_u3_ssp_spi_SSPCLKIN_cfg	WR	0x3b	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[15]	Reserved	None	0x0	Reserved
[22:16]	sys_iomux_gpi_u3_ssp_spi_SSPFSSIN_cfg	WR	0x3a	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[23]	Reserved	None	0x0	Reserved
[30:24]	sys_iomux_gpi_u3_ssp_spi_SSPRXD_cfg	WR	0x3c	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 50

The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "sys_iomux_gpi_u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals for a complete list of the input GPIO signals.

Table 51. SYS IOMUX CFGSAIF SYSCFG FMUX 50 Register Description
Offset	0xc8
Default	0x2e310000
Bit	Name	Access	Default	Description
[6:0]	sys_iomux_gpi_u4_i2c_ic_clk_in_a_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[7]	Reserved	None	0x0	Reserved
[14:8]	sys_iomux_gpi_u4_i2c_ic_data_in_a_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[15]	Reserved	None	0x0	Reserved
[22:16]	sys_iomux_gpi_u4_uart_cts_n_cfg	WR	0x31	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[23]	Reserved	None	0x0	Reserved
[30:24]	sys_iomux_gpi_u4_uart_sin_cfg	WR	0x2e	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 51

The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "sys_iomux_gpi_u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals for a complete list of the input GPIO signals.

Table 52. SYS IOMUX CFGSAIF SYSCFG FMUX 51 Register Description
Offset	0xcc
Default	0x403e3f
Bit	Name	Access	Default	Description
[6:0]	sys_iomux_gpi_u4_ssp_spi_SSPCLKIN_cfg	WR	0x3f	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[7]	Reserved	None	0x0	Reserved
[14:8]	sys_iomux_gpi_u4_ssp_spi_SSPFSSIN_cfg	WR	0x3e	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[15]	Reserved	None	0x0	Reserved
[22:16]	sys_iomux_gpi_u4_ssp_spi_SSPRXD_cfg	WR	0x40	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[23]	Reserved	None	0x0	Reserved
[30:24]	sys_iomux_gpi_u5_i2c_ic_clk_in_a_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 52

The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "sys_iomux_gpi_u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals for a complete list of the input GPIO signals.

Table 53. SYS IOMUX CFGSAIF SYSCFG FMUX 52 Register Description
Offset	0xd0
Default	0x0
Bit	Name	Access	Default	Description
[6:0]	sys_iomux_gpi_u5_i2c_ic_data_in_a_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[7]	Reserved	None	0x0	Reserved
[14:8]	sys_iomux_gpi_u5_uart_cts_n_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[15]	Reserved	None	0x0	Reserved
[22:16]	sys_iomux_gpi_u5_uart_sin_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[23]	Reserved	None	0x0	Reserved
[30:24]	sys_iomux_gpi_u5_ssp_spi_SSPCLKIN_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 53

The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "sys_iomux_gpi_u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals for a complete list of the input GPIO signals.

Table 54. SYS IOMUX CFGSAIF SYSCFG FMUX 53 Register Description
Offset	0xd4
Default	0x0
Bit	Name	Access	Default	Description
[6:0]	sys_iomux_gpi_u5_ssp_spi_SSPFSSIN_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[7]	Reserved	None	0x0	Reserved
[14:8]	sys_iomux_gpi_u5_ssp_spi_SSPRXD_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[15]	Reserved	None	0x0	Reserved
[22:16]	sys_iomux_gpi_u6_i2c_ic_clk_in_a_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[23]	Reserved	None	0x0	Reserved
[30:24]	sys_iomux_gpi_u6_i2c_ic_data_in_a_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG FMUX 54

The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "sys_iomux_gpi_u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals for a complete list of the input GPIO signals.

Table 55. SYS IOMUX CFGSAIF SYSCFG FMUX 54 Register Description
Offset	0xd8
Default	0x0
Bit	Name	Access	Default	Description
[6:0]	sys_iomux_gpi_u6_ssp_spi_SSPCLKIN_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[7]	Reserved	None	0x0	Reserved
[14:8]	sys_iomux_gpi_u6_ssp_spi_SSPFSSIN_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[15]	Reserved	None	0x0	Reserved
[22:16]	sys_iomux_gpi_u6_ssp_spi_SSPRXD_cfg	WR	0x0	The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal.
[31:23]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG IOIRQ 55

Table 56. SYS IOMUX CFGSAIF SYSCFG IOIRQ 55 Register Description
Offset	0xdc
Default	0x0
Bit	Name	Access	Default	Description
[0]	sys_gpioen_0_reg	WR	0x0	Enable GPIO IRQ function
[1:31]	Reserved	None	0x0	Reserved

SYS IOMUX CFGSAIF SYSCFG IOIRQ 56

Table 57. SYS IOMUX CFGSAIF SYSCFG IOIRQ 56 Register Description
Offset	0xe0
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	sys_gpiois_0_reg	WR	0x0	1: Edge trigger 0: Level trigger

SYS IOMUX CFGSAIF SYSCFG IOIRQ 57

Table 58. SYS IOMUX CFGSAIF SYSCFG IOIRQ 57 Register Description
Offset	0xe4
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	sys_gpiois_1_reg	WR	0x0	1: Edge trigger 0: Level trigger

SYS IOMUX CFGSAIF SYSCFG IOIRQ 58

Table 59. SYS IOMUX CFGSAIF SYSCFG IOIRQ 58 Register Description
Offset	0xe8
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	sys_gpioic_0_reg	WR	0x0	Do not clear the register Clear the register

Note: You can also write 0 and 1 sequentially to clear edge IRQ.

SYS IOMUX CFGSAIF SYSCFG IOIRQ 59

Table 60. SYS IOMUX CFGSAIF SYSCFG IOIRQ 59 Register Description
Offset	0xec
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	sys_gpioic_1_reg	WR	0x0	Do not clear the register Clear the register

Note: You can also write 0 and 1 sequentially to clear edge IRQ.

SYS IOMUX CFGSAIF SYSCFG IOIRQ 60

Table 61. SYS IOMUX CFGSAIF SYSCFG IOIRQ 60 Register Description
Offset	0xf0
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	sys_gpioibe_0_reg	WR	0x0	Trigger on both edges Trigger on a single edge

SYS IOMUX CFGSAIF SYSCFG IOIRQ 61

Table 62. SYS IOMUX CFGSAIF SYSCFG IOIRQ 61 Register Description
Offset	0xf4
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	sys_gpioibe_1_reg	WR	0x0	Trigger on both edges Trigger on a single edge

SYS IOMUX CFGSAIF SYSCFG IOIRQ 62

Table 63. SYS IOMUX CFGSAIF SYSCFG IOIRQ 62 Register Description
Offset	0xf8
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	sys_gpioiev_0_reg	WR	0x0	1: Positive/Low 0: Negative/High

SYS IOMUX CFGSAIF SYSCFG IOIRQ 63

Table 64. SYS IOMUX CFGSAIF SYSCFG IOIRQ 63 Register Description
Offset	0xfc
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	sys_gpioiev_1_reg	WR	0x0	1: Positive/Low 0: Negative/High

SYS IOMUX CFGSAIF SYSCFG IOIRQ 64

Table 65. SYS IOMUX CFGSAIF SYSCFG IOIRQ 64 Register Description
Offset	0x100
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	sys_gpioie_0_reg	WR	0x0	1: Unmask 0: Mask

SYS IOMUX CFGSAIF SYSCFG IOIRQ 65

Table 66. SYS IOMUX CFGSAIF SYSCFG IOIRQ 65 Register Description
Offset	0x104
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	sys_gpioie_1_reg	WR	0x0	1: Unmask 0: Mask

SYS IOMUX CFGSAIF SYSCFG IOIRQ 66

Table 67. SYS IOMUX CFGSAIF SYSCFG IOIRQ 66 Register Description
Offset	0x108
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	sys_gpioris_0_reg	RO	0x0	Status of the edge trigger. The register can be cleared by writing gpio ic.

SYS IOMUX CFGSAIF SYSCFG IOIRQ 67

Table 68. SYS IOMUX CFGSAIF SYSCFG IOIRQ 67 Register Description
Offset	0x10c
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	sys_gpioris_1_reg	RO	0x0	Status of the edge trigger. The register can be cleared by writing gpio ic.

SYS IOMUX CFGSAIF SYSCFG IOIRQ 68

Table 69. SYS IOMUX CFGSAIF SYSCFG IOIRQ 68 Register Description
Offset	0x110
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	sys_gpiomis_0_reg	RO	0x0	The masked GPIO IRQ status

SYS IOMUX CFGSAIF SYSCFG IOIRQ 69

Table 70. SYS IOMUX CFGSAIF SYSCFG IOIRQ 69 Register Description
Offset	0x114
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	sys_gpiomis_1_reg	RO	0x0	The masked GPIO IRQ status

SYS IOMUX CFGSAIF SYSCFG IOIRQ 70

Table 71. SYS IOMUX CFGSAIF SYSCFG IOIRQ 70 Register Description
Offset	0x118
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	sys_gpio_in_sync2_0_reg	RO	0x0	Status of the gpio_in after synchronization

SYS IOMUX CFGSAIF SYSCFG IOIRQ 71

Table 72. SYS IOMUX CFGSAIF SYSCFG IOIRQ 71 Register Description
Offset	0x11c
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	sys_gpio_in_sync2_1_reg	RO	0x0	Status of the gpio_in after synchronization

SYS IOMUX CFG SAIF SYSCFG 288

The register can be used to configure the core settings of system signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, "PADCFG_PAD_GPIO0_IE" indicates the attribute "IE" of the signal "GPIO0". See Signal Description for a complete list of the system signals.

Table 73. SYS IOMUX CFG SAIF SYSCFG 288 Register Description
Offset	0x120
Default	0x11
Bit	Name	Access	Default	Description
[0]	PADCFG_PAD_GPIO0_IE	WR	0x1	Input Enable (IE) Controller: 1: Enable the receiver 0: Disable the receiver
[1:2]	PADCFG_PAD_GPIO0_DS	WR	0x0	Output Drive Strength (DS): 00: The rated drive strength is 2 mA. 01: The rated drive strength is 4 mA. 10: The rated drive strength is 8 mA. 01: The rated drive strength is 12 mA.
[3]	PADCFG_PAD_GPIO0_PU	WR	0x0	Pull-Up (PU) settings: 1: Yes 0: No
[4]	PADCFG_PAD_GPIO0_PD	WR	0x1	Pull-Down (PD) settings: 1: Yes 0: No
[5]	PADCFG_PAD_GPIO0_SLEW	WR	0x0	Slew Rate Control: 0: Slow (Half frequency) 1: Fast
[6]	PADCFG_PAD_GPIO0_SMT	WR	0x0	Active high Schmitt (SMT) trigger selector: 0: No hysteresis 1: Schmitt trigger enabled
[7]	PADCFG_PAD_GPIO0_POS	WR	0x0	Power-on-Start (POS) enabler: 1: Enable active pull down for loss of core power 0: Active pull-down capability disabled
[8:31]	Reserved	None	0x0	Reserved

SYS IOMUX CFG SAIF SYSCFG 292

The register can be used to configure the core settings of system signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, "PADCFG_PAD_GPIO0_IE" indicates the attribute "IE" of the signal "GPIO0". See Signal Description for a complete list of the system signals.

Table 74. SYS IOMUX CFG SAIF SYSCFG 292 Register Description
Offset	0x124
Default	0x9
Bit	Name	Access	Default	Description
[0]	PADCFG_PAD_GPIO1_IE	WR	0x1	Input Enable (IE) Controller: 1: Enable the receiver 0: Disable the receiver
[1:2]	PADCFG_PAD_GPIO1_DS	WR	0x0	Output Drive Strength (DS): 00: The rated drive strength is 2 mA. 01: The rated drive strength is 4 mA. 10: The rated drive strength is 8 mA. 01: The rated drive strength is 12 mA.
[3]	PADCFG_PAD_GPIO1_PU	WR	0x1	Pull-Up (PU) settings: 1: Yes 0: No
[4]	PADCFG_PAD_GPIO1_PD	WR	0x0	Pull-Down (PD) settings: 1: Yes 0: No
[5]	PADCFG_PAD_GPIO1_SLEW	WR	0x0	Slew Rate Control: 0: Slow (Half frequency) 1: Fast
[6]	PADCFG_PAD_GPIO1_SMT	WR	0x0	Active high Schmitt (SMT) trigger selector: 0: No hysteresis 1: Schmitt trigger enabled
[7]	PADCFG_PAD_GPIO1_POS	WR	0x0	Power-on-Start (POS) enabler: 1: Enable active pull down for loss of core power 0: Active pull-down capability disabled
[8:31]	Reserved	None	0x0	Reserved

SYS IOMUX CFG SAIF SYSCFG 296

The register can be used to configure the core settings of system signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, "PADCFG_PAD_GPIO0_IE" indicates the attribute "IE" of the signal "GPIO0". See Signal Description for a complete list of the system signals.

Table 75. SYS IOMUX CFG SAIF SYSCFG 296 Register Description
Offset	0x128
Default	0x1
Bit	Name	Access	Default	Description
[0]	PADCFG_PAD_GPIO2_IE	WR	0x1	Input Enable (IE) Controller: 1: Enable the receiver 0: Disable the receiver
[1:2]	PADCFG_PAD_GPIO2_DS	WR	0x0	Output Drive Strength (DS): 00: The rated drive strength is 2 mA. 01: The rated drive strength is 4 mA. 10: The rated drive strength is 8 mA. 01: The rated drive strength is 12 mA.
[3]	PADCFG_PAD_GPIO2_PU	WR	0x0	Pull-Up (PU) settings: 1: Yes 0: No
[4]	PADCFG_PAD_GPIO2_PD	WR	0x0	Pull-Down (PD) settings: 1: Yes 0: No
[5]	PADCFG_PAD_GPIO2_SLEW	WR	0x0	Slew Rate Control: 0: Slow (Half frequency) 1: Fast
[6]	PADCFG_PAD_GPIO2_SMT	WR	0x0	Active high Schmitt (SMT) trigger selector: 0: No hysteresis 1: Schmitt trigger enabled
[7]	PADCFG_PAD_GPIO2_POS	WR	0x0	Power-on-Start (POS) enabler: 1: Enable active pull down for loss of core power 0: Active pull-down capability disabled
[8:31]	Reserved	None	0x0	Reserved

SYS IOMUX CFG SAIF SYSCFG 300

The register can be used to configure the core settings of system signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, "PADCFG_PAD_GPIO0_IE" indicates the attribute "IE" of the signal "GPIO0". See Signal Description for a complete list of the system signals.

Table 76. SYS IOMUX CFG SAIF SYSCFG 300 Register Description
Offset	0x12c
Default	0x1
Bit	Name	Access	Default	Description
[0]	PADCFG_PAD_GPIO3_IE	WR	0x1	Input Enable (IE) Controller: 1: Enable the receiver 0: Disable the receiver
[1:2]	PADCFG_PAD_GPIO3_DS	WR	0x0	Output Drive Strength (DS): 00: The rated drive strength is 2 mA. 01: The rated drive strength is 4 mA. 10: The rated drive strength is 8 mA. 01: The rated drive strength is 12 mA.
[3]	PADCFG_PAD_GPIO3_PU	WR	0x0	Pull-Up (PU) settings: 1: Yes 0: No
[4]	PADCFG_PAD_GPIO3_PD	WR	0x0	Pull-Down (PD) settings: 1: Yes 0: No
[5]	PADCFG_PAD_GPIO3_SLEW	WR	0x0	Slew Rate Control: 0: Slow (Half frequency) 1: Fast
[6]	PADCFG_PAD_GPIO3_SMT	WR	0x0	Active high Schmitt (SMT) trigger selector: 0: No hysteresis 1: Schmitt trigger enabled
[7]	PADCFG_PAD_GPIO3_POS	WR	0x0	Power-on-Start (POS) enabler: 1: Enable active pull down for loss of core power 0: Active pull-down capability disabled
[8:31]	Reserved	None	0x0	Reserved

SYS IOMUX CFG SAIF SYSCFG 304

The register can be used to configure the core settings of system signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, "PADCFG_PAD_GPIO0_IE" indicates the attribute "IE" of the signal "GPIO0". See Signal Description for a complete list of the system signals.

Table 77. SYS IOMUX CFG SAIF SYSCFG 304 Register Description
Offset	0x130
Default	0x9
Bit	Name	Access	Default	Description
[0]	PADCFG_PAD_GPIO4_IE	WR	0x1	Input Enable (IE) Controller: 1: Enable the receiver 0: Disable the receiver
[1:2]	PADCFG_PAD_GPIO4_DS	WR	0x0	Output Drive Strength (DS): 00: The rated drive strength is 2 mA. 01: The rated drive strength is 4 mA. 10: The rated drive strength is 8 mA. 01: The rated drive strength is 12 mA.
[3]	PADCFG_PAD_GPIO4_PU	WR	0x1	Pull-Up (PU) settings: 1: Yes 0: No
[4]	PADCFG_PAD_GPIO4_PD	WR	0x0	Pull-Down (PD) settings: 1: Yes 0: No
[5]	PADCFG_PAD_GPIO4_SLEW	WR	0x0	Slew Rate Control: 0: Slow (Half frequency) 1: Fast
[6]	PADCFG_PAD_GPIO4_SMT	WR	0x0	Active high Schmitt (SMT) trigger selector: 0: No hysteresis 1: Schmitt trigger enabled
[7]	PADCFG_PAD_GPIO4_POS	WR	0x0	Power-on-Start (POS) enabler: 1: Enable active pull down for loss of core power 0: Active pull-down capability disabled
[8:31]	Reserved	None	0x0	Reserved

SYS IOMUX CFG SAIF SYSCFG 308

The register can be used to configure the core settings of system signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, "PADCFG_PAD_GPIO0_IE" indicates the attribute "IE" of the signal "GPIO0". See Signal Description for a complete list of the system signals.

Table 78. SYS IOMUX CFG SAIF SYSCFG 308 Register Description
Offset	0x134
Default	0x0
Bit	Name	Access	Default	Description
[0]	PADCFG_PAD_GPIO5_IE	WR	0x1	Input Enable (IE) Controller: 1: Enable the receiver 0: Disable the receiver
[1:2]	PADCFG_PAD_GPIO5_DS	WR	0x0	Output Drive Strength (DS): 00: The rated drive strength is 2 mA. 01: The rated drive strength is 4 mA. 10: The rated drive strength is 8 mA. 01: The rated drive strength is 12 mA.
[3]	PADCFG_PAD_GPIO5_PU	WR	0x1	Pull-Up (PU) settings: 1: Yes 0: No
[4]	PADCFG_PAD_GPIO5_PD	WR	0x0	Pull-Down (PD) settings: 1: Yes 0: No
[5]	PADCFG_PAD_GPIO5_SLEW	WR	0x0	Slew Rate Control: 0: Slow (Half frequency) 1: Fast
[6]	PADCFG_PAD_GPIO5_SMT	WR	0x0	Active high Schmitt (SMT) trigger selector: 0: No hysteresis 1: Schmitt trigger enabled
[7]	PADCFG_PAD_GPIO5_POS	WR	0x0	Power-on-Start (POS) enabler: 1: Enable active pull down for loss of core power 0: Active pull-down capability disabled
[8:31]	Reserved	None	0x0	Reserved

SYS IOMUX CFG SAIF SYSCFG 312

The register can be used to configure the core settings of system signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, "PADCFG_PAD_GPIO0_IE" indicates the attribute "IE" of the signal "GPIO0". See Signal Description for a complete list of the system signals.

Table 79. SYS IOMUX CFG SAIF SYSCFG 312 Register Description
Offset	0x138
Default	0x9
Bit	Name	Access	Default	Description
[0]	PADCFG_PAD_GPIO6_IE	WR	0x1	Input Enable (IE) Controller: 1: Enable the receiver 0: Disable the receiver
[1:2]	PADCFG_PAD_GPIO6_DS	WR	0x0	Output Drive Strength (DS): 00: The rated drive strength is 2 mA. 01: The rated drive strength is 4 mA. 10: The rated drive strength is 8 mA. 01: The rated drive strength is 12 mA.
[3]	PADCFG_PAD_GPIO6_PU	WR	0x1	Pull-Up (PU) settings: 1: Yes 0: No
[4]	PADCFG_PAD_GPIO6_PD	WR	0x0	Pull-Down (PD) settings: 1: Yes 0: No
[5]	PADCFG_PAD_GPIO6_SLEW	WR	0x0	Slew Rate Control: 0: Slow (Half frequency) 1: Fast
[6]	PADCFG_PAD_GPIO6_SMT	WR	0x0	Active high Schmitt (SMT) trigger selector: 0: No hysteresis 1: Schmitt trigger enabled
[7]	PADCFG_PAD_GPIO6_POS	WR	0x0	Power-on-Start (POS) enabler: 1: Enable active pull down for loss of core power 0: Active pull-down capability disabled
[8:31]	Reserved	None	0x0	Reserved

SYS IOMUX CFG SAIF SYSCFG 316

The register can be used to configure the core settings of system signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, "PADCFG_PAD_GPIO0_IE" indicates the attribute "IE" of the signal "GPIO0". See Signal Description for a complete list of the system signals.

Table 80. SYS IOMUX CFG SAIF SYSCFG 316 Register Description
Offset	0x13c
Default	0x1
Bit	Name	Access	Default	Description
[0]	PADCFG_PAD_GPIO7_IE	WR	0x1	Input Enable (IE) Controller: 1: Enable the receiver 0: Disable the receiver
[1:2]	PADCFG_PAD_GPIO7_DS	WR	0x0	Output Drive Strength (DS): 00: The rated drive strength is 2 mA. 01: The rated drive strength is 4 mA. 10: The rated drive strength is 8 mA. 01: The rated drive strength is 12 mA.
[3]	PADCFG_PAD_GPIO7_PU	WR	0x0	Pull-Up (PU) settings: 1: Yes 0: No
[4]	PADCFG_PAD_GPIO7_PD	WR	0x0	Pull-Down (PD) settings: 1: Yes 0: No
[5]	PADCFG_PAD_GPIO7_SLEW	WR	0x0	Slew Rate Control: 0: Slow (Half frequency) 1: Fast
[6]	PADCFG_PAD_GPIO7_SMT	WR	0x0	Active high Schmitt (SMT) trigger selector: 0: No hysteresis 1: Schmitt trigger enabled
[7]	PADCFG_PAD_GPIO7_POS	WR	0x0	Power-on-Start (POS) enabler: 1: Enable active pull down for loss of core power 0: Active pull-down capabil