SYS SYSCON

The JH-7110 system provides the following SYS SYSCON system control registers which provides clock and reset signals to interfaces with master and/or slave signals.

SYS SYSCONSAIF SYSCFG 0

Table 1. SYS SYSCONSAIF SYSCFG 0 Register Description
Offset 0x0
Default 0x0
Bit Name Access Default Description
[3:0] SCFG_e24_remap_haddr WR 0x0
[4:7] SCFG_hifi4_idma_remap_araddr WR 0x0
[11:8] SCFG_hifi4_idma_remap_awaddr WR 0x0
[15:12] SCFG_hifi4_sys_remap_araddr WR 0x0
[19:16] SCFG_hifi4_sys_remap_awaddr WR 0x0
[23:20] SCFG_jpg_remap_araddr WR 0x0
[27:24] SCFG_jpg_remap_awaddr WR 0x0
[31:28] SCFG_sd0_remap_araddr WR 0x0

SYS SYSCONSAIF SYSCFG 4

Table 2. SYS SYSCONSAIF SYSCFG 4 Register Description
Offset 0x4
Default 0x0
Bit Name Access Default Description
[3:0] SCFG_sd1_remap_awaddr WR 0x0
[4:7] SCFG_sec_haddr_remap WR 0x0
[11:8] SCFG_usb_araddr_remap WR 0x0
[15:12] SCFG_usb_awaddr_remap WR 0x0
[19:16] SCFG_vdec_remap_awaddr WR 0x0
[23:20] SCFG_venc_remap_araddr WR 0x0
[27:24] SCFG_venc_remap_awaddr WR 0x0
[31:28] SCFG_vout0_remap_araddr WR 0x0

SYS SYSCONSAIF SYSCFG 8

Table 3. SYS SYSCONSAIF SYSCFG 8 Register Description
Offset 0x8
Default 0x0
Bit Name Access Default Description
[3:0] SCFG_vout0_remap_awaddr WR 0x0
[4:7] SCFG_vout1_remap_araddr WR 0x0
[11:8] SCFG_vout1_remap_awaddr WR 0x0
[31:12] Reserved None 0x0 Reserved

SYS SYSCONSAIF SYSCFG 12

Table 4. SYS SYSCONSAIF SYSCFG 12 Register Description
Offset 16’h0
Access RW
Bit Name Access Default Description
[31] Reserved 0 Reserved
[3:0 ] SYSCFG_gpio_sel18_cfg WR 0x0 Set the GPIO voltage of all the 4 GPIO groups in this field:
  • Bit 0 = 0 : GPIO Group 0 (GPIO21-35) voltage select 3.3 V
  • Bit 0 = 1 : GPIO Group 0 (GPIO21-35) voltage select 1.8 V
  • Bit 1 = 0 : GPIO Group 1 (GPIO36-63) voltage select 3.3 V
  • Bit 1 = 1 : GPIO Group 1 (GPIO36-63) voltage select 1.38V
  • Bit 2 = 0 : GPIO Group 2 (GPIO0-6) voltage select 3.3 V
  • Bit 2 = 1: GPIO Group 2 (GPIO0-6) voltage select 1.8 V
  • Bit 3 = 0 : GPIO Group 3 (GPIO7-20) voltage select 3.3 V
  • Bit 3 = 1 : GPIO Group 3 (GPIO7-20) voltage select 1.8 V
[31:4] Reserved None 0x0 Reserved

SYS SYSCONSAIF SYSCFG 16

Table 5. SYS SYSCONSAIF SYSCFG 16 Register Description
Offset 0x10
Default 0x0
Bit Name Access Default Description
[1:0] u0_CODAJ12_o_cur_inst_a RO 0x0 Tie 0 in jpu internal, do not care
[2] u0_WAVE511_o_vpu_idle RO 0x0 VPU monitoring signal
[3] u0_can_ctrl_can_fd_enable WR 0x0
[4] u0_can_ctrl_host_ecc_disable WR 0x0
[23:5] u0_can_ctrl_host_if RO 0x0
[28:24] u0_cdns_qspi_SCFG_qspi_sclk_dlychain_sel WR 0x0 des_qspi_sclk_dla:clock delay
[31:29] Reserved None 0x0 Reserved

SYS SYSCONSAIF SYSCFG 20

Table 6. SYS SYSCONSAIF SYSCFG 20 Register Description
Offset 0x14
Default 0xd54d54
Bit Name Access Default Description
[0:11] u0_cdns_qspi_SCFG_sram_config WR 0xd54 SRAM/ROM configuration.
  • [0]: SLP, sleep enable, high active, default is low.
  • [1]: SD, shutdown enable, high active, default is low.
  • [2:3]: RTSEL, timing setting for debug purpose, default is 2’b01
  • [4:5]: PTSEL, timing setting for debug purpose, default is 2’b01
  • [6:7]: TRB, timing setting for debug purpose, default is 2’b01
  • [8:9]: WTSEL, timing setting for debug purpose, default is 2’b01
  • [10]: VS, timing setting for debug purpose, default is 1’b1
  • [11]: VG, timing setting for debug purpose, default is 1’b1
[23:12] u0_cdns_spdif_SCFG_sram_config WR 0xd54 SRAM/ROM configuration.
  • [12]: SLP, sleep enable, high active, default is low.
  • [13]: SD, shutdown enable, high active, default is low.
  • [15:14]: RTSEL, timing setting for debug purpose, default is 2’b01
  • [17:16]: PTSEL, timing setting for debug purpose, default is 2’b01
  • [19:18]: TRB, timing setting for debug purpose, default is 2’b01
  • [21:20]: WTSEL, timing setting for debug purpose, default is 2’b01
  • [22]: VS, timing setting for debug purpose, default is 1’b1
  • [23]: VG, timing setting for debug purpose, default is 1’b1
[24] u0_cdns_spdif_trmodeo RO 0x0 1 for transmitter 0 for receiver
[25] u0_i2c_ic_en RO 0x0 I2C interface enable.
[30:26] u0_sdio_data_strobe_phase_ctrl WR 0x0 data strobe delay chain select
[31] u0_sdio_hbig_endian WR 0x0 AHB bus interface endianness:
  • 1: Big-endian AHB bus interface
  • 0: Little-endian AHB bus interface

SYS SYSCONSAIF SYSCFG 24

Table 7. SYS SYSCONSAIF SYSCFG 24 Register Description
Offset 0x18
Default 0x4dea80
Bit Name Access Default Description
[0] u0_sdio_m_hbig_endian WR 0x0 AHB master bus interface endianness:
  • 1: Big-endian AHB bus interface
  • 0: Little-endian AHB bus interface
[1] u0_i2srx_3ch_adc_ena WR 0x0
[2] u0_intmem_rom_sram_SCFG_disable_rom WR 0x0
[14:3] u0_intmem_rom_sram_sram_config WR 0xd50 SRAM/ROM configuration.
  • [3]: SLP, sleep enable, high active, default is low.
  • [4]: SD, shutdown enable, high active, default is low.
  • [6:5]: RTSEL, timing setting for debug purpose, default is 2’b00
  • [8:7]: PTSEL, timing setting for debug purpose, default is 2’b01
  • [10:9]: TRB, timing setting for debug purpose, default is 2’b01
  • [12:11]: WTSEL, timing setting for debug purpose, default is 2’b01
  • [13]: VS, timing setting for debug purpose, default is 1’b1
  • [14]: VG, timing setting for debug purpose, default is 1’b1
[15] u0_jtag_daisy_chain_jtag_en_0 WR 0x1
[16] u0_jtag_daisy_chain_jtag_en_1 WR 0x1
[17] u0_pdrstn_split_sw_usbpipe_plugen WR 0x0
[20:18] u0_pll_wrap_pll0_cpi_bias WR 0x3
[23:21] u0_pll_wrap_pll0_cpp_bias WR 0x2
[24] u0_pll_wrap_pll0_dacpd WR 0x0
[25] u0_pll_wrap_pll0_dsmpd WR 0x0
[31:26] Reserved None 0x0 Reserved

SYS SYSCONSAIF SYSCFG 28

Table 8. SYS SYSCONSAIF SYSCFG 28 Register Description
Offset 0x1c
Default 0x53
Bit Name Access Default Description
[0:11] u0_pll_wrap_pll0_fbdiv WR 0x53
[31:12] Reserved None 0x0 Reserved

SYS SYSCONSAIF SYSCFG 32

Table 9. SYS SYSCONSAIF SYSCFG 32 Register Description
Offset 0x20
Default 0x51555555
Bit Name Access Default Description
[0:23] u0_pll_wrap_pll0_frac WR 0x555555
[25:24] u0_pll_wrap_pll0_gvco_bias WR 0x1
[26] u0_pll_wrap_pll0_lock RO 0x0
[27] u0_pll_wrap_pll0_pd WR 0x0
[29:28] u0_pll_wrap_pll0_postdiv1 WR 0x1
[30:31] u0_pll_wrap_pll0_postdiv2 WR 0x1

SYS SYSCONSAIF SYSCFG 36

Table 10. SYS SYSCONSAIF SYSCFG 36 Register Description
Offset 0x24
Default 0xb02601
Bit Name Access Default Description
[5:0] u0_pll_wrap_pll0_prediv WR 0x1
[6] u0_pll_wrap_pll0_testen WR 0x0
[8:7] u0_pll_wrap_pll0_testsel WR 0x0
[11:9] u0_pll_wrap_pll1_cpi_bias WR 0x3
[14:12] u0_pll_wrap_pll1_cpp_bias WR 0x2
[15] u0_pll_wrap_pll1_dacpd WR 0x0
[16] u0_pll_wrap_pll1_dsmpd WR 0x0
[28:17] u0_pll_wrap_pll1_fbdiv WR 0x58
[31:29] Reserved None 0x0 Reserved

SYS SYSCONSAIF SYSCFG 40

Table 11. SYS SYSCONSAIF SYSCFG 40 Register Description
Offset 0x28
Default 0x51e00000
Bit Name Access Default Description
[0:23] u0_pll_wrap_pll1_frac WR 0xe00000
[25:24] u0_pll_wrap_pll1_gvco_bias WR 0x1
[26] u0_pll_wrap_pll1_lock RO 0x0
[27] u0_pll_wrap_pll1_pd WR 0x0
[29:28] u0_pll_wrap_pll1_postdiv1 WR 0x1
[30:31] u0_pll_wrap_pll1_postdiv2 WR 0x1

SYS SYSCONSAIF SYSCFG 44

Table 12. SYS SYSCONSAIF SYSCFG 44 Register Description
Offset 0x2c
Default 0x662601
Bit Name Access Default Description
[5:0] u0_pll_wrap_pll1_prediv WR 0x1
[6] u0_pll_wrap_pll1_testen WR 0x0
[8:7] u0_pll_wrap_pll1_testsel WR 0x0
[11:9] u0_pll_wrap_pll2_cpi_bias WR 0x3
[14:12] u0_pll_wrap_pll2_cpp_bias WR 0x2
[15] u0_pll_wrap_pll2_dacpd WR 0x0
[16] u0_pll_wrap_pll2_dsmpd WR 0x0
[28:17] u0_pll_wrap_pll2_fbdiv WR 0x33
[31:29] Reserved None 0x0 Reserved

SYS SYSCONSAIF SYSCFG 48

Table 13. SYS SYSCONSAIF SYSCFG 48 Register Description
Offset 0x30
Default 0x41333333
Bit Name Access Default Description
[0:23] u0_pll_wrap_pll2_frac WR 0x333333
[25:24] u0_pll_wrap_pll2_gvco_bias WR 0x1
[26] u0_pll_wrap_pll2_lock RO 0x0
[27] u0_pll_wrap_pll2_pd WR 0x0
[29:28] u0_pll_wrap_pll2_postdiv1 WR 0x0
[30:31] u0_pll_wrap_pll2_postdiv2 WR 0x1

SYS SYSCONSAIF SYSCFG 52

Table 14. SYS SYSCONSAIF SYSCFG 52 Register Description
Offset 0x34
Default 0x1
Bit Name Access Default Description
[5:0] u0_pll_wrap_pll2_prediv WR 0x1
[6] u0_pll_wrap_pll2_testen WR 0x0
[8:7] u0_pll_wrap_pll2_testsel WR 0x0
[9] u0_pll_wrap_syscfg_test_pll_mode WR 0x0 PLL test mode, only used for PLL BIST through jtag2apb.
[17:10] u0_saif_audio_sdin_mux_SCFG_i2sdin_sel WR 0x0
[18] u0_sft7110_noc_bus_CLOCK_GATING_OFF WR 0x0
[19] u0_sft7110_noc_bus_oic_evemon_0_start WR 0x0
[20] u0_sft7110_noc_bus_oic_evemon_0_trigger RO 0x0
[21] u0_sft7110_noc_bus_oic_evemon_1_start WR 0x0
[22] u0_sft7110_noc_bus_oic_evemon_1_trigger RO 0x0
[23] u0_sft7110_noc_bus_oic_evemon_2_start WR 0x0
[24] u0_sft7110_noc_bus_oic_evemon_2_trigger RO 0x0
[25] u0_sft7110_noc_bus_oic_evemon_3_start WR 0x0
[26] u0_sft7110_noc_bus_oic_evemon_3_trigger RO 0x0
[27] u0_sft7110_noc_bus_oic_evemon_4_start WR 0x0
[28] u0_sft7110_noc_bus_oic_evemon_4_trigger RO 0x0
[29] u0_sft7110_noc_bus_oic_evemon_5_start WR 0x0
[30] u0_sft7110_noc_bus_oic_evemon_5_trigger RO 0x0
[31] u0_sft7110_noc_bus_oic_evemon_6_start WR 0x0

SYS SYSCONSAIF SYSCFG 56

Table 15. SYS SYSCONSAIF SYSCFG 56 Register Description
Offset 0x38
Default 0x0
Bit Name Access Default Description
[0] u0_sft7110_noc_bus_oic_evemon_6_trigger RO 0x0
[1] u0_sft7110_noc_bus_oic_evemon_7_start WR 0x0
[2] u0_sft7110_noc_bus_oic_evemon_7_trigger RO 0x0
[3] u0_sft7110_noc_bus_oic_evemon_8_start WR 0x0
[4] u0_sft7110_noc_bus_oic_evemon_8_trigger RO 0x0
[5] u0_sft7110_noc_bus_oic_ignore_modifiable_0 WR 0x0
[6] u0_sft7110_noc_bus_oic_ignore_modifiable_1 WR 0x0
[7] u0_sft7110_noc_bus_oic_ignore_modifiable_2 WR 0x0
[8] u0_sft7110_noc_bus_oic_ignore_modifiable_3 WR 0x0
[9] u0_sft7110_noc_bus_oic_ignore_modifiable_4 WR 0x0
[10:31] Reserved None 0x0 Reserved

SYS SYSCONSAIF SYSCFG 60

Table 16. SYS SYSCONSAIF SYSCFG 60 Register Description
Offset 0x3c
Default 0x0
Bit Name Access Default Description
[0:31] u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_0 WR 0x0

SYS SYSCONSAIF SYSCFG 64

Table 17. SYS SYSCONSAIF SYSCFG 64 Register Description
Offset 0x40
Default 0x0
Bit Name Access Default Description
[0:31] u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_1 WR 0x0

SYS SYSCONSAIF SYSCFG 68

Table 18. SYS SYSCONSAIF SYSCFG 68 Register Description
Offset 0x44
Default 0x0
Bit Name Access Default Description
[0:31] u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_2 WR 0x0

SYS SYSCONSAIF SYSCFG 72

Table 19. SYS SYSCONSAIF SYSCFG 72 Register Description
Offset 0x48
Default 0x0
Bit Name Access Default Description
[0:31] u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_3 WR 0x0

SYS SYSCONSAIF SYSCFG 76

Table 20. SYS SYSCONSAIF SYSCFG 76 Register Description
Offset 0x4c
Default 0x0
Bit Name Access Default Description
[0:31] u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_4 WR 0x0

SYS SYSCONSAIF SYSCFG 80

Table 21. SYS SYSCONSAIF SYSCFG 80 Register Description
Offset 0x50
Default 0x0
Bit Name Access Default Description
[0:31] u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_5 WR 0x0

SYS SYSCONSAIF SYSCFG 84

Table 22. SYS SYSCONSAIF SYSCFG 84 Register Description
Offset 0x54
Default 0x0
Bit Name Access Default Description
[0:31] u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_6 WR 0x0

SYS SYSCONSAIF SYSCFG 88

Table 23. SYS SYSCONSAIF SYSCFG 88 Register Description
Offset 0x58
Default 0x0
Bit Name Access Default Description
[0:31] u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_7 WR 0x0

SYS SYSCONSAIF SYSCFG 92

Table 24. SYS SYSCONSAIF SYSCFG 92 Register Description
Offset 0x5c
Default 0x0
Bit Name Access Default Description
[0:31] u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_8 WR 0x0

SYS SYSCONSAIF SYSCFG 96

Table 25. SYS SYSCONSAIF SYSCFG 96 Register Description
Offset 0x60
Default 0x0
Bit Name Access Default Description
[0] u0_tdm16slot_CLKPOL RO 0x0
[1] u0_tdm16slot_PCM_MS RO 0x0
[6:2] u0_trace_mtx_SCFG_c0_in0_ctl WR 0x0
[11:7] u0_trace_mtx_SCFG_c0_in1_ctl WR 0x0
[16:12] u0_trace_mtx_SCFG_c1_in0_ctl WR 0x0
[21:17] u0_trace_mtx_SCFG_c1_in1_ctl WR 0x0
[26:22] u0_trace_mtx_SCFG_c2_in0_ctl WR 0x0
[31:27] u0_trace_mtx_SCFG_c2_in1_ctl WR 0x0

SYS SYSCONSAIF SYSCFG 100

Table 26. SYS SYSCONSAIF SYSCFG 100 Register Description
Offset 0x64
Default 0x0
Bit Name Access Default Description
[4:0] u0_trace_mtx_SCFG_c3_in0_ctl WR 0x0
[9:5] u0_trace_mtx_SCFG_c3_in1_ctl WR 0x0
[14:10] u0_trace_mtx_SCFG_c4_in0_ctl WR 0x0
[19:15] u0_trace_mtx_SCFG_c4_in1_ctl WR 0x0
[20] u0_u7mc_sft7110_cease_from_tile_0 RO 0x0
[21] u0_u7mc_sft7110_cease_from_tile_1 RO 0x0
[22] u0_u7mc_sft7110_cease_from_tile_2 RO 0x0
[23] u0_u7mc_sft7110_cease_from_tile_3 RO 0x0
[24] u0_u7mc_sft7110_cease_from_tile_4 RO 0x0
[25] u0_u7mc_sft7110_halt_from_tile_0 RO 0x0
[26] u0_u7mc_sft7110_halt_from_tile_1 RO 0x0
[27] u0_u7mc_sft7110_halt_from_tile_2 RO 0x0
[28] u0_u7mc_sft7110_halt_from_tile_3 RO 0x0
[29] u0_u7mc_sft7110_halt_from_tile_4 RO 0x0
[30:31] Reserved None 0x0 Reserved

SYS SYSCONSAIF SYSCFG 104

Table 27. SYS SYSCONSAIF SYSCFG 104 Register Description
Offset 0x68
Default 0x2a000000
Bit Name Access Default Description
[0:31] u0_u7mc_sft7110_reset_vector_1_31_0_ WR 0x2a000000

SYS SYSCONSAIF SYSCFG 108

Table 28. SYS SYSCONSAIF SYSCFG 108 Register Description
Offset 0x6c
Default 0x0
Bit Name Access Default Description
[3:0] u0_u7mc_sft7110_reset_vector_1_35_32_ WR 0x0
[4:31] Reserved None 0x0 Reserved

SYS SYSCONSAIF SYSCFG 112

Table 29. SYS SYSCONSAIF SYSCFG 112 Register Description
Offset 0x70
Default 0x2a000000
Bit Name Access Default Description
[0:31] u0_u7mc_sft7110_reset_vector_2_31_0_ WR 0x2a000000

SYS SYSCONSAIF SYSCFG 116

Table 30. SYS SYSCONSAIF SYSCFG 116 Register Description
Offset 0x74
Default 0x0
Bit Name Access Default Description
[3:0] u0_u7mc_sft7110_reset_vector_2_35_32_ WR 0x0
[4:31] Reserved None 0x0 Reserved

SYS SYSCONSAIF SYSCFG 120

Table 31. SYS SYSCONSAIF SYSCFG 120 Register Description
Offset 0x78
Default 0x2a000000
Bit Name Access Default Description
[0:31] u0_u7mc_sft7110_reset_vector_3_31_0_ WR 0x2a000000

SYS SYSCONSAIF SYSCFG 124

Table 32. SYS SYSCONSAIF SYSCFG 124 Register Description
Offset 0x7c
Default 0x0
Bit Name Access Default Description
[3:0] u0_u7mc_sft7110_reset_vector_3_35_32_ WR 0x0
[4:31] Reserved None 0x0 Reserved

SYS SYSCONSAIF SYSCFG 128

Table 33. SYS SYSCONSAIF SYSCFG 128 Register Description
Offset 0x80
Default 0x2a000000
Bit Name Access Default Description
[0:31] u0_u7mc_sft7110_reset_vector_4_31_0_ WR 0x2a000000

SYS SYSCONSAIF SYSCFG 132

Table 34. SYS SYSCONSAIF SYSCFG 132 Register Description
Offset 0x84
Default 0x1aa8000
Bit Name Access Default Description
[3:0] u0_u7mc_sft7110_reset_vector_4_35_32_ WR 0x0
[4] u0_u7mc_sft7110_suppress_fetch_1 WR 0x0
[5] u0_u7mc_sft7110_suppress_fetch_2 WR 0x0
[6] u0_u7mc_sft7110_suppress_fetch_3 WR 0x0
[7] u0_u7mc_sft7110_suppress_fetch_4 WR 0x0
[8] u0_u7mc_sft7110_wfi_from_tile_0 RO 0x0
[9] u0_u7mc_sft7110_wfi_from_tile_1 RO 0x0
[10] u0_u7mc_sft7110_wfi_from_tile_2 RO 0x0
[11] u0_u7mc_sft7110_wfi_from_tile_3 RO 0x0
[12] u0_u7mc_sft7110_wfi_from_tile_4 RO 0x0
[24:13] u0_vdec_intsram_sram_config WR 0xd54 SRAM/ROM configuration.
  • [13]: SLP, sleep enable, high active, default is low.
  • [14]: SD, shutdown enable, high active, default is low.
  • [16:15]: RTSEL, timing setting for debug purpose, default is 2’b01
  • [18:17]: PTSEL, timing setting for debug purpose, default is 2’b01
  • [20:19]: TRB, timing setting for debug purpose, default is 2’b01
  • [22:21]: WTSEL, timing setting for debug purpose, default is 2’b01
  • [23]: VS, timing setting for debug purpose, default is 1’b1
  • [24]: VG, timing setting for debug purpose, default is 1’b1
[31:25] Reserved None 0x0 Reserved

SYS SYSCONSAIF SYSCFG 136

Table 35. SYS SYSCONSAIF SYSCFG 136 Register Description
Offset 0x88
Default 0xd54
Bit Name Access Default Description
[0:11] u0_venc_intsram_sram_config WR 0xd54 SRAM/ROM configuration.
  • [0]: SLP, sleep enable, high active, default is low.
  • [1]: SD, shutdown enable, high active, default is low.
  • [2:3]: RTSEL, timing setting for debug purpose, default is 2’b01
  • [4:5]: PTSEL, timing setting for debug purpose, default is 2’b01
  • [6:7]: TRB, timing setting for debug purpose, default is 2’b01
  • [8:9]: WTSEL, timing setting for debug purpose, default is 2’b01
  • [10]: VS, timing setting for debug purpose, default is 1’b1
  • [11]: VG, timing setting for debug purpose, default is 1’b1
[14:12] u0_wave420l_i_ipu_current_buffer WR 0x0 This signal indicates which buffer is currently active so that the VPU can correctly use the ipu_end_of_row signal for row counter.
[15] u0_wave420l_i_ipu_end_of_row WR 0x0 This signal is flipped every time when the IPU completes writing a row.
[16] u0_wave420l_i_ipu_new_frame WR 0x0 This signal is flipped every time the IPU starts writing a new frame.
[17] u0_wave420l_o_vpu_idle RO 0x0 VPU monitoring signal, This signal gives out an opposite value of VPU_BUSY register.
[18] u1_can_ctrl_can_fd_enable WR 0x0
[19] u1_can_ctrl_host_ecc_disable WR 0x0
[31:20] Reserved None 0x0 Reserved

SYS SYSCONSAIF SYSCFG 140

Table 36. SYS SYSCONSAIF SYSCFG 140 Register Description
Offset 0x8c
Default 0x6aa00000
Bit Name Access Default Description
[18:0] u1_can_ctrl_host_if RO 0x0
[30:19] u1_gmac5_axi64_SCFG_ram_cfg WR 0xd54 SRAM/ROM configuration.
  • [19]: SLP, sleep enable, high active, default is low.
  • [20]: SD, shutdown enable, high active, default is low.
  • [22:21]: RTSEL, timing setting for debug purpose, default is 2’b01
  • [24:23]: PTSEL, timing setting for debug purpose, default is 2’b01
  • [25:26]: TRB, timing setting for debug purpose, default is 2’b01
  • [27:28]: WTSEL, timing setting for debug purpose, default is 2’b01
  • [29]: VS, timing setting for debug purpose, default is 1’b1
  • [30]: VG, timing setting for debug purpose, default is 1’b1
[31] Reserved None 0x0 Reserved

SYS SYSCONSAIF SYSCFG 144

Table 37. SYS SYSCONSAIF SYSCFG 144 Register Description
Offset 0x90
Default 0x4
Bit Name Access Default Description
[1:0] u1_gmac5_axi64_mac_speed_o RO 0x0
[4:2] u1_gmac5_axi64_phy_intf_sel_i WR 0x1

Active PHY Selected

When you have multiple GMAC PHY interfaces in your configuration, this field indicates the sampled value of the PHY selector during reset de-assertion.

Values:

  • 0x0(GMII_MII): GMII or MII
  • 0x1(RGMII): RGMII
  • 0x2(SGMII): SGMII
  • 0x3(TBI): TBI
  • 0x4(RMII): RMII
  • 0x5(RTBI): RTBI
  • 0x6(SMII): SMII
  • 0x7(REVMIII): RevMII
[31:5] Reserved None 0x0 Reserved

SYS SYSCONSAIF SYSCFG 148

Table 38. SYS SYSCONSAIF SYSCFG 148 Register Description
Offset 0x94
Default 0x0
Bit Name Access Default Description
[0:31] u1_gmac5_axi64_ptp_timestamp_o_31_0_ RO 0x0

SYS SYSCONSAIF SYSCFG 152

Table 39. SYS SYSCONSAIF SYSCFG 152 Register Description
Offset 0x98
Default 0x0
Bit Name Access Default Description
[0:31] u1_gmac5_axi64_ptp_timestamp_o_63_32_ RO 0x0

SYS SYSCONSAIF SYSCFG 156

Table 40. SYS SYSCONSAIF SYSCFG 156 Register Description
Offset 0x9c
Default 0x400
Bit Name Access Default Description
[0] u1_i2c_ic_en RO 0x0 I2C interface enable.
[5:1] u1_sdio_data_strobe_phase_ctrl WR 0x0 data strobe delay chain select
[6] u1_sdio_hbig_endian WR 0x0 AHB bus interface endianness:
  • 1: Big-endian AHB bus interface
  • 0: Little-endian AHB bus interface
[7] u1_sdio_m_hbig_endian WR 0x0 AHB master bus interface endianness:
  • 1: Big-endian AHB bus interface
  • 0: Little-endian AHB bus interface
[8] u1_reset_ctrl_clr_reset_status WR 0x0
[9] u1_reset_ctrl_pll_timecnt_finish RO 0x0
[10] u1_reset_ctrl_rstn_sw WR 0x1
[14:11] u1_reset_ctrl_sys_reset_status RO 0x0
[15] u2_i2c_ic_en RO 0x0 I2C interface enable.
[16] u3_i2c_ic_en RO 0x0 I2C interface enable.
[17] u4_i2c_ic_en RO 0x0 I2C interface enable.
[18] u5_i2c_ic_en RO 0x0 I2C interface enable.
[19] u6_i2c_ic_en RO 0x0 I2C interface enable.
[31:20] Reserved None 0x0 Reserved