STG SYSCON

SYS_SYSCONSAIF__SYSCFG_0

Table 1. SYS_SYSCONSAIF__SYSCFG_0 Register Description
Offset	0x0
Default	0x0
Bit	Name	Access	Default	Description
[0:3]	SCFG_hprot_sd0	WR	0x0
[4:7]	SCFG_hprot_sd1	WR	0x0
[8]	u0_cdn_usb_adp_en	RO	0x0
[9]	u0_cdn_usb_adp_probe_ana	WR	0x0
[10]	u0_cdn_usb_adp_probe_en	RO	0x0
[11]	u0_cdn_usb_adp_sense_ana	WR	0x0
[12]	u0_cdn_usb_adp_sense_en	RO	0x0
[13]	u0_cdn_usb_adp_sink_current_en	RO	0x0
[14]	u0_cdn_usb_adp_source_current_en	RO	0x0
[15]	u0_cdn_usb_bc_en	RO	0x0
[16]	u0_cdn_usb_chrg_vbus	WR	0x0
[17]	u0_cdn_usb_dcd_comp_sts	WR	0x0
[18]	u0_cdn_usb_dischrg_vbus	WR	0x0
[19]	u0_cdn_usb_dm_vdat_ref_comp_en	RO	0x0
[20]	u0_cdn_usb_dm_vdat_ref_comp_sts	WR	0x0
[21]	u0_cdn_usb_dm_vlgc_comp_en	RO	0x0
[22]	u0_cdn_usb_dm_vlgc_comp_sts	WR	0x0
[23]	u0_cdn_usb_dp_vdat_ref_comp_en	RO	0x0
[24]	u0_cdn_usb_dp_vdat_ref_comp_sts	WR	0x0
[25]	u0_cdn_usb_host_system_err	WR	0x0
[26]	u0_cdn_usb_hsystem_err_ext	RO	0x0
[27]	u0_cdn_usb_idm_sink_en	RO	0x0
[28]	u0_cdn_usb_idp_sink_en	RO	0x0
[29]	u0_cdn_usb_idp_src_en	RO	0x0
[30:31]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 4

Table 2. STG SYSCONSAIF SYSCFG 4 Register Description
Offset	0x4
Default	0x2000
Bit	Name	Access	Default	Description
[0:11]	u0_cdn_usb_lowest_belt	RO	0x0	LTM interface to software
[12]	u0_cdn_usb_ltm_host_req	RO	0x0	LTM interface to software
[13]	u0_cdn_usb_ltm_host_req_halt	WR	0x1	LTM interface to software
[14]	u0_cdn_usb_mdctrl_clk_sel	WR	0x0
[15]	u0_cdn_usb_mdctrl_clk_status	RO	0x0
[18:16]	u0_cdn_usb_mode_strap	WR	0x0	Can only be changed when pwrup_rst_n is low
[19]	u0_cdn_usb_otg_suspendm	WR	0x0
[20]	u0_cdn_usb_otg_suspendm_byps	WR	0x0
[21]	u0_cdn_usb_phy_bvalid	RO	0x0
[22]	u0_cdn_usb_pll_en	WR	0x0
[23]	u0_cdn_usb_refclk_mode	WR	0x0
[24]	u0_cdn_usb_rid_a_comp_sts	WR	0x0
[25]	u0_cdn_usb_rid_b_comp_sts	WR	0x0
[26]	u0_cdn_usb_rid_c_comp_sts	WR	0x0
[27]	u0_cdn_usb_rid_float_comp_en	RO	0x0
[28]	u0_cdn_usb_rid_float_comp_sts	WR	0x0
[29]	u0_cdn_usb_rid_gnd_comp_sts	WR	0x0
[30]	u0_cdn_usb_rid_nonfloat_comp_en	RO	0x0
[31]	u0_cdn_usb_rx_dm	RO	0x0

STG SYSCONSAIF SYSCFG 8

Table 3. STG SYSCONSAIF SYSCFG 8 Register Description
Offset	0x8
Default	0x41000
Bit	Name	Access	Default	Description
[0]	u0_cdn_usb_rx_dp	RO	0x0
[1]	u0_cdn_usb_rx_rcv	RO	0x0
[2]	u0_cdn_usb_self_test	WR	0x0	for software bist_test
[3]	u0_cdn_usb_sessend	RO	0x0
[4]	u0_cdn_usb_sessvalid	RO	0x0
[5]	u0_cdn_usb_sof	RO	0x0
[6]	u0_cdn_usb_test_bist	RO	0x0	for software bist_test
[7]	u0_cdn_usb_usbdev_main_power_off_ack	RO	0x0
[8]	u0_cdn_usb_usbdev_main_power_off_ready	RO	0x0
[9]	u0_cdn_usb_usbdev_main_power_off_req	WR	0x0
[10]	u0_cdn_usb_usbdev_main_power_on_ready	RO	0x0
[11]	u0_cdn_usb_usbdev_main_power_on_req	RO	0x0
[12]	u0_cdn_usb_usbdev_main_power_on_valid	WR	0x1
[13]	u0_cdn_usb_usbdev_power_off_ack	RO	0x0
[14]	u0_cdn_usb_usbdev_power_off_ready	RO	0x0
[15]	u0_cdn_usb_usbdev_power_off_req	WR	0x0
[16]	u0_cdn_usb_usbdev_power_on_ready	RO	0x0
[17]	u0_cdn_usb_usbdev_power_on_req	RO	0x0
[18]	u0_cdn_usb_usbdev_power_on_valid	WR	0x1
[19]	u0_cdn_usb_utmi_dmpulldown_sit	WR	0x0
[20]	u0_cdn_usb_utmi_dppulldown_sit	WR	0x0
[21]	u0_cdn_usb_utmi_fslsserialmode_sit	WR	0x0
[22]	u0_cdn_usb_utmi_hostdisconnect_sit	RO	0x0
[23]	u0_cdn_usb_utmi_iddig_sit	RO	0x0
[24]	u0_cdn_usb_utmi_idpullup_sit	WR	0x0
[25:26]	u0_cdn_usb_utmi_linestate_sit	RO	0x0
[27:28]	u0_cdn_usb_utmi_opmode_sit	WR	0x0
[29]	u0_cdn_usb_utmi_rxactive_sit	RO	0x0
[30]	u0_cdn_usb_utmi_rxerror_sit	RO	0x0
[31]	u0_cdn_usb_utmi_rxvalid_sit	RO	0x0

STG SYSCONSAIF SYSCFG 12

Table 4. STG SYSCONSAIF SYSCFG 12 Register Description
Offset	0xc
Default	0x2
Bit	Name	Access	Default	Description
[0]	u0_cdn_usb_utmi_rxvalidh_sit	RO	0x0
[1]	u0_cdn_usb_utmi_sessvld	WR	0x1
[2]	u0_cdn_usb_utmi_termselect_sit	WR	0x0
[3]	u0_cdn_usb_utmi_tx_dat_sit	WR	0x0
[4]	u0_cdn_usb_utmi_tx_enable_n_sit	WR	0x0
[5]	u0_cdn_usb_utmi_tx_se0_sit	WR	0x0
[6]	u0_cdn_usb_utmi_txbitstuffenable_sit	WR	0x0
[7]	u0_cdn_usb_utmi_txready_sit	RO	0x0
[8]	u0_cdn_usb_utmi_txvalid_sit	WR	0x0
[9]	u0_cdn_usb_utmi_txvalidh_sit	WR	0x0
[10]	u0_cdn_usb_utmi_vbusvalid_sit	RO	0x0
[12:11]	u0_cdn_usb_utmi_xcvrselect_sit	WR	0x0
[13]	u0_cdn_usb_vdm_src_en	RO	0x0
[14]	u0_cdn_usb_vdp_src_en	RO	0x0
[15]	u0_cdn_usb_wakeup	WR	0x0
[16]	u0_cdn_usb_xhc_d0_ack	RO	0x0
[17]	u0_cdn_usb_xhc_d0_req	WR	0x0
[18:31]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 16

Table 5. STG SYSCONSAIF SYSCFG 16 Register Description
Offset	0x10
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_cdn_usb_xhci_debug_bus	RO	0x0

STG SYSCONSAIF SYSCFG 20

Table 6. STG SYSCONSAIF SYSCFG 20 Register Description
Offset	0x14
Default	0x0
Bit	Name	Access	Default	Description
[0:30]	u0_cdn_usb_xhci_debug_link_state	RO	0x0
[31]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 24

Table 7. STG SYSCONSAIF SYSCFG 24 Register Description
Offset	0x18
Default	0x8200
Bit	Name	Access	Default	Description
[4:0]	u0_cdn_usb_xhci_debug_sel	WR	0x0
[5]	u0_cdn_usb_xhci_main_power_off_ack	RO	0x0
[6]	u0_cdn_usb_xhci_main_power_off_req	WR	0x0
[7]	u0_cdn_usb_xhci_main_power_on_ready	RO	0x0
[8]	u0_cdn_usb_xhci_main_power_on_req	RO	0x0
[9]	u0_cdn_usb_xhci_main_power_on_valid	WR	0x1
[10]	u0_cdn_usb_xhci_power_off_ack	RO	0x0
[11]	u0_cdn_usb_xhci_power_off_ready	RO	0x0
[12]	u0_cdn_usb_xhci_power_off_req	WR	0x0
[13]	u0_cdn_usb_xhci_power_on_ready	RO	0x0
[14]	u0_cdn_usb_xhci_power_on_req	RO	0x0
[15]	u0_cdn_usb_xhci_power_on_valid	WR	0x1
[16]	u0_e2_sft7110_cease_from_tile_0	RO	0x0
[17]	u0_e2_sft7110_debug_from_tile_0	RO	0x0
[18]	u0_e2_sft7110_halt_from_tile_0	RO	0x0
[19:31]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 28

Table 8. STG SYSCONSAIF SYSCFG 28 Register Description
Offset	0x1c
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_e2_sft7110_nmi_0_rnmi_exception_vector	WR	0x0

STG SYSCONSAIF SYSCFG 32

Table 9. STG SYSCONSAIF SYSCFG 32 Register Description
Offset	0x20
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_e2_sft7110_nmi_0_rnmi_interrupt_vector	WR	0x0

STG SYSCONSAIF SYSCFG 36

Table 10. STG SYSCONSAIF SYSCFG 36 Register Description
Offset	0x24
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_e2_sft7110_reset_vector_0	WR	0x0

STG SYSCONSAIF SYSCFG 40

Table 11. STG SYSCONSAIF SYSCFG 40 Register Description
Offset	0x28
Default	0x0
Bit	Name	Access	Default	Description
[0]	u0_e2_sft7110_wfi_from_tile_0	RO	0x0
[1:31]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 44

Table 12. STG SYSCONSAIF SYSCFG 44 Register Description
Offset	0x2c
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_hifi4_AltResetVec	WR	0x0	Reset Vector Address

STG SYSCONSAIF SYSCFG 48

Table 13. STG SYSCONSAIF SYSCFG 48 Register Description
Offset	0x30
Default	0x0
Bit	Name	Access	Default	Description
[0]	u0_hifi4_BreakIn	WR	0x0	Debug signal
[1]	u0_hifi4_BreakInAck	RO	0x0	Debug signal
[2]	u0_hifi4_BreakOut	RO	0x0	Debug signal
[3]	u0_hifi4_BreakOutAck	WR	0x0	Debug signal
[4]	u0_hifi4_DebugMode	RO	0x0	Debug signal
[5]	u0_hifi4_DoubleExceptionError	RO	0x0	Fault Handling Signals
[6]	u0_hifi4_IRam0LoadStore	RO	0x0	indicates that iram0 work
[7]	u0_hifi4_IRam1LoadStore	RO	0x0	indicates that iram1 work
[8]	u0_hifi4_OCDHaltOnReset	WR	0x0	Debug signal
[9]	u0_hifi4_PFatalError	RO	0x0	Fault Handling Signals
[10:31]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 52

Table 14. STG SYSCONSAIF SYSCFG 52 Register Description
Offset	0x34
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_hifi4_PFaultInfo	RO	0x0	Fault Handling Signals

STG SYSCONSAIF SYSCFG 56

Table 15. STG SYSCONSAIF SYSCFG 56 Register Description
Offset	0x38
Default	0x0
Bit	Name	Access	Default	Description
[0]	u0_hifi4_PFaultInfoValid	RO	0x0	Fault Handling Signals
[16:1]	u0_hifi4_PRID	WR	0x0	module id
[17]	u0_hifi4_PWaitMode	RO	0x0	Wait Mode
[18]	u0_hifi4_RunStall	WR	0x0	Run Stall
[19:31]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 60

Table 16. STG SYSCONSAIF SYSCFG 60 Register Description
Offset	0x3c
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_hifi4_SCFG_dsp_mst_offset	WR	0x0	[0:11] indicates that master port remap address [27:16] indicates that DMA port remap address

STG SYSCONSAIF SYSCFG 64

Table 17. STG SYSCONSAIF SYSCFG 64 Register Description
Offset	0x40
Default	0x40000000
Bit	Name	Access	Default	Description
[0:31]	u0_hifi4_SCFG_dsp_slv_offset	WR	0x40000000	The value indicates the slave port remap address

STG SYSCONSAIF SYSCFG 68

Table 18. STG SYSCONSAIF SYSCFG 68 Register Description
Offset	0x44
Default	0xd54
Bit	Name	Access	Default	Description
[0:11]	u0_hifi4_SCFG_sram_config	WR	0xd54	SRAM/ROM configuration. [0]: SLP, sleep enable, high active, default is low. [1]: SD, shutdown enable, high active, default is low. [2:3]: RTSEL, timing setting for debug purpose, default is 2’b01 [4:5]: PTSEL, timing setting for debug purpose, default is 2’b01 [6:7]: TRB, timing setting for debug purpose, default is 2’b01 [8:9]: WTSEL, timing setting for debug purpose, default is 2’b01 [10]: VS, timing setting for debug purpose, default is 1’b1 [11]: VG, timing setting for debug purpose, default is 1’b1
[12]	u0_hifi4_StatVectorSel	WR	0x0	When the value is 1, it indicates that the AltResetVec is valid
[13]	u0_hifi4_TrigIn_iDMA	WR	0x0	DMA port trigger
[14]	u0_hifi4_TrigOut_iDMA	RO	0x0	DMA port trigger
[15]	u0_hifi4_XOCDMode	RO	0x0	Debug signal
[16]	u0_plda_pcie_align_detect	RO	0x0
[31:17]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 72

Table 19. STG SYSCONSAIF SYSCFG 72 Register Description
Offset	0x48
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_axi4_mst0_aratomop_31_0_	RO	0x0

STG SYSCONSAIF SYSCFG 76

Table 20. STG SYSCONSAIF SYSCFG 76 Register Description
Offset	0x4c
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_axi4_mst0_aratomop_63_32_	RO	0x0

STG SYSCONSAIF SYSCFG 80

Table 21. STG SYSCONSAIF SYSCFG 80 Register Description
Offset	0x50
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_axi4_mst0_aratomop_95_64_	RO	0x0

STG SYSCONSAIF SYSCFG 84

Table 22. STG SYSCONSAIF SYSCFG 84 Register Description
Offset	0x54
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_axi4_mst0_aratomop_127_96_	RO	0x0

STG SYSCONSAIF SYSCFG 88

Table 23. STG SYSCONSAIF SYSCFG 88 Register Description
Offset	0x58
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_axi4_mst0_aratomop_159_128_	RO	0x0

STG SYSCONSAIF SYSCFG 92

Table 24. STG SYSCONSAIF SYSCFG 92 Register Description
Offset	0x5c
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_axi4_mst0_aratomop_191_160_	RO	0x0

STG SYSCONSAIF SYSCFG 96

Table 25. STG SYSCONSAIF SYSCFG 96 Register Description
Offset	0x60
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_axi4_mst0_aratomop_223_192_	RO	0x0

STG SYSCONSAIF SYSCFG 100

Table 26. STG SYSCONSAIF SYSCFG 100 Register Description
Offset	0x64
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_axi4_mst0_aratomop_255_224_	RO	0x0

STG SYSCONSAIF SYSCFG 104

Table 27. STG SYSCONSAIF SYSCFG 104 Register Description
Offset	0x68
Default	0x0
Bit	Name	Access	Default	Description
[1:0]	u0_plda_pcie_axi4_mst0_aratomop_257_256_	RO	0x0
[16:2]	u0_plda_pcie_axi4_mst0_arfunc	RO	0x0
[20:17]	u0_plda_pcie_axi4_mst0_arregion	RO	0x0
[31:21]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 108

Table 28. STG SYSCONSAIF SYSCFG 108 Register Description
Offset	0x6c
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_axi4_mst0_aruser_31_0_	RO	0x0

STG SYSCONSAIF SYSCFG 112

Table 29. STG SYSCONSAIF SYSCFG 112 Register Description
Offset	0x70
Default	0x0
Bit	Name	Access	Default	Description
[20:0]	u0_plda_pcie_axi4_mst0_aruser_52_32_	RO	0x0
[31:21]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 116

Table 30. STG SYSCONSAIF SYSCFG 116 Register Description
Offset	0x74
Default	0x0
Bit	Name	Access	Default	Description
[14:0]	u0_plda_pcie_axi4_mst0_awfunc	RO	0x0
[18:15]	u0_plda_pcie_axi4_mst0_awregion	RO	0x0
[19:31]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 120

Table 31. STG SYSCONSAIF SYSCFG 120 Register Description
Offset	0x78
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_axi4_mst0_awuser_31_0_	RO	0x0

STG SYSCONSAIF SYSCFG 124

Table 32. STG SYSCONSAIF SYSCFG 124 Register Description
Offset	0x7c
Default	0x0
Bit	Name	Access	Default	Description
[10:0]	u0_plda_pcie_axi4_mst0_awuser_42_32_	RO	0x0
[18:11]	u0_plda_pcie_axi4_mst0_rderr	WR	0x0
[19:31]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 128

Table 33. STG SYSCONSAIF SYSCFG 128 Register Description
Offset	0x80
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_axi4_mst0_ruser	WR	0x0

STG SYSCONSAIF SYSCFG 132

Table 34. STG SYSCONSAIF SYSCFG 132 Register Description
Offset	0x84
Default	0x0
Bit	Name	Access	Default	Description
[7:0]	u0_plda_pcie_axi4_mst0_wderr	RO	0x0
[8:31]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 136

Table 35. STG SYSCONSAIF SYSCFG 136 Register Description
Offset	0x88
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_axi4_slv0_aratomop_31_0_	WR	0x0

STG SYSCONSAIF SYSCFG 140

Table 36. STG SYSCONSAIF SYSCFG 140 Register Description
Offset	0x8c
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_axi4_slv0_aratomop_63_32_	WR	0x0

STG SYSCONSAIF SYSCFG 144

Table 37. STG SYSCONSAIF SYSCFG 144 Register Description
Offset	0x90
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_axi4_slv0_aratomop_95_64_	WR	0x0

STG SYSCONSAIF SYSCFG 148

Table 38. STG SYSCONSAIF SYSCFG 148 Register Description
Offset	0x94
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_axi4_slv0_aratomop_127_96_	WR	0x0

STG SYSCONSAIF SYSCFG 152

Table 39. STG SYSCONSAIF SYSCFG 152 Register Description
Offset	0x98
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_axi4_slv0_aratomop_159_128_	WR	0x0

STG SYSCONSAIF SYSCFG 156

Table 40. STG SYSCONSAIF SYSCFG 156 Register Description
Offset	0x9c
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_axi4_slv0_aratomop_191_160_	WR	0x0

STG SYSCONSAIF SYSCFG 160

Table 41. STG SYSCONSAIF SYSCFG 160 Register Description
Offset	0xa0
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_axi4_slv0_aratomop_223_192_	WR	0x0

STG SYSCONSAIF SYSCFG 164

Table 42. STG SYSCONSAIF SYSCFG 164 Register Description
Offset	0xa4
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_axi4_slv0_aratomop_255_224_	WR	0x0

STG SYSCONSAIF SYSCFG 168

Table 43. STG SYSCONSAIF SYSCFG 168 Register Description
Offset	0xa8
Default	0x0
Bit	Name	Access	Default	Description
[1:0]	u0_plda_pcie_axi4_slv0_aratomop_257_256_	WR	0x0
[16:2]	u0_plda_pcie_axi4_slv0_arfunc	WR	0x0
[20:17]	u0_plda_pcie_axi4_slv0_arregion	WR	0x0
[31:21]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 172

Table 44. STG SYSCONSAIF SYSCFG 172 Register Description
Offset	0xac
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_axi4_slv0_aruser_31_0_	WR	0x0

STG SYSCONSAIF SYSCFG 176

Table 45. STG SYSCONSAIF SYSCFG 176 Register Description
Offset	0xb0
Default	0x0
Bit	Name	Access	Default	Description
[8:0]	u0_plda_pcie_axi4_slv0_aruser_40_32_	WR	0x0
[23:9]	u0_plda_pcie_axi4_slv0_awfunc	WR	0x0
[27:24]	u0_plda_pcie_axi4_slv0_awregion	WR	0x0
[31:28]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 180

Table 46. STG SYSCONSAIF SYSCFG 180 Register Description
Offset	0xb4
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_axi4_slv0_awuser_31_0_	WR	0x0

STG SYSCONSAIF SYSCFG 184

Table 47. STG SYSCONSAIF SYSCFG 184 Register Description
Offset	0xb8
Default	0x0
Bit	Name	Access	Default	Description
[8:0]	u0_plda_pcie_axi4_slv0_awuser_40_32_	WR	0x0
[16:9]	u0_plda_pcie_axi4_slv0_rderr	RO	0x0
[31:17]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 188

Table 48. STG SYSCONSAIF SYSCFG 188 Register Description
Offset	0xbc
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_axi4_slv0_ruser	RO	0x0

STG SYSCONSAIF SYSCFG 192

Table 49. STG SYSCONSAIF SYSCFG 192 Register Description
Offset	0xc0
Default	0x0
Bit	Name	Access	Default	Description
[7:0]	u0_plda_pcie_axi4_slv0_wderr	WR	0x0
[22:8]	u0_plda_pcie_axi4_slvl_arfunc	WR	0x0
[31:23]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 196

Table 50. STG SYSCONSAIF SYSCFG 196 Register Description
Offset	0xc4
Default	0x0
Bit	Name	Access	Default	Description
[14:0]	u0_plda_pcie_axi4_slvl_awfunc	WR	0x0
[16:15]	u0_plda_pcie_bus_width_o	RO	0x0
[17]	u0_plda_pcie_bypass_codec	WR	0x0
[19:18]	u0_plda_pcie_ckref_src	WR	0x0
[21:20]	u0_plda_pcie_clk_sel	WR	0x0
[22]	u0_plda_pcie_clkreq	WR	0x0
[31:23]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 200

Table 51. STG SYSCONSAIF SYSCFG 200 Register Description
Offset	0xc8
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_k_phyparam_31_0_	WR	0x0

STG SYSCONSAIF SYSCFG 204

Table 52. STG SYSCONSAIF SYSCFG 204 Register Description
Offset	0xcc
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_k_phyparam_63_32_	WR	0x0

STG SYSCONSAIF SYSCFG 208

Table 53. STG SYSCONSAIF SYSCFG 208 Register Description
Offset	0xd0
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_k_phyparam_95_64_	WR	0x0

STG SYSCONSAIF SYSCFG 212

Table 54. STG SYSCONSAIF SYSCFG 212 Register Description
Offset	0xd4
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_k_phyparam_127_96_	WR	0x0

STG SYSCONSAIF SYSCFG 216

Table 55. STG SYSCONSAIF SYSCFG 216 Register Description
Offset	0xd8
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_k_phyparam_159_128_	WR	0x0

STG SYSCONSAIF SYSCFG 220

Table 56. STG SYSCONSAIF SYSCFG 220 Register Description
Offset	0xdc
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_k_phyparam_191_160_	WR	0x0

STG SYSCONSAIF SYSCFG 224

Table 57. STG SYSCONSAIF SYSCFG 224 Register Description
Offset	0xe0
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_k_phyparam_223_192_	WR	0x0

STG SYSCONSAIF SYSCFG 228

Table 58. STG SYSCONSAIF SYSCFG 228 Register Description
Offset	0xe4
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_k_phyparam_255_224_	WR	0x0

STG SYSCONSAIF SYSCFG 232

Table 59. STG SYSCONSAIF SYSCFG 232 Register Description
Offset	0xe8
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_k_phyparam_287_256_	WR	0x0

STG SYSCONSAIF SYSCFG 236

Table 60. STG SYSCONSAIF SYSCFG 236 Register Description
Offset	0xec
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_k_phyparam_319_288_	WR	0x0

STG SYSCONSAIF SYSCFG 240

Table 61. STG SYSCONSAIF SYSCFG 240 Register Description
Offset	0xf0
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_k_phyparam_351_320_	WR	0x0

STG SYSCONSAIF SYSCFG 244

Table 62. STG SYSCONSAIF SYSCFG 244 Register Description
Offset	0xf4
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_k_phyparam_383_352_	WR	0x0

STG SYSCONSAIF SYSCFG 248

Table 63. STG SYSCONSAIF SYSCFG 248 Register Description
Offset	0xf8
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_k_phyparam_415_384_	WR	0x0

STG SYSCONSAIF SYSCFG 252

Table 64. STG SYSCONSAIF SYSCFG 252 Register Description
Offset	0xfc
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_k_phyparam_447_416_	WR	0x0

STG SYSCONSAIF SYSCFG 256

Table 65. STG SYSCONSAIF SYSCFG 256 Register Description
Offset	0x100
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_k_phyparam_479_448_	WR	0x0

STG SYSCONSAIF SYSCFG 260

Table 66. STG SYSCONSAIF SYSCFG 260 Register Description
Offset	0x104
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_k_phyparam_511_480_	WR	0x0

STG SYSCONSAIF SYSCFG 264

Table 67. STG SYSCONSAIF SYSCFG 264 Register Description
Offset	0x108
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_k_phyparam_543_512_	WR	0x0

STG SYSCONSAIF SYSCFG 268

Table 68. STG SYSCONSAIF SYSCFG 268 Register Description
Offset	0x10c
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_k_phyparam_575_544_	WR	0x0

STG SYSCONSAIF SYSCFG 272

Table 69. STG SYSCONSAIF SYSCFG 272 Register Description
Offset	0x110
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_k_phyparam_607_576_	WR	0x0

STG SYSCONSAIF SYSCFG 276

Table 70. STG SYSCONSAIF SYSCFG 276 Register Description
Offset	0x114
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_k_phyparam_671_640_	WR	0x0

STG SYSCONSAIF SYSCFG 284

Table 71. STG SYSCONSAIF SYSCFG 284 Register Description
Offset	0x11c
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_k_phyparam_703_672_	WR	0x0

STG SYSCONSAIF SYSCFG 288

Table 72. STG SYSCONSAIF SYSCFG 288 Register Description
Offset	0x120
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_k_phyparam_735_704_	WR	0x0

STG SYSCONSAIF SYSCFG 292

Table 73. STG SYSCONSAIF SYSCFG 292 Register Description
Offset	0x124
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_k_phyparam_767_736_	WR	0x0

STG SYSCONSAIF SYSCFG 296

Table 74. STG SYSCONSAIF SYSCFG 296 Register Description
Offset	0x128
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_k_phyparam_799_768_	WR	0x0

STG SYSCONSAIF SYSCFG 300

Table 75. STG SYSCONSAIF SYSCFG 300 Register Description
Offset	0x12c
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_k_phyparam_831_800_	WR	0x0

STG SYSCONSAIF SYSCFG 304

Table 76. STG SYSCONSAIF SYSCFG 304 Register Description
Offset	0x130
Default	0x0
Bit	Name	Access	Default	Description
[7:0]	u0_plda_pcie_k_phyparam_839_832_	WR	0x0
[8]	u0_plda_pcie_k_rp_nep	WR	0x0
[9]	u0_plda_pcie_l1sub_entack	RO	0x0
[10]	u0_plda_pcie_l1sub_entreq	WR	0x0
[31:11]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 308

Table 77. STG SYSCONSAIF SYSCFG 308 Register Description
Offset	0x134
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_local_interrupt_in	WR	0x0

STG SYSCONSAIF SYSCFG 312

Table 78. SYS_SYSCONSAIF__SYSCFG_0 Register Description
Offset	0x138
Default	0x4800001
Bit	Name	Access	Default	Description
[0]	u0_plda_pcie_mperstn	WR	0x1
[1]	u0_plda_pcie_pcie_ebuf_mode	WR	0x0
[24:2]	u0_plda_pcie_pcie_phy_test_cfg	WR	0x200000
[25]	u0_plda_pcie_pcie_rx_eq_training	WR	0x0
[26]	u0_plda_pcie_pcie_rxterm_en	WR	0x1
[27]	u0_plda_pcie_pcie_tx_oneszeros	WR	0x0
[31:28]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 316

Table 79. STG SYSCONSAIF SYSCFG 316 Register Description
Offset	0x13c
Default	0x0
Bit	Name	Access	Default	Description
[19:0]	u0_plda_pcie_pf0_offset	WR	0x0
[31:20]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 320

Table 80. STG SYSCONSAIF SYSCFG 320 Register Description
Offset	0x140
Default	0x0
Bit	Name	Access	Default	Description
[19:0]	u0_plda_pcie_pf1_offset	WR	0x0
[31:20]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 324

Table 81. STG SYSCONSAIF SYSCFG 324 Register Description
Offset	0x144
Default	0x0
Bit	Name	Access	Default	Description
[19:0]	u0_plda_pcie_pf2_offset	WR	0x0
[31:20]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 328

Table 82. STG SYSCONSAIF SYSCFG 328 Register Description
Offset	0x148
Default	0x0
Bit	Name	Access	Default	Description
[19:0]	u0_plda_pcie_pf3_offset	WR	0x0
[21:20]	u0_plda_pcie_phy_mode	WR	0x0
[22]	u0_plda_pcie_pl_clkrem_allow	WR	0x0
[23]	u0_plda_pcie_pl_clkreq_oen	RO	0x0
[25:24]	u0_plda_pcie_pl_equ_phase	RO	0x0
[30:26]	u0_plda_pcie_pl_ltssm	RO	0x0
[31]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 332

Table 83. STG SYSCONSAIF SYSCFG 332 Register Description
Offset	0x14c
Default	0x0
Bit	Name	Access	Default	Description
[4:0]	u0_plda_pcie_pl_pclk_rate	RO	0x0
[31:5]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 336

Table 84. SYS_SYSCONSAIF__SYSCFG_0 Register Description
Offset	0x150
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_pl_sideband_in_31_0_	WR	0x0

STG SYSCONSAIF SYSCFG 340

Table 85. STG SYSCONSAIF SYSCFG 340 Register Description
Offset	0x154
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_pl_sideband_in_63_32_	WR	0x0

STG SYSCONSAIF SYSCFG 344

Table 86. STG SYSCONSAIF SYSCFG 344 Register Description
Offset	0x158
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_pl_sideband_out_31_0_	RO	0x0

STG SYSCONSAIF SYSCFG 348

Table 87. STG SYSCONSAIF SYSCFG 348 Register Description
Offset	0x15c
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_pl_sideband_out_63_32_	RO	0x0

STG SYSCONSAIF SYSCFG 352

Table 88. SYS_SYSCONSAIF__SYSCFG_0 Register Description
Offset	0x160
Default	0x1
Bit	Name	Access	Default	Description
[0]	u0_plda_pcie_pl_wake_in	WR	0x1
[1]	u0_plda_pcie_pl_wake_oen	RO	0x0
[2]	u0_plda_pcie_rx_standby_o	RO	0x0
[31:3]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 356

Table 89. STG SYSCONSAIF SYSCFG 356 Register Description
Offset	0x164
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_test_in_31_0_	WR	0x0

STG SYSCONSAIF SYSCFG 360

Table 90. STG SYSCONSAIF SYSCFG 360 Register Description
Offset	0x168
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_test_in_63_32_	WR	0x0

STG SYSCONSAIF SYSCFG 364

Table 91. STG SYSCONSAIF SYSCFG 364 Register Description
Offset	0x16c
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_test_out_bridge_31_0_	RO	0x0

STG SYSCONSAIF SYSCFG 368

Table 92. STG SYSCONSAIF SYSCFG 368 Register Description
Offset	0x170
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_test_out_bridge_63_32_	RO	0x0

STG SYSCONSAIF SYSCFG 372

Table 93. STG SYSCONSAIF SYSCFG 372 Register Description
Offset	0x174
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_test_out_bridge_95_64_	RO	0x0

STG SYSCONSAIF SYSCFG 376

Table 94. STG SYSCONSAIF SYSCFG 376 Register Description
Offset	0x178
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_test_out_bridge_127_96_	RO	0x0

STG SYSCONSAIF SYSCFG 380

Table 95. STG SYSCONSAIF SYSCFG 380 Register Description
Offset	0x17c
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_test_out_bridge_159_128_	RO	0x0

STG SYSCONSAIF SYSCFG 384

Table 96. STG SYSCONSAIF SYSCFG 384 Register Description
Offset	0x180
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_test_out_bridge_191_160_	RO	0x0

STG SYSCONSAIF SYSCFG 388

Table 97. STG SYSCONSAIF SYSCFG 388 Register Description
Offset	0x184
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_test_out_bridge_223_192_	RO	0x0

STG SYSCONSAIF SYSCFG 392

Table 98. STG SYSCONSAIF SYSCFG 392 Register Description
Offset	0x188
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_test_out_bridge_255_224_	RO	0x0

STG SYSCONSAIF SYSCFG 396

Table 99. STG SYSCONSAIF SYSCFG 396 Register Description
Offset	0x18c
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_test_out_bridge_287_256_	RO	0x0

STG SYSCONSAIF SYSCFG 400

Table 100. STG SYSCONSAIF SYSCFG 400 Register Description
Offset	0x190
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_test_out_bridge_319_288_	RO	0x0

STG SYSCONSAIF SYSCFG 404

Table 101. STG SYSCONSAIF SYSCFG 404 Register Description
Offset	0x198
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_test_out_bridge_383_352_	RO	0x0

STG SYSCONSAIF SYSCFG 408

Table 102. STG SYSCONSAIF SYSCFG 408 Register Description
Offset	0x198
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_test_out_bridge_383_352_	RO	0x0

STG SYSCONSAIF SYSCFG 412

Table 103. STG SYSCONSAIF SYSCFG 412 Register Description
Offset	0x19c
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_test_out_bridge_415_384_	RO	0x0

STG SYSCONSAIF SYSCFG 416

Table 104. STG SYSCONSAIF SYSCFG 416 Register Description
Offset	0x1a0
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_test_out_bridge_447_416_	RO	0x0

STG SYSCONSAIF SYSCFG 420

Table 105. STG SYSCONSAIF SYSCFG 420 Register Description
Offset	0x1a4
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_test_out_bridge_479_448_	RO	0x0

STG SYSCONSAIF SYSCFG 424

Table 106. STG SYSCONSAIF SYSCFG 424 Register Description
Offset	0x1a8
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_test_out_bridge_511_480_	RO	0x0

STG SYSCONSAIF SYSCFG 428

Table 107. STG SYSCONSAIF SYSCFG 428 Register Description
Offset	0x1ac
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_test_out_pcie_31_0_	RO	0x0

STG SYSCONSAIF SYSCFG 432

Table 108. STG SYSCONSAIF SYSCFG 432 Register Description
Offset	0x1b0
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_test_out_pcie_63_32_	RO	0x0

STG SYSCONSAIF SYSCFG 436

Table 109. STG SYSCONSAIF SYSCFG 436 Register Description
Offset	0x1b0
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_test_out_pcie_63_32_	RO	0x0

STG SYSCONSAIF SYSCFG 440

Table 110. STG SYSCONSAIF SYSCFG 440 Register Description
Offset	0x1b8
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_test_out_pcie_127_96_	RO	0x0

STG SYSCONSAIF SYSCFG 444

Table 111. STG SYSCONSAIF SYSCFG 444 Register Description
Offset	0x1bc
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_test_out_pcie_159_128_	RO	0x0

STG SYSCONSAIF SYSCFG 448

Table 112. STG SYSCONSAIF SYSCFG 448 Register Description
Offset	0x1c0
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_test_out_pcie_191_160_	RO	0x0

STG SYSCONSAIF SYSCFG 452

Table 113. STG SYSCONSAIF SYSCFG 452 Register Description
Offset	0x1c4
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_test_out_pcie_223_192_	RO	0x0

STG SYSCONSAIF SYSCFG 456

Table 114. STG SYSCONSAIF SYSCFG 456 Register Description
Offset	0x1c8
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_test_out_pcie_255_224_	RO	0x0

STG SYSCONSAIF SYSCFG 460

Table 115. STG SYSCONSAIF SYSCFG 460 Register Description
Offset	0x1cc
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_test_out_pcie_287_256_	RO	0x0

STG SYSCONSAIF SYSCFG 464

Table 116. STG SYSCONSAIF SYSCFG 464 Register Description
Offset	0x1d0
Default	0x0
Bit	Name	Access	Default	Description
31:0]	u0_plda_pcie_test_out_pcie_319_288_	RO	0x0

STG SYSCONSAIF SYSCFG 468

Table 117. STG SYSCONSAIF SYSCFG 468 Register Description
Offset	0x1d4
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_test_out_pcie_351_320_	RO	0x0

STG SYSCONSAIF SYSCFG 472

Table 118. STG SYSCONSAIF SYSCFG 472 Register Description
Offset	0x1d8
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_test_out_pcie_383_352_	RO	0x0

STG SYSCONSAIF SYSCFG 476

Table 119. STG SYSCONSAIF SYSCFG 476 Register Description
Offset	0x1dc
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_test_out_pcie_415_384_	RO	0x0

STG SYSCONSAIF SYSCFG 480

Table 120. STG SYSCONSAIF SYSCFG 480 Register Description
Offset	0x1e0
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_test_out_pcie_447_416_	RO	0x0

STG SYSCONSAIF SYSCFG 484

Table 121. STG SYSCONSAIF SYSCFG 484 Register Description
Offset	0x1e4
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_test_out_pcie_479_448_	RO	0x0

STG SYSCONSAIF SYSCFG 488

Table 122. STG SYSCONSAIF SYSCFG 488 Register Description
Offset	0x1e8
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u0_plda_pcie_test_out_pcie_511_480_	RO	0x0

STG SYSCONSAIF SYSCFG 492

Table 123. STG SYSCONSAIF SYSCFG 492 Register Description
Offset	0x1ec
Default	0xc80
Bit	Name	Access	Default	Description
[0:3]	u0_plda_pcie_test_sel	WR	0x0
[25:4]	u0_plda_pcie_tl_clock_freq	WR	0xc8
[31:26]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 496

Table 124. STG SYSCONSAIF SYSCFG 496 Register Description
Offset	0x1f0
Default	0x0
Bit	Name	Access	Default	Description
[15:0]	u0_plda_pcie_tl_ctrl_hotplug	RO	0x0
[31:16]	u0_plda_pcie_tl_report_hotplug	WR	0x0

STG SYSCONSAIF SYSCFG 500

Table 125. STG SYSCONSAIF SYSCFG 500 Register Description
Offset	0x1f4
Default	0x6aa008
Bit	Name	Access	Default	Description
[1:0]	u0_plda_pcie_tx_pattern	WR	0x0
[2:3]	u0_plda_pcie_usb3_bus_width	WR	0x2
[4]	u0_plda_pcie_usb3_phy_enable	WR	0x0
[6:5]	u0_plda_pcie_usb3_rate	WR	0x0
[7]	u0_plda_pcie_usb3_rx_standby	WR	0x0
[8]	u0_plda_pcie_xwdecerr	RO	0x0
[9]	u0_plda_pcie_xwerrclr	WR	0x0
[10]	u0_plda_pcie_xwslverr	RO	0x0
[22:11]	u0_sec_top_sramcfg	WR	0xd54	SRAM/ROM configuration. [11]: SLP, sleep enable, high active, default is low. [12]: SD, shutdown enable, high active, default is low. [14:13]: RTSEL, timing setting for debug purpose, default is 2’b01 [16:15]: PTSEL, timing setting for debug purpose, default is 2’b01 [18:17]: TRB, timing setting for debug purpose, default is 2’b01 [20:19]: WTSEL, timing setting for debug purpose, default is 2’b01 [21]: VS, timing setting for debug purpose, default is 1’b1 [22]: VG, timing setting for debug purpose, default is 1’b1
[23]	u1_plda_pcie_align_detect	RO	0x0
[31:24]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 504

Table 126. STG SYSCONSAIF SYSCFG 504 Register Description
Offset	0x1f8
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_axi4_mst0_aratomop_31_0_	RO	0x0

STG SYSCONSAIF SYSCFG 508

Table 127. STG SYSCONSAIF SYSCFG 508 Register Description
Offset	0x1fc
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_axi4_mst0_aratomop_63_32_	RO	0x0

STG SYSCONSAIF SYSCFG 512

Table 128. STG SYSCONSAIF SYSCFG 512 Register Description
Offset	0x200
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_axi4_mst0_aratomop_95_64_	RO	0x0

STG SYSCONSAIF SYSCFG 516

Table 129. STG SYSCONSAIF SYSCFG 516 Register Description
Offset	0x204
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_axi4_mst0_aratomop_127_96_	RO	0x0

STG SYSCONSAIF SYSCFG 520

Table 130. STG SYSCONSAIF SYSCFG 520 Register Description
Offset	0x208
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_axi4_mst0_aratomop_159_128_	RO	0x0

STG SYSCONSAIF SYSCFG 524

Table 131. STG SYSCONSAIF SYSCFG 524 Register Description
Offset	0x20c
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_axi4_mst0_aratomop_191_160_	RO	0x0

STG SYSCONSAIF SYSCFG 528

Table 132. STG SYSCONSAIF SYSCFG 528 Register Description
Offset	0x210
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_axi4_mst0_aratomop_223_192_	RO	0x0

STG SYSCONSAIF SYSCFG 532

Table 133. STG SYSCONSAIF SYSCFG 532 Register Description
Offset	0x214
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_axi4_mst0_aratomop_255_224_	RO	0x0

STG SYSCONSAIF SYSCFG 536

Table 134. STG SYSCONSAIF SYSCFG 536 Register Description
Offset	0x218
Default	0x0
Bit	Name	Access	Default	Description
[1:0]	u1_plda_pcie_axi4_mst0_aratomop_257_256_	RO	0x0
[16:2]	u1_plda_pcie_axi4_mst0_arfunc	RO	0x0
[20:17]	u1_plda_pcie_axi4_mst0_arregion	RO	0x0
[31:21]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 540

Table 135. STG SYSCONSAIF SYSCFG 540 Register Description
Offset	0x21c
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_axi4_mst0_aruser_31_0_	RO	0x0

STG SYSCONSAIF SYSCFG 544

Table 136. STG SYSCONSAIF SYSCFG 544 Register Description
Offset	0x220
Default	0x0
Bit	Name	Access	Default	Description
[20:0]	u1_plda_pcie_axi4_mst0_aruser_52_32_	RO	0x0
[31:21]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 548

Table 137. STG SYSCONSAIF SYSCFG 548 Register Description
Offset	0x224
Default	0x0
Bit	Name	Access	Default	Description
[14:0]	u1_plda_pcie_axi4_mst0_awfunc	RO	0x0
[18:15]	u1_plda_pcie_axi4_mst0_awregion	RO	0x0
[19:31]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 552

Table 138. STG SYSCONSAIF SYSCFG 552 Register Description
Offset	0x228
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_axi4_mst0_awuser_31_0_	RO	0x0

STG SYSCONSAIF SYSCFG 556

Table 139. STG SYSCONSAIF SYSCFG 556 Register Description
Offset	0x22c
Default	0x0
Bit	Name	Access	Default	Description
[10:0]	u1_plda_pcie_axi4_mst0_awuser_42_32_	RO	0x0
[18:11]	u1_plda_pcie_axi4_mst0_rderr	WR	0x0
[19:31]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 560

Table 140. STG SYSCONSAIF SYSCFG 560 Register Description
Offset	0x230
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_axi4_mst0_ruser	WR	0x0

STG SYSCONSAIF SYSCFG 564

Table 141. STG SYSCONSAIF SYSCFG 564 Register Description
Offset	0x234
Default	0x0
Bit	Name	Access	Default	Description
[7:0]	u1_plda_pcie_axi4_mst0_wderr	RO	0x0
[8:31]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 568

Table 142. STG SYSCONSAIF SYSCFG 568 Register Description
Offset	0x238
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_axi4_slv0_aratomop_31_0_	WR	0x0

STG SYSCONSAIF SYSCFG 572

Table 143. STG SYSCONSAIF SYSCFG 572 Register Description
Offset	0x23c
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_axi4_slv0_aratomop_63_32_	WR	0x0

STG SYSCONSAIF SYSCFG 576

Table 144. STG SYSCONSAIF SYSCFG 576 Register Description
Offset	0x240
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_axi4_slv0_aratomop_95_64_	WR	0x0

STG SYSCONSAIF SYSCFG 580

Table 145. STG SYSCONSAIF SYSCFG 580 Register Description
Offset	0x244
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_axi4_slv0_aratomop_127_96_	WR	0x0

STG SYSCONSAIF SYSCFG 584

Table 146. STG SYSCONSAIF SYSCFG 584 Register Description
Offset	0x248
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_axi4_slv0_aratomop_159_128_	WR	0x0

STG SYSCONSAIF SYSCFG 588

Table 147. STG SYSCONSAIF SYSCFG 588 Register Description
Offset	0x24c
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_axi4_slv0_aratomop_191_160_	WR	0x0

STG SYSCONSAIF SYSCFG 592

Table 148. STG SYSCONSAIF SYSCFG 592 Register Description
Offset	0x250
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_axi4_slv0_aratomop_223_192_	WR	0x0

STG SYSCONSAIF SYSCFG 596

Table 149. STG SYSCONSAIF SYSCFG 596 Register Description
Offset	0x254
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_axi4_slv0_aratomop_255_224_	WR	0x0

STG SYSCONSAIF SYSCFG 600

Table 150. STG SYSCONSAIF SYSCFG 600 Register Description
Offset	0x258
Default	0x0
Bit	Name	Access	Default	Description
[1:0]	u1_plda_pcie_axi4_slv0_aratomop_257_256_	WR	0x0
[16:2]	u1_plda_pcie_axi4_slv0_arfunc	WR	0x0
[20:17]	u1_plda_pcie_axi4_slv0_arregion	WR	0x0
[31:21]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 604

Table 151. STG SYSCONSAIF SYSCFG 604 Register Description
Offset	0x25c
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_axi4_slv0_aruser_31_0_	WR	0x0

STG SYSCONSAIF SYSCFG 608

Table 152. STG SYSCONSAIF SYSCFG 608 Register Description
Offset	0x260
Default	0x0
Bit	Name	Access	Default	Description
[8:0]	u1_plda_pcie_axi4_slv0_aruser_40_32_	WR	0x0
[23:9]	u1_plda_pcie_axi4_slv0_awfunc	WR	0x0
[27:24]	u1_plda_pcie_axi4_slv0_awregion	WR	0x0
[31:28]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 612

Table 153. STG SYSCONSAIF SYSCFG 612 Register Description
Offset	0x264
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_axi4_slv0_awuser_31_0_	WR	0x0

STG SYSCONSAIF SYSCFG 616

Table 154. STG SYSCONSAIF SYSCFG 616 Register Description
Offset	0x268
Default	0x0
Bit	Name	Access	Default	Description
[8:0]	u1_plda_pcie_axi4_slv0_awuser_40_32_	WR	0x0
[16:9]	u1_plda_pcie_axi4_slv0_rderr	RO	0x0
[31:17]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 620

Table 155. STG SYSCONSAIF SYSCFG 620 Register Description
Offset	0x26c
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_axi4_slv0_ruser	RO	0x0

STG SYSCONSAIF SYSCFG 624

Table 156. STG SYSCONSAIF SYSCFG 624 Register Description
Offset	0x270
Default	0x0
Bit	Name	Access	Default	Description
[7:0]	u1_plda_pcie_axi4_slv0_wderr	WR	0x0
[22:8]	u1_plda_pcie_axi4_slvl_arfunc	WR	0x0
[31:23]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 628

Table 157. STG SYSCONSAIF SYSCFG 628 Register Description
Offset	0x274
Default	0x0
Bit	Name	Access	Default	Description
[14:0]	u1_plda_pcie_axi4_slvl_awfunc	WR	0x0
[16:15]	u1_plda_pcie_bus_width_o	RO	0x0
[17]	u1_plda_pcie_bypass_codec	WR	0x0
[19:18]	u1_plda_pcie_ckref_src	WR	0x0
[21:20]	u1_plda_pcie_clk_sel	WR	0x0
[22]	u1_plda_pcie_clkreq	WR	0x0
[31:23]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 632

Table 158. STG SYSCONSAIF SYSCFG 632 Register Description
Offset	0x278
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_k_phyparam_31_0_	WR	0x0

STG SYSCONSAIF SYSCFG 636

Table 159. STG SYSCONSAIF SYSCFG 636 Register Description
Offset	0x27c
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_k_phyparam_63_32_	WR	0x0

STG SYSCONSAIF SYSCFG 640

Table 160. STG SYSCONSAIF SYSCFG 640 Register Description
Offset	0x280
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_k_phyparam_95_64_	WR	0x0

STG SYSCONSAIF SYSCFG 644

Table 161. STG SYSCONSAIF SYSCFG 644 Register Description
Offset	0x284
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_k_phyparam_127_96_	WR	0x0

STG SYSCONSAIF SYSCFG 648

Table 162. STG SYSCONSAIF SYSCFG 648 Register Description
Offset	0x288
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_k_phyparam_159_128_	WR	0x0

STG SYSCONSAIF SYSCFG 652

Table 163. STG SYSCONSAIF SYSCFG 652 Register Description
Offset	0x28c
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_k_phyparam_191_160_	WR	0x0

STG SYSCONSAIF SYSCFG 656

Table 164. STG SYSCONSAIF SYSCFG 656 Register Description
Offset	0x290
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_k_phyparam_223_192_	WR	0x0

STG SYSCONSAIF SYSCFG 660

Table 165. STG SYSCONSAIF SYSCFG 660 Register Description
Offset	0x294
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_k_phyparam_255_224_	WR	0x0

STG SYSCONSAIF SYSCFG 664

Table 166. STG SYSCONSAIF SYSCFG 664 Register Description
Offset	0x298
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_k_phyparam_287_256_	WR	0x0

STG SYSCONSAIF SYSCFG 668

Table 167. STG SYSCONSAIF SYSCFG 668 Register Description
Offset	0x29c
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_k_phyparam_319_288_	WR	0x0

STG SYSCONSAIF SYSCFG 672

Table 168. STG SYSCONSAIF SYSCFG 672 Register Description
Offset	0x2a0
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_k_phyparam_351_320_	WR	0x0

STG SYSCONSAIF SYSCFG 676

Table 169. STG SYSCONSAIF SYSCFG 676 Register Description
Offset	0x2a4
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_k_phyparam_383_352_	WR	0x0

STG SYSCONSAIF SYSCFG 680

Table 170. STG SYSCONSAIF SYSCFG 680 Register Description
Offset	0x2a8
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_k_phyparam_415_384_	WR	0x0

STG SYSCONSAIF SYSCFG 684

Table 171. STG SYSCONSAIF SYSCFG 684 Register Description
Offset	0x2ac
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_k_phyparam_447_416_	WR	0x0

STG SYSCONSAIF SYSCFG 688

Table 172. STG SYSCONSAIF SYSCFG 688 Register Description
Offset	0x2b0
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_k_phyparam_479_448_	WR	0x0

STG SYSCONSAIF SYSCFG 692

Table 173. STG SYSCONSAIF SYSCFG 692 Register Description
Offset	0x2b4
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_k_phyparam_511_480_	WR	0x0

STG SYSCONSAIF SYSCFG 696

Table 174. STG SYSCONSAIF SYSCFG 696 Register Description
Offset	0x2b8
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_k_phyparam_543_512_	WR	0x0

STG SYSCONSAIF SYSCFG 700

Table 175. STG SYSCONSAIF SYSCFG 700 Register Description
Offset	0x2bc
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_k_phyparam_575_544_	WR	0x0

STG SYSCONSAIF SYSCFG 704

Table 176. STG SYSCONSAIF SYSCFG 704 Register Description
Offset	0x2c0
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_k_phyparam_607_576_	WR	0x0

STG SYSCONSAIF SYSCFG 708

Table 177. STG SYSCONSAIF SYSCFG 708 Register Description
Offset	0x2c4
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_k_phyparam_639_608_	WR	0x0

STG SYSCONSAIF SYSCFG 712

Table 178. STG SYSCONSAIF SYSCFG 712 Register Description
Offset	0x2c8
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_k_phyparam_671_640_	WR	0x0

STG SYSCONSAIF SYSCFG 716

Table 179. STG SYSCONSAIF SYSCFG 716 Register Description
Offset	0x2cc
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_k_phyparam_703_672_	WR	0x0

STG SYSCONSAIF SYSCFG 720

Table 180. STG SYSCONSAIF SYSCFG 720 Register Description
Offset	0x2d0
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_k_phyparam_735_704_	WR	0x0

STG SYSCONSAIF SYSCFG 724

Table 181. STG SYSCONSAIF SYSCFG 724 Register Description
Offset	0x2d4
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_k_phyparam_767_736_	WR	0x0

STG SYSCONSAIF SYSCFG 728

Table 182. STG SYSCONSAIF SYSCFG 728 Register Description
Offset	0x2d8
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_k_phyparam_799_768_	WR	0x0

STG SYSCONSAIF SYSCFG 732

Table 183. STG SYSCONSAIF SYSCFG 732 Register Description
Offset	0x2dc
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_k_phyparam_831_800_	WR	0x0

STG SYSCONSAIF SYSCFG 736

Table 184. STG SYSCONSAIF SYSCFG 736 Register Description
Offset	0x2e0
Default	0x0
Bit	Name	Access	Default	Description
[7:0]	u1_plda_pcie_k_phyparam_839_832_	WR	0x0
[8]	u1_plda_pcie_k_rp_nep	WR	0x0
[9]	u1_plda_pcie_l1sub_entack	RO	0x0
[10]	u1_plda_pcie_l1sub_entreq	WR	0x0
[31:11]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 740

Table 185. STG SYSCONSAIF SYSCFG 740 Register Description
Offset	0x2e4
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_local_interrupt_in	WR	0x0

STG SYSCONSAIF SYSCFG 744

Table 186. STG SYSCONSAIF SYSCFG 744 Register Description
Offset	0x2e8
Default	0x4800001
Bit	Name	Access	Default	Description
[0]	u1_plda_pcie_mperstn	WR	0x1
[1]	u1_plda_pcie_pcie_ebuf_mode	WR	0x0
[24:2]	u1_plda_pcie_pcie_phy_test_cfg	WR	0x200000
[25]	u1_plda_pcie_pcie_rx_eq_training	WR	0x0
[26]	u1_plda_pcie_pcie_rxterm_en	WR	0x1
[27]	u1_plda_pcie_pcie_tx_oneszeros	WR	0x0
[31:28]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 748

Table 187. STG SYSCONSAIF SYSCFG 748 Register Description
Offset	0x2ec
Default	0x0
Bit	Name	Access	Default	Description
[19:0]	u1_plda_pcie_pf0_offset	WR	0x0
[31:20]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 752

Table 188. STG SYSCONSAIF SYSCFG 752 Register Description
Offset	0x2f0
Default	0x0
Bit	Name	Access	Default	Description
[19:0]	u1_plda_pcie_pf1_offset	WR	0x0
[31:20]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 756

Table 189. STG SYSCONSAIF SYSCFG 756 Register Description
Offset	0x2f4
Default	0x0
Bit	Name	Access	Default	Description
[19:0]	u1_plda_pcie_pf2_offset	WR	0x0
[31:20]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 760

Table 190. STG SYSCONSAIF SYSCFG 760 Register Description
Offset	0x2f8
Default	0x0
Bit	Name	Access	Default	Description
[19:0]	u1_plda_pcie_pf3_offset	WR	0x0
[21:20]	u1_plda_pcie_phy_mode	WR	0x0
[22]	u1_plda_pcie_pl_clkrem_allow	WR	0x0
[23]	u1_plda_pcie_pl_clkreq_oen	RO	0x0
[25:24]	u1_plda_pcie_pl_equ_phase	RO	0x0
[30:26]	u1_plda_pcie_pl_ltssm	RO	0x0
[31]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 764

Table 191. STG SYSCONSAIF SYSCFG 764 Register Description
Offset	0x2fc
Default	0x0
Bit	Name	Access	Default	Description
[4:0]	u1_plda_pcie_pl_pclk_rate	RO	0x0
[31:5]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 768

Table 192. STG SYSCONSAIF SYSCFG 768 Register Description
Offset	0x300
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_pl_sideband_in_31_0_	WR	0x0

STG SYSCONSAIF SYSCFG 772

Table 193. STG SYSCONSAIF SYSCFG 772 Register Description
Offset	0x304
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_pl_sideband_in_63_32_	WR	0x0

STG SYSCONSAIF SYSCFG 776

Table 194. STG SYSCONSAIF SYSCFG 776 Register Description
Offset	0x308
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_pl_sideband_out_31_0_	RO	0x0

STG SYSCONSAIF SYSCFG 780

Table 195. STG SYSCONSAIF SYSCFG 780 Register Description
Offset	0x30c
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_pl_sideband_out_63_32_	RO	0x0

STG SYSCONSAIF SYSCFG 784

Table 196. STG SYSCONSAIF SYSCFG 784 Register Description
Offset	0x310
Default	0x1
Bit	Name	Access	Default	Description
[0]	u1_plda_pcie_pl_wake_in	WR	0x1
[1]	u1_plda_pcie_pl_wake_oen	RO	0x0
[2]	u1_plda_pcie_rx_standby_o	RO	0x0
[31:3]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 788

Table 197. STG SYSCONSAIF SYSCFG 788 Register Description
Offset	0x314
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_test_in_31_0_	WR	0x0

STG SYSCONSAIF SYSCFG 792

Table 198. STG SYSCONSAIF SYSCFG 792 Register Description
Offset	0x318
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_test_in_63_32_	WR	0x0

STG SYSCONSAIF SYSCFG 796

Table 199. STG SYSCONSAIF SYSCFG 796 Register Description
Offset	0x31c
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_test_out_bridge_31_0_	RO	0x0

STG SYSCONSAIF SYSCFG 800

Table 200. STG SYSCONSAIF SYSCFG 800 Register Description
Offset	0x320
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_test_out_bridge_63_32_	RO	0x0

STG SYSCONSAIF SYSCFG 804

Table 201. STG SYSCONSAIF SYSCFG 804 Register Description
Offset	0x324
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_test_out_bridge_95_64_	RO	0x0

STG SYSCONSAIF SYSCFG 808

Table 202. STG SYSCONSAIF SYSCFG 808 Register Description
Offset	0x328
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_test_out_bridge_127_96_	RO	0x0

STG SYSCONSAIF SYSCFG 812

Table 203. STG SYSCONSAIF SYSCFG 812 Register Description
Offset	0x32c
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_test_out_bridge_159_128_	RO	0x0

STG SYSCONSAIF SYSCFG 816

Table 204. STG SYSCONSAIF SYSCFG 816 Register Description
Offset	0x330
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_test_out_bridge_191_160_	RO	0x0

STG SYSCONSAIF SYSCFG 820

Table 205. STG SYSCONSAIF SYSCFG 820 Register Description
Offset	0x334
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_test_out_bridge_223_192_	RO	0x0

STG SYSCONSAIF SYSCFG 824

Table 206. STG SYSCONSAIF SYSCFG 824 Register Description
Offset	0x338
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_test_out_bridge_255_224_	RO	0x0

STG SYSCONSAIF SYSCFG 828

Table 207. STG SYSCONSAIF SYSCFG 828 Register Description
Offset	0x33c
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_test_out_bridge_287_256_	RO	0x0

STG SYSCONSAIF SYSCFG 832

Table 208. STG SYSCONSAIF SYSCFG 832 Register Description
Offset	0x340
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_test_out_bridge_319_288_	RO	0x0

STG SYSCONSAIF SYSCFG 836

Table 209. STG SYSCONSAIF SYSCFG 836 Register Description
Offset	0x344
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_test_out_bridge_351_320_	RO	0x0

STG SYSCONSAIF SYSCFG 840

Table 210. STG SYSCONSAIF SYSCFG 840 Register Description
Offset	0x348
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_test_out_bridge_383_352_	RO	0x0

STG SYSCONSAIF SYSCFG 844

Table 211. STG SYSCONSAIF SYSCFG 844 Register Description
Offset	0x34c
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_test_out_bridge_415_384_	RO	0x0

STG SYSCONSAIF SYSCFG 848

Table 212. STG SYSCONSAIF SYSCFG 848 Register Description
Offset	0x350
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_test_out_bridge_447_416_	RO	0x0

STG SYSCONSAIF SYSCFG 852

Table 213. STG SYSCONSAIF SYSCFG 852 Register Description
Offset	0x354
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_test_out_bridge_479_448_	RO	0x0

STG SYSCONSAIF SYSCFG 856

Table 214. STG SYSCONSAIF SYSCFG 856 Register Description
Offset	0x358
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_test_out_bridge_511_480_	RO	0x0

STG SYSCONSAIF SYSCFG 860

Table 215. STG SYSCONSAIF SYSCFG 860 Register Description
Offset	0x35c
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_test_out_pcie_31_0_	RO	0x0

STG SYSCONSAIF SYSCFG 864

Table 216. STG SYSCONSAIF SYSCFG 864 Register Description
Offset	0x360
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_test_out_pcie_63_32_	RO	0x0

STG SYSCONSAIF SYSCFG 868

Table 217. STG SYSCONSAIF SYSCFG 868 Register Description
Offset	0x364
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_test_out_pcie_95_64_	RO	0x0

STG SYSCONSAIF SYSCFG 872

Table 218. STG SYSCONSAIF SYSCFG 872 Register Description
Offset	0x368
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_test_out_pcie_127_96_	RO	0x0

STG SYSCONSAIF SYSCFG 876

Table 219. STG SYSCONSAIF SYSCFG 876 Register Description
Offset	0x36c
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_test_out_pcie_159_128_	RO	0x0

STG SYSCONSAIF SYSCFG 880

Table 220. STG SYSCONSAIF SYSCFG 880 Register Description
Offset	0x370
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_test_out_pcie_191_160_	RO	0x0

STG SYSCONSAIF SYSCFG 884

Table 221. STG SYSCONSAIF SYSCFG 884 Register Description
Offset	0x374
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_test_out_pcie_223_192_	RO	0x0

STG SYSCONSAIF SYSCFG 888

Table 222. STG SYSCONSAIF SYSCFG 888 Register Description
Offset	0x378
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_test_out_pcie_255_224_	RO	0x0

STG SYSCONSAIF SYSCFG 892

Table 223. STG SYSCONSAIF SYSCFG 892 Register Description
Offset	0x37c
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_test_out_pcie_287_256_	RO	0x0

STG SYSCONSAIF SYSCFG 896

Table 224. STG SYSCONSAIF SYSCFG 896 Register Description
Offset	0x380
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_test_out_pcie_319_288_	RO	0x0

STG SYSCONSAIF SYSCFG 900

Table 225. STG SYSCONSAIF SYSCFG 900 Register Description
Offset	0x384
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_test_out_pcie_351_320_	RO	0x0

STG SYSCONSAIF SYSCFG 904

Table 226. STG SYSCONSAIF SYSCFG 904 Register Description
Offset	0x388
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_test_out_pcie_383_352_	RO	0x0

STG SYSCONSAIF SYSCFG 908

Table 227. STG SYSCONSAIF SYSCFG 908 Register Description
Offset	0x38c
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_test_out_pcie_415_384_	RO	0x0

STG SYSCONSAIF SYSCFG 912

Table 228. STG SYSCONSAIF SYSCFG 912 Register Description
Offset	0x390
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_test_out_pcie_447_416_	RO	0x0

STG SYSCONSAIF SYSCFG 916

Table 229. STG SYSCONSAIF SYSCFG 916 Register Description
Offset	0x394
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_test_out_pcie_479_448_	RO	0x0

STG SYSCONSAIF SYSCFG 920

Table 230. STG SYSCONSAIF SYSCFG 920 Register Description
Offset	0x398
Default	0x0
Bit	Name	Access	Default	Description
[0:31]	u1_plda_pcie_test_out_pcie_511_480_	RO	0x0

STG SYSCONSAIF SYSCFG 924

Table 231. STG SYSCONSAIF SYSCFG 924 Register Description
Offset	0x39c
Default	0xc80
Bit	Name	Access	Default	Description
[0:3]	u1_plda_pcie_test_sel	WR	0x0
[25:4]	u1_plda_pcie_tl_clock_freq	WR	0xc8
[31:26]	Reserved	None	0x0	Reserved

STG SYSCONSAIF SYSCFG 928

Table 232. STG SYSCONSAIF SYSCFG 928 Register Description
Offset	0x3a0
Default	0x0
Bit	Name	Access	Default	Description
[15:0]	u1_plda_pcie_tl_ctrl_hotplug	RO	0x0
[31:16]	u1_plda_pcie_tl_report_hotplug	WR	0x0

STG SYSCONSAIF SYSCFG 932

Table 233. STG SYSCONSAIF SYSCFG 932 Register Description
Offset	0x3a4
Default	0x8
Bit	Name	Access	Default	Description
[1:0]	u1_plda_pcie_tx_pattern	WR	0x0
[2:3]	u1_plda_pcie_usb3_bus_width	WR	0x2
[4]	u1_plda_pcie_usb3_phy_enable	WR	0x0
[6:5]	u1_plda_pcie_usb3_rate	WR	0x0
[7]	u1_plda_pcie_usb3_rx_standby	WR	0x0
[8]	u1_plda_pcie_xwdecerr	RO	0x0
[9]	u1_plda_pcie_xwerrclr	WR	0x0
[10]	u1_plda_pcie_xwslverr	RO	0x0
[31:11]	Reserved	None	0x0	Reserved