SYS CRG

Clock CPU Root

Table 1. Clock CPU Root Register Description
Offset	16’h0
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	clk_mux_sel	6’d0	Clock multiplexing selector: clk_osc clk_pll0
[0:23]	Reserved	0	Reserved

Clock CPU Core

Table 2. Clock CPU Core Register Description
Offset	16’h4
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d1	Clock divider coefficient: Max: 7 Default: 1 Min: 1 Typical: 1

Clock CPU Bus

Table 3. Clock CPU Bus Register Description
Offset	16’h8
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d2	Clock divider coefficient: Max: 2 Default: 2 Min: 2 Typical: 2

Clock GPU Root

Table 4. Clock GPU Root Register Description
Offset	16’hc
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	clk_mux_sel	6’d0	Clock multiplexing selector: clk_pll2 clk_pll1
[0:23]	Reserved	0	Reserved

Clock Peripheral Root

Table 5. Clock Peripheral Root Register Description
Offset	16’h10
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	clk_mux_sel	6’d0	Clock multiplexing selector: clk_pll0 clk_pll2
[0:23]	clk_divcfg	24’d2	Clock divider coefficient: Max: 2 Default: 2 Min: 2 Typical: 2

Clock Bus Root

Table 6. Clock Bus Root Register Description
Offset	16’h14
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	clk_mux_sel	6’d0	Clock multiplexing selector: clk_osc clk_pll2
[0:23]	Reserved	0	Reserved

clk_nocstg_bus

Table 7. clk_nocstg_bus Register Description
Offset	16’h18
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d3	Clock divider coefficient: Max: 3 Default: 3 Min: 3 Typical: 3

Clock AXI Configuration 0

Table 8. Clock AXI Configuration 0 Register Description
Offset	16’h1c
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d3	Clock divider coefficient: Max: 3 Default: 3 Min: 3 Typical: 3

clk_stg_axiahb

Table 9. clk_stg_axiahb Register Description
Offset	16’h20
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d2	Clock divider coefficient: Max: 2 Default: 2 Min: 2 Typical: 2

Clock AHB 0

Table 10. Clock AHB 0 Register Description
Offset	16’h24
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock AHB 1

Table 11. Clock AHB 1 Register Description
Offset	16’h28
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock APB Bus Function

Table 12. Clock APB Bus Function Register Description
Offset	16’h2c
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d4	Clock divider coefficient: Max: 8 Default: 4 Min: 4 Typical: 4

Clock APB 0

Table 13. Clock APB 0 Register Description
Offset	16’h30
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock PLL 0 Divider 2

Table 14. Clock PLL 0 Divider 2 Register Description
Offset	16’h34
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d2	Clock divider coefficient: Max: 2 Default: 2 Min: 2 Typical: 2

Clock PLL 1 Divider 2

Table 15. Clock PLL 1 Divider 2 Register Description
Offset	16’h38
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d2	Clock divider coefficient: Max: 2 Default: 2 Min: 2 Typical: 2

Clock PLL 2 Divider 2

Table 16. Clock PLL 2 Divider 2 Register Description
Offset	16’h3c
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d2	Clock divider coefficient: Max: 2 Default: 2 Min: 2 Typical: 2

Clock Audio Root

Table 17. Clock Audio Root Register Description
Offset	16’h40
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d2	Clock divider coefficient: Max: 8 Default: 2 Min: 2 Typical: 2

Clock MCLK Inner

Table 18. Clock MCLK Inner Register Description
Offset	16’h44
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d12	Clock divider coefficient: Max: 64 Default: 12 Min: 12 Typical: 12

Clock MCLK

Table 19. Clock MCLK Register Description
Offset	16’h48
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	clk_mux_sel	6’d0	Clock multiplexing selector: clk_mclk_inner clk_mclk_ext
[0:23]	Reserved	0	Reserved

MCLK Out

Table 20. MCLK Out Register Description
Offset	16’h4c
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock ISP 2x

Table 21. Clock ISP 2x Register Description
Offset	16’h50
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	clk_mux_sel	6’d0	Clock multiplexing selector: clk_pll2 clk_pll1
[0:23]	clk_divcfg	24’d2	Clock divider coefficient: Max: 8 Default: 2 Min: 2 Typical: 2

Clock ISP AXI

Table 22. Clock ISP AXI Register Description
Offset	16’h54
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d2	Clock divider coefficient: Max: 4 Default: 2 Min: 2 Typical: 2

Clock GCLK 0

Table 23. Clock GCLK 0 Register Description
Offset	16’h58
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d20	Clock divider coefficient: Max: 62 Default: 20 Min: 16 Typical: 20

Clock GCLK 1

Table 24. Clock GCLK 1 Register Description
Offset	16’h5c
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d16	Clock divider coefficient: Max: 62 Default: 16 Min: 16 Typical: 16

Clock GCLK 2

Table 25. Clock GCLK 2 Register Description
Offset	16’h60
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d12	Clock divider coefficient: Max: 62 Default: 12 Min: 12 Typical: 12

U7MC Core Clock

Table 26. U7MC Core Clock Register Description
Offset	16’h64
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U7MC Core Clock 1

Table 27. U7MC Core Clock 1 Register Description
Offset	16’h68
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U7MC Core Clock 2

Table 28. U7MC Core Clock 2 Register Description
Offset	16’h6c
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U7MC Core Clock 3

Table 29. U7MC Core Clock 3 Register Description
Offset	16’h70
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U7MC Core Clock 4

Table 30. U7MC Core Clock 4 Register Description
Offset	16’h74
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U7MC Debug Clock

Table 31. U7MC Debug Clock Register Description
Offset	16’h78
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U7MC RTC Toggle

Table 32. U7MC RTC Toggle Register Description
Offset	16’h7c
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d6	Clock divider coefficient: Max: 6 Default: 6 Min: 6 Typical: 6

U7MC Trace Clock 0

Table 33. U7MC Trace Clock 0 Register Description
Offset	16’h80
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U7MC Trace Clock 1

Table 34. U7MC Trace Clock 1 Register Description
Offset	16’h84
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U7MC Trace Clock 2

Table 35. U7MC Trace Clock 2 Register Description
Offset	16’h88
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U7MC Trace Clock 3

Table 36. U7MC Trace Clock 3 Register Description
Offset	16’h8c
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U7MC Trace Clock 4

Table 37. U7MC Trace Clock 4 Register Description
Offset	16’h90
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U7MC Trace COM Clock

Table 38. U7MC Trace COM Clock Register Description
Offset	16’h94
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

clk_u0_sft7110_noc_bus_clk_cpu_axi

Table 39. clk_u0_sft7110_noc_bus_clk_cpu_axi Register Description
Offset	16’h98
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

clk_u0_sft7110_noc_bus_clk_axicfg0_axi

Table 40. clk_u0_sft7110_noc_bus_clk_axicfg0_axi Register Description
Offset	16’h9c
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

clk_osc_div2

Table 41. clk_osc_div2 Register Description
Offset	16’ha0
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d2	Clock divider coefficient: Max: 2 Default: 2 Min: 2 Typical: 2

clk_pll1_div4

Table 42. clk_pll1_div4 Register Description
Offset	16’ha4
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d2	Clock divider coefficient: Max: 2 Default: 2 Min: 2 Typical: 2

clk_pll1_div8

Table 43. clk_pll1_div8 Register Description
Offset	16’ha8
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d2	Clock divider coefficient: Max: 2 Default: 2 Min: 2 Typical: 2

clk_ddr_bus

Table 44. clk_ddr_bus Register Description
Offset	16’hac
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	clk_mux_sel	6’d0	Clock multiplexing selector: clk_osc_div2 clk_pll1_div4 clk_pll1_div8
[0:23]	Reserved	0	Reserved

clk_u0_ddr_sft7110_clk_axi

Table 45. clk_u0_ddr_sft7110_clk_axi Register Description
Offset	16’hb0
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

clk_gpu_core

Table 46. clk_gpu_core Register Description
Offset	16’hb4
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d3	Clock divider coefficient: Max: 7 Default: 3 Min: 3 Typical: 3

clk_u0_img_gpu_core_clk

Table 47. clk_u0_img_gpu_core_clk Register Description
Offset	16’hb8
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

clk_u0_img_gpu_sys_clk

Table 48. clk_u0_img_gpu_sys_clk Register Description
Offset	16’hbc
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

clk_u0_img_gpu_clk_apb

Table 49. clk_u0_img_gpu_clk_apb Register Description
Offset	16’hc0
Access	RW
Bit	Name	Default	Description
31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

clk_u0_img_gpu_rtc_toggle

Table 50. clk_u0_img_gpu_rtc_toggle Register Description
Offset	16’hc4
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d12	Clock divider coefficient: Max: 12 Default: 12 Min: 12 Typical: 12

clk_u0_sft7110_noc_bus_clk_gpu_axi

Table 51. clk_u0_sft7110_noc_bus_clk_gpu_axi Register Description
Offset	16’hc8
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x

Table 52. clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x Register Description
Offset	16’hcc
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi

Table 53. clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi Register Description
Offset	16’hd0
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

clk_u0_sft7110_noc_bus_clk_isp_axi

Table 54. clk_u0_sft7110_noc_bus_clk_isp_axi Register Description
Offset	16’hd4
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

clk_hifi4_core

Table 55. clk_hifi4_core Register Description
Offset	16’hd8
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d3	Clock divider coefficient: Max: 15 Default: 3 Min: 3 Typical: 3

clk_hifi4_axi

Table 56. clk_hifi4_axi Register Description
Offset	16’hdc
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d2	Clock divider coefficient: Max: 2 Default: 2 Min: 2 Typical: 2

clk_u0_axi_cfg1_dec_clk_main

Table 57. clk_u0_axi_cfg1_dec_clk_main Register Description
Offset	16’he0
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

clk_u0_axi_cfg1_dec_clk_ahb

Table 58. clk_u0_axi_cfg1_dec_clk_ahb Register Description
Offset	16’he4
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src

Table 59. clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src Register Description
Offset	16’he8
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock Video Output AXI

Table 60. Clock Video Output AXI Register Description
Offset	16’hec
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d2	Clock divider coefficient: Max: 7 Default: 2 Min: 2 Typical: 2

Clock NOC Display AXI

Table 61. Clock NOC Display AXI Register Description
Offset	16’hf0
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock Video Output AHB

Table 62. Clock Video Output AHB Register Description
Offset	16’hf4
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock Video Output AXI

Table 63. Clock Video Output AXI Register Description
Offset	16’hf8
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock Video Output HDMI TX0 MCLK

Table 64. Clock Video Output HDMI TX0 MCLK Register Description
Offset	16’hfc
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock Video Output MIPI PHY Reference

Table 65. Clock Video Output MIPI PHY Reference Register Description
Offset	16’h100
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d2	Clock divider coefficient: Max: 2 Default: 2 Min: 2 Typical: 2

Clock JPEG Codec AXI

Table 66. Clock JPEG Codec AXI Register Description
Offset	16’h104
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d6	Clock divider coefficient: Max: 16 Default: 6 Min: 6 Typical: 6

CODAJ12 Clock AXI

Table 67. CODAJ12 Clock AXI Register Description
Offset	16’h108
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

CODAJ12 Clock Core

Table 68. CODAJ12 Clock Core Register Description
Offset	16’h10c
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d6	Clock divider coefficient: Max: 16 Default: 6 Min: 6 Typical: 6

CODAJ12 Clock APB

Table 69. CODAJ12 Clock APB Register Description
Offset	16’h110
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock Video Decoder AXI

Table 70. Clock Video Decoder AXI Register Description
Offset	16’h114
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d3	Clock divider coefficient: Max: 7 Default: 3 Min: 3 Typical: 3

Clock WAVE511 AXI

Table 71. Clock WAVE511 AXI Register Description
Offset	16’h118
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock WAVE511 BPU

Table 72. Clock WAVE511 BPU Register Description
Offset	16’h11c
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d3	Clock divider coefficient: Max: 7 Default: 3 Min: 3 Typical: 3

Clock WAVE511 VCE

Table 73. Clock WAVE511 VCE Register Description
Offset	16’h120
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d2	Clock divider coefficient: Max: 7 Default: 2 Min: 3 Typical: 2

Clock WAVE511 APB

Table 74. Clock WAVE511 APB Register Description
Offset	16’h124
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock Video Decoder JPG ARB

Table 75. Clock Video Decoder JPG ARB Register Description
Offset	16’h128
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock Video Decoder JPG Main

Table 76. Clock Video Decoder JPG Main Register Description
Offset	16’h12c
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock NOC Video Decoder AXI

Table 77. Clock NOC Video Decoder AXI Register Description
Offset	16’h130
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock Video Encoder AXI

Table 78. Clock Video Encoder AXI Register Description
Offset	16’h134
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d5	Clock divider coefficient: Max: 15 Default: 5 Min: 5 Typical: 5

Clock WAVE420L AXI

Table 79. Clock WAVE420L AXI Register Description
Offset	16’h138
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock WAVE420L BPU

Table 80. Clock WAVE420L BPU Register Description
Offset	16’h13c
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d5	Clock divider coefficient: Max: 15 Default: 5 Min: 5 Typical: 5

Clock WAVE420L VCE

Table 81. Clock WAVE420L VCE Register Description
Offset	16’h140
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d5	Clock divider coefficient: Max: 15 Default: 5 Min: 5 Typical: 5

Clock WAVE420L APB

Table 82. Clock WAVE420L APB Register Description
Offset	16’h144
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock NOC Video Encoder AXI

Table 83. Clock NOC Video Encoder AXI Register Description
Offset	16’h148
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock AXI Config 0 DEC Main Divider

Table 84. Clock AXI Config 0 DEC Main Divider Register Description
Offset	16’h14c
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock AXI Config 0 DEC Main

Table 85. Clock AXI Config 0 DEC Main Register Description
Offset	16’h150
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock AXI Config 0 DEC HIFI4

Table 86. Clock AXI Config 0 DEC HIFI4 Register Description
Offset	16’h154
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock AXIMEM 128B AXI

Table 87. Clock AXIMEM 128B AXI Register Description
Offset	16’h158
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

QSPI Clock AHB

Table 88. QSPI Clock AHB Register Description
Offset	16’h15c
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

QSPI Clock APB

Table 89. QSPI Clock APB Register Description
Offset	16’h160
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock QSPI Reference Source

Table 90. Clock QSPI Reference Source Register Description
Offset	16’h164
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d10	Clock divider coefficient: Max: 16 Default: 10 Min: 10 Typical: 10

QSPI Clock Reference

Table 91. QSPI Clock Reference Register Description
Offset	16’h168
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	clk_mux_sel	6’d0	Clock multiplexing selector: clk_osc clk_qspi_ref_src
[0:23]	Reserved	0	Reserved

U0 SD Clock AHB

Table 92. U0 SD Clock AHB Register Description
Offset	16’h16c
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U1 SD Clock AHB

Table 93. U1 SD Clock AHB Register Description
Offset	16’h170
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U0 SD Card Clock

Table 94. U0 SD Card Clock Register Description
Offset	16’h174
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d2	Clock divider coefficient: Max: 15 Default: 2 Min: 2 Typical: 2

U1 SD Card Clock

Table 95. U1 SD Card Clock Register Description
Offset	16’h178
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d2	Clock divider coefficient: Max: 15 Default: 2 Min: 2 Typical: 2

Clock USB 125M

Table 96. Clock USB 125M Register Description
Offset	16’h17c
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d8	Clock divider coefficient: Max: 15 Default: 8 Min: 12 Typical: 10

Clock NOC STG AXI

Table 97. Clock NOC STG AXI Register Description
Offset	16’h180
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock GMAC 5 AXI 64 AHB

Table 98. Clock GMAC 5 AXI 64 AHB Register Description
Offset	16’h184
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock GMAC 5 AXI 64 AXI

Table 99. Clock GMAC 5 AXI 64 AXI Register Description
Offset	16’h188
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock GMAC Source

Table 100. Clock GMAC Source Register Description
Offset	16’h18c
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d2	Clock divider coefficient: Max: 7 Default: 2 Min: 2 Typical: 2

Clock GMAC 1 GTX

Table 101. Clock GMAC 1 GTX Register Description
Offset	16’h190
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d8	Clock divider coefficient: Max: 15 Default: 8 Min: 12 Typical: 10

Clock GMAC 1 RMII RTX

Table 102. Clock GMAC 1 RMII RTX Register Description
Offset	16’h194
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d2	Clock divider coefficient: Max: 30 Default: 2 Min: 2 Typical: 2

Clock GMAC 5 AXI 64 PTP

Table 103. Clock GMAC 5 AXI 64 PTP Register Description
Offset	16’h198
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d10	Clock divider coefficient: Max: 31 Default: 10 Min: 15 Typical: 10

Clock GMAC 5 AXI 64 RX

Table 104. Clock GMAC 5 AXI 64 RX Register Description
Offset	16’h19c
Access	RW
Bit	Name	Default	Description
[31:24]	reserverd	0x0	Reserved
[23: 0]	dly_chain_sel	0x0	Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, dly_chain_sel=1 means to delay 1 stage.

Clock GMAC 5 AXI 64 RX Inverter

Table 105. Clock GMAC 5 AXI 64 RX Inverter Register Description
Offset	16’h1a0
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	clk_polarity	1	1: Clock inverter 0: Clock buffer
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock GMAC 5 AXI 64 TX

Table 106. Clock GMAC 5 AXI 64 TX Register Description
Offset	16’h1a4
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	clk_mux_sel	6’d0	Clock multiplexing selector: clk_gmac1_gtxclk clk_gmac1_rmii_rtx
[0:23]	Reserved	0	Reserved

Clock GMAC 5 AXI 64 TX Inverter

Table 107. Clock GMAC 5 AXI 64 TX Inverter Register Description
Offset	16’h1a8
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	clk_polarity	1	1: Clock inverter 0: Clock buffer
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock GMAC 1 GTXC

Table 108. Clock GMAC 1 GTXC Register Description
Offset	16’h1ac
Access	RW
Bit	Name	Default	Description
[31:24]	reserverd	0x0	Reserved
[23: 0]	dly_chain_sel	0x0	Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, dly_chain_sel=1 means to delay 1 stage.

Clock GMAC 0 GTX

Table 109. Clock GMAC 0 GTX Register Description
Offset	16’h1b0
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d8	Clock divider coefficient: Max: 15 Default: 8 Min: 12 Typical: 10

Clock GMAC 0 PTP

Table 110. Clock GMAC 0 PTP Register Description
Offset	16’h1b4
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d10	Clock divider coefficient: Max: 31 Default: 10 Min: 15 Typical: 25

Clock GMAC PHY

Table 111. Clock GMAC PHY Register Description
Offset	16’h1b8
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d10	Clock divider coefficient: Max: 31 Default: 10 Min: 15 Typical: 25

Clock GMAC 0 GTXC

Table 112. Clock GMAC 0 GTXC Register Description
Offset	16’h1bc
Access	RW
Bit	Name	Default	Description
[31:24]	reserverd	0x0	Reserved
[23: 0]	dly_chain_sel	0x0	Selector delay chain stage number, totally 32 stages, -50ps each stage. The register value indicates the delay chain stage number. For example, dly_chain_sel=1 means to delay 1 stage.

Clock SYS IOMUX PCLK

Table 113. Clock SYS IOMUX PCLK Register Description
Offset	16’h1c0
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock Mailbox APB

Table 114. Clock Mailbox APB Register Description
Offset	16’h1c4
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock Internal Controller APB

Table 115. Clock Internal Controller APB Register Description
Offset	16’h1c8
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U0 Clock CAN Controller APB

Table 116. U0 Clock CAN Controller APB Register Description
Offset	16’h1cc
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U0 Clock CAN Controller Timer

Table 117. U0 Clock CAN Controller Timer Register Description
Offset	16’h1d0
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d24	Clock divider coefficient: Max: 24 Default: 24 Min: 6 Typical: 24

U0 Clock CAN Controller CAN

Table 118. U0 Clock CAN Controller CAN Register Description
Offset	16’h1d4
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d8	Clock divider coefficient: Max: 63 Default: 8 Min: 8 Typical: 8

U1 Clock CAN Controller APB

Table 119. U1 Clock CAN Controller APB Register Description
Offset	16’h1d8
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U1 Clock CAN Controller Timer

Table 120. U1 Clock CAN Controller Timer Register Description
Offset	16’h1dc
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d24	Clock divider coefficient: Max: 24 Default: 24 Min: 6 Typical: 24

U1 Clock CAN Controller CAN

Table 121. U1 Clock CAN Controller CAN Register Description
Offset	16’h1e0
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d8	Clock divider coefficient: Max: 63 Default: 8 Min: 8 Typical: 8

Clock PWM APB

Table 122. Clock PWM APB Register Description
Offset	16’h1e4
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock WDT APB

Table 123. Clock WDT APB Register Description
Offset	16’h1e8
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock WDT

Table 124. Clock WDT Register Description
Offset	16’h1ec
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock Timer APB

Table 125. Clock Timer APB Register Description
Offset	16’h1f0
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock Timer 0

Table 126. Clock Timer 0 Register Description
Offset	16’h1f4
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock Timer 1

Table 127. Clock Timer 1 Register Description
Offset	16’h1f8
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock Timer 2

Table 128. Clock Timer 2 Register Description
Offset	16’h1fc
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock Timer 3

Table 129. Clock Timer 3 Register Description
Offset	16’h200
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock Temperature Sensor APB

Table 130. Clock Temperature Sensor APB Register Description
Offset	16’h204
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock Temperature Sensor

Table 131. Clock Temperature Sensor Register Description
Offset	16’h208
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d24	Clock divider coefficient: Max: 24 Default: 24 Min: 24 Typical: 24

U0 Clock SPI APB

Table 132. U0 Clock SPI APB Register Description
Offset	16’h20c
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U1 Clock SPI APB

Table 133. U1 Clock SPI APB Register Description
Offset	16’h210
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U2 Clock SPI APB

Table 134. U2 Clock SPI APB Register Description
Offset	16’h214
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U3 Clock SPI APB

Table 135. U3 Clock SPI APB Register Description
Offset	16’h218
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U4 Clock SPI APB

Table 136. U4 Clock SPI APB Register Description
Offset	16’h21c
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U5 Clock SPI APB

Table 137. U5 Clock SPI APB Register Description
Offset	16’h220
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U6 Clock SPI APB

Table 138. U6 Clock SPI APB Register Description
Offset	16’h224
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U0 Clock I2C APB

Table 139. U0 Clock I2C APB Register Description
Offset	16’h228
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U1 Clock I2C APB

Table 140. U1 Clock I2C APB Register Description
Offset	16’h22c
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U2 Clock I2C APB

Table 141. U2 Clock I2C APB Register Description
Offset	16’h230
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U3 Clock I2C APB

Table 142. U3 Clock I2C APB Register Description
Offset	16’h234
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U4 Clock I2C APB

Table 143. U4 Clock I2C APB Register Description
Offset	16’h238
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U5 Clock I2C APB

Table 144. U5 Clock I2C APB Register Description
Offset	16’h23c
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U6 Clock I2C APB

Table 145. U6 Clock I2C APB Register Description
Offset	16’h240
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U0 Clock UART APB

Table 146. U0 Clock UART APB Register Description
Offset	16’h244
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U0 Clock UART Core

Table 147. U0 Clock UART Core Register Description
Offset	16’h248
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	1	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U1 Clock UART APB

Table 148. U1 Clock UART APB Register Description
Offset	16’h24c
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U1 Clock UART Core

Table 149. U1 Clock UART Core Register Description
Offset	16’h250
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U2 Clock UART APB

Table 150. U2 Clock UART APB Register Description
Offset	16’h254
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U2 Clock UART Core

Table 151. U2 Clock UART Core Register Description
Offset	16’h258
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U3 Clock UART APB

Table 152. U3 Clock UART APB Register Description
Offset	16’h25c
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U3 Clock UART Core

Table 153. U3 Clock UART Core Register Description
Offset	16’h260
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d2560	Clock divider coefficient: Max: 131,071 Default: 2,560 Min: 2,560 Typical: 2,560

U4 Clock UART APB

Table 154. U4 Clock UART APB Register Description
Offset	16’h264
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U4 Clock UART Core

Table 155. U4 Clock UART Core Register Description
Offset	16’h268
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d2560	Clock divider coefficient: Max: 131,071 Default: 2,560 Min: 2,560 Typical: 2,560

U5 Clock UART APB

Table 156. U5 Clock UART APB Register Description
Offset	16’h26c
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U5 Clock UART Core

Table 157. U5 Clock UART Core Register Description
Offset	16’h270
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d2560	Clock divider coefficient: Max: 131,071 Default: 2,560 Min: 2,560 Typical: 2,560

Clock PWMDAC APB

Table 158. Clock PWMDAC APB Register Description
Offset	16’h274
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock PWMDAC Core

Table 159. Clock PWMDAC Core Register Description
Offset	16’h278
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d12	Clock divider coefficient: Max: 256 Default: 12 Min: 12 Typical: 12

Clock SPDIF APB

Table 160. Clock SPDIF APB Register Description
Offset	16’h27c
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock SPDIF Core

Table 161. Clock SPDIF Core Register Description
Offset	16’h280
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U0 Clock I2S TX APB

Table 162. U0 Clock I2S TX APB Register Description
Offset	16’h284
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock I2S TX 0 BCLK MST

Table 163. U0 Clock I2S TX 0 BCLK MST Register Description
Offset	16’h288
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d4	Clock divider coefficient: Max: 32 Default: 4 Min: 4 Typical: 4

Clock I2S TX 0 BCLK MST Inverter

Table 164. U0 Clock I2S TX 0 BCLK MST Inverter Register Description
Offset	16’h28c
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	clk_polarity	1	1: Clock inverter 0: Clock buffer
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock I2S TX 0 LRCK MST

Table 165. U0 Clock I2S TX 0 LRCK MST Register Description
Offset	16’h290
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	clk_mux_sel	6’d0	Clock multiplexing selector: clk_i2stx_4ch0_bclk_mst_inv clk_i2stx_4ch0_bclk_mst
[0:23]	clk_divcfg	24’d64	Clock divider coefficient: Max: 64 Default: 64 Min: 64 Typical: 64

U0 Clock I2S TX BCLK

Table 166. U0 Clock I2S TX BCLK Register Description
Offset	16’h294
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	clk_mux_sel	6’d0	Clock multiplexing selector: clk_i2stx_4ch0_bclk_mst clk_i2stx_bclk_ext
[0:23]	Reserved	0	Reserved

U0 Clock I2S TX BCLK Negative

Table 167. U0 Clock I2S TX BCLK Negative Register Description
Offset	16’h298
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	clk_polarity	1	1: Clock inverter 0: Clock buffer
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U0 Clock I2S TX LRCK

Table 168. U0 Clock I2S TX LRCK Register Description
Offset	16’h29c
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	clk_mux_sel	6’d0	Clock multiplexing selector: clk_i2stx_4ch0_lrck_mst clk_i2stx_lrck_ext
[0:23]	Reserved	0	Reserved

U1 Clock I2S TX APB

Table 169. U1 Clock I2S TX APB Register Description
Offset	16’h2a0
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock I2S TX 1 BCLK MST

Table 170. Clock I2S TX 1 BCLK MST Register Description
Offset	16’h2a4
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d4	Clock divider coefficient: Max: 32 Default: 4 Min: 4 Typical: 4

Clock I2S TX 1 BCLK MST Inverter

Table 171. Clock I2S TX 1 BCLK MST Inverter Register Description
Offset	16’h2a8
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	clk_polarity	1	1: Clock inverter 0: Clock buffer
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock I2S TX 1 BCLK MST

Table 172. Clock I2S TX 1 BCLK MST Register Description
Offset	16’h2ac
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	clk_mux_sel	6’d0	Clock multiplexing selector: clk_i2stx_4ch1_bclk_mst_inv clk_i2stx_4ch1_bclk_mst
[0:23]	clk_divcfg	24’d64	Clock divider coefficient: Max: 64 Default: 64 Min: 64 Typical: 64

U1 Clock I2S TX BCLK

Table 173. U1 Clock I2S TX BCLK Register Description
Offset	16’h2b0
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	clk_mux_sel	6’d0	Clock multiplexing selector: clk_i2stx_4ch1_bclk_mst clk_i2stx_bclk_ext
[0:23]	Reserved	0	Reserved

U1 Clock I2S TX BCLK Negative

Table 174. U1 Clock I2S TX BCLK Negative Register Description
Offset	16’h2b4
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	clk_polarity	1	1: Clock inverter 0: Clock buffer
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

U1 Clock I2S TX LRCK

Table 175. U1 Clock I2S TX LRCK Register Description
Offset	16’h2b8
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	clk_mux_sel	6’d0	Clock multiplexing selector: clk_i2stx_4ch1_lrck_mst clk_i2stx_lrck_ext
[0:23]	Reserved	0	Reserved

Clock I2S APB

Table 176. Clock I2S APB Register Description
Offset	16’h2bc
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock I2S BCLK MST

Table 177. Clock I2S BCLK MST Register Description
Offset	16’h2c0
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d4	Clock divider coefficient: Max: 32 Default: 4 Min: 4 Typical: 4

Clock I2S BCLK MST Inverter

Table 178. Clock I2S BCLK MST Inverter Register Description
Offset	16’h2c4
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	clk_polarity	1	1: Clock inverter 0: Clock buffer
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock I2S LRCK MST

Table 179. Clock I2S LRCK MST Register Description
Offset	16’h2c8
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	clk_mux_sel	6’d0	Clock multiplexing selector: clk_i2srx_3ch_bclk_mst_inv clk_i2srx_3ch_bclk_mst
[0:23]	clk_divcfg	24’d64	Clock divider coefficient: Max: 64 Default: 64 Min: 64 Typical: 64

Clock I2S BCLK

Table 180. Clock I2S BCLK Register Description
Offset	16’h2cc
Access	RW
Bit	Name	Default	Description
31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	clk_mux_sel	6’d0	Clock multiplexing selector: clk_i2srx_3ch_bclk_mst clk_i2srx_bclk_ext
[0:23]	Reserved	0	Reserved

Clock I2S BCLK Negative

Table 181. Clock I2S BCLK Negative Register Description
Offset	16’h2d0
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	clk_polarity	1	1: Clock inverter 0: Clock buffer
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock I2S LRCK

Table 182. Clock I2S LRCK Register Description
Offset	16’h2d4
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	clk_mux_sel	6’d0	Clock multiplexing selector: clk_i2srx_3ch_lrck_mst clk_i2srx_lrck_ext
[0:23]	Reserved	0	Reserved

Clock PDM DMIC

Table 183. Clock PDM DMIC Register Description
Offset	16’h2d8
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d8	Clock divider coefficient: Max: 64 Default: 8 Min: 8 Typical: 8

Clock PDM APB

Table 184. Clock PDM APB Register Description
Offset	16’h2dc
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock TDM AHB

Table 185. Clock TDM AHB Register Description
Offset	16’h2e0
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock TDM APB

Table 186. Clock TDM APB Register Description
Offset	16’h2e4
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock TDM Internal

Table 187. Clock TDM Internal Register Description
Offset	16’h2e8
Access	RW
Bit	Name	Default	Description
[31]	clk_icg	0	1: Clock enable 0: Clock disable
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d1	Clock divider coefficient: Max: 64 Default: 1 Min: 1 Typical: 1

Clock TDM

Table 188. Clock TDM Register Description
Offset	16’h2ec
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	clk_mux_sel	6’d0	Clock multiplexing selector: clk_tdm_internal clk_tdm_ext
[0:23]	Reserved	0	Reserved

Clock TDM Negative

Table 189. Clock TDM Negative Register Description
Offset	16’h2f0
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	clk_polarity	1	1: Clock inverter 0: Clock buffer
[24:29]	Reserved	0	Reserved
[0:23]	Reserved	0	Reserved

Clock JTAG Certification TRNG

Table 190. Clock JTAG Certification TRNG Clock Register Description
Offset	16’h2f4
Access	RW
Bit	Name	Default	Description
[31]	Reserved	0	Reserved
[30]	Reserved	0	Reserved
[24:29]	Reserved	0	Reserved
[0:23]	clk_divcfg	24’d4	Clock divider coefficient: Max: 4 Default: 4 Min: 4 Typical: 4

Software RESET 0 Address Selector

Table 191. Software RESET 0 Address Selector Register Description
Offset	16’h2f8
Access	RW
Bit	Name	Default	Description
[0]	rstn_u0_jtag2apb_presetn	0	1: Assert reset 0: De-assert reset
[1]	rstn_u0_sys_syscon_presetn	0	1: Assert reset 0: De-assert reset
[2]	rstn_u0_sys_iomux_presetn	0	1: Assert reset 0: De-assert reset
[3]	rst_u0_u7mc_sft7110_rst_bus	0	1: Assert reset 0: De-assert reset
[4]	rst_u0_u7mc_sft7110_debug_reset	0	1: Assert reset 0: De-assert reset
[5]	rst_u0_u7mc_sft7110_rst_core0	0	1: Assert reset 0: De-assert reset
[6]	rst_u0_u7mc_sft7110_rst_core1	0	1: Assert reset 0: De-assert reset
[7]	rst_u0_u7mc_sft7110_rst_core2	0	1: Assert reset 0: De-assert reset
[8]	rst_u0_u7mc_sft7110_rst_core3	0	1: Assert reset 0: De-assert reset
[9]	rst_u0_u7mc_sft7110_rst_core4	0	1: Assert reset 0: De-assert reset
[10]	rst_u0_u7mc_sft7110_rst_core0_st	0	1: Assert reset 0: De-assert reset
[11]	rst_u0_u7mc_sft7110_rst_core1_st	0	1: Assert reset 0: De-assert reset
[12]	rst_u0_u7mc_sft7110_rst_core2_st	0	1: Assert reset 0: De-assert reset
[13]	rst_u0_u7mc_sft7110_rst_core3_st	0	1: Assert reset 0: De-assert reset
[14]	rst_u0_u7mc_sft7110_rst_core4_st	0	1: Assert reset 0: De-assert reset
[15]	rst_u0_u7mc_sft7110_trace_rst0	0	1: Assert reset 0: De-assert reset
[16]	rst_u0_u7mc_sft7110_trace_rst1	0	1: Assert reset 0: De-assert reset
[17]	rst_u0_u7mc_sft7110_trace_rst2	0	1: Assert reset 0: De-assert reset
[18]	rst_u0_u7mc_sft7110_trace_rst3	0	1: Assert reset 0: De-assert reset
[19]	rst_u0_u7mc_sft7110_trace_rst4	0	1: Assert reset 0: De-assert reset
[20]	rst_u0_u7mc_sft7110_trace_com_rst	0	1: Assert reset 0: De-assert reset
[21]	rstn_u0_img_gpu_rstn_apb	1	1: Assert reset 0: De-assert reset
[22]	rstn_u0_img_gpu_rstn_doma	1	1: Assert reset 0: De-assert reset
[23]	rstn_u0_sft7110_noc_bus_reset_apb_bus_n	0	1: Assert reset 0: De-assert reset
[24]	rstn_u0_sft7110_noc_bus_reset_axicfg0_axi_n	0	1: Assert reset 0: De-assert reset
[25]	rstn_u0_sft7110_noc_bus_reset_cpu_axi_n	0	1: Assert reset 0: De-assert reset
[26]	rstn_u0_sft7110_noc_bus_reset_disp_axi_n	0	1: Assert reset 0: De-assert reset
[27]	rstn_u0_sft7110_noc_bus_reset_gpu_axi_n	0	1: Assert reset 0: De-assert reset
[28]	rstn_u0_sft7110_noc_bus_reset_isp_axi_n	0	1: Assert reset 0: De-assert reset
[29]	rstn_u0_sft7110_noc_bus_reset_ddrc_n	0	1: Assert reset 0: De-assert reset
[30]	rstn_u0_sft7110_noc_bus_reset_stg_axi_n	0	1: Assert reset 0: De-assert reset
[31]	rstn_u0_sft7110_noc_bus_reset_vdec_axi_n	0	1: Assert reset 0: De-assert reset

Software RESET 1 Address Selector

Table 192. Software RESET 1 Address Selector Register Description
Offset	16’h2fc
Access	RW
Bit	Name	Default	Description
[0]	rstn_u0_sft7110_noc_bus_reset_venc_axi_n	0	1: Assert reset 0: De-assert reset
[1]	rstn_u0_axi_cfg1_dec_rstn_ahb	0	1: Assert reset 0: De-assert reset
[2]	rstn_u0_axi_cfg1_dec_rstn_main	0	1: Assert reset 0: De-assert reset
[3]	rstn_u0_axi_cfg0_dec_rstn_main	0	1: Assert reset 0: De-assert reset
[4]	rstn_u0_axi_cfg0_dec_rstn_main_div	0	1: Assert reset 0: De-assert reset
[5]	rstn_u0_axi_cfg0_dec_rstn_hifi4	0	1: Assert reset 0: De-assert reset
[6]	rstn_u0_ddr_sft7110_rstn_axi	0	1: Assert reset 0: De-assert reset
[7]	rstn_u0_ddr_sft7110_rstn_osc	0	1: Assert reset 0: De-assert reset
[8]	rstn_u0_ddr_sft7110_rstn_apb	0	1: Assert reset 0: De-assert reset
[9]	rstn_u0_dom_isp_top_rstn_dom_isp_top_ip_top_reset_n	1	1: Assert reset 0: De-assert reset
[10]	rstn_u0_dom_isp_top_rstn_dom_isp_top_rstn_isp_axi	1	1: Assert reset 0: De-assert reset
[11]	rstn_u0_dom_vout_top_rstn_dom_vout_top_rstn_vout_src	1	1: Assert reset 0: De-assert reset
[12]	rstn_u0_CODAJ12_rstn_axi	1	1: Assert reset 0: De-assert reset
[13]	rstn_u0_CODAJ12_rstn_core	1	1: Assert reset 0: De-assert reset
[14]	rstn_u0_CODAJ12_rstn_apb	1	1: Assert reset 0: De-assert reset
[15]	rstn_u0_WAVE511_rstn_axi	1	1: Assert reset 0: De-assert reset
[16]	rstn_u0_WAVE511_rstn_bpu	1	1: Assert reset 0: De-assert reset
[17]	rstn_u0_WAVE511_rstn_vce	1	1: Assert reset 0: De-assert reset
[18]	rstn_u0_WAVE511_rstn_apb	1	1: Assert reset 0: De-assert reset
[19]	rstn_u0_vdec_jpg_arb_jpgresetn	0	1: Assert reset 0: De-assert reset
[20]	rstn_u0_vdec_jpg_arb_mainresetn	0	1: Assert reset 0: De-assert reset
[21]	rstn_u0_aximem_128b_rstn_axi	1	1: Assert reset 0: De-assert reset
[22]	rstn_u0_wave420l_rstn_axi	1	1: Assert reset 0: De-assert reset
[23]	rstn_u0_wave420l_rstn_bpu	1	1: Assert reset 0: De-assert reset
[24]	rstn_u0_wave420l_rstn_vce	1	1: Assert reset 0: De-assert reset
[25]	rstn_u0_wave420l_rstn_apb	1	1: Assert reset 0: De-assert reset
[26]	rstn_u1_aximem_128b_rstn_axi	1	1: Assert reset 0: De-assert reset
[27]	rstn_u2_aximem_128b_rstn_axi	0	1: Assert reset 0: De-assert reset
[28]	rstn_u0_intmem_rom_sram_rstn_rom	0	1: Assert reset 0: De-assert reset
[29]	rstn_u0_cdns_qspi_rstn_ahb	0	1: Assert reset 0: De-assert reset
[30]	rstn_u0_cdns_qspi_rstn_apb	0	1: Assert reset 0: De-assert reset
[31]	rstn_u0_cdns_qspi_rstn_ref	0	1: Assert reset 0: De-assert reset

Software RESET 2 Address Selector

Table 193. Software RESET 2 Address Selector Register Description
Offset	16’h300
Access	RW
Bit	Name	Default	Description
[0]	rstn_u0_sdio_rstn_ahb	0	1: Assert reset 0: De-assert reset
[1]	rstn_u1_sdio_rstn_ahb	0	1: Assert reset 0: De-assert reset
[2]	rstn_u1_gmac5_axi64_aresetn_i	1	1: Assert reset 0: De-assert reset
[3]	rstn_u1_gmac5_axi64_hreset_n	1	1: Assert reset 0: De-assert reset
[4]	rstn_u0_mailbox_presetn	0	1: Assert reset 0: De-assert reset
[5]	rstn_u0_ssp_spi_rstn_apb	0	1: Assert reset 0: De-assert reset
[6]	rstn_u1_ssp_spi_rstn_apb	1	1: Assert reset 0: De-assert reset
[7]	rstn_u2_ssp_spi_rstn_apb	1	1: Assert reset 0: De-assert reset
[8]	rstn_u3_ssp_spi_rstn_apb	1	1: Assert reset 0: De-assert reset
[9]	rstn_u4_ssp_spi_rstn_apb	1	1: Assert reset 0: De-assert reset
[10]	rstn_u5_ssp_spi_rstn_apb	1	1: Assert reset 0: De-assert reset
[11]	rstn_u6_ssp_spi_rstn_apb	1	1: Assert reset 0: De-assert reset
[12]	rstn_u0_i2c_rstn_apb	0	1: Assert reset 0: De-assert reset
[13]	rstn_u1_i2c_rstn_apb	1	1: Assert reset 0: De-assert reset
[14]	rstn_u2_i2c_rstn_apb	1	1: Assert reset 0: De-assert reset
[15]	rstn_u3_i2c_rstn_apb	1	1: Assert reset 0: De-assert reset
[16]	rstn_u4_i2c_rstn_apb	1	1: Assert reset 0: De-assert reset
[17]	rstn_u5_i2c_rstn_apb	1	1: Assert reset 0: De-assert reset
[18]	rstn_u6_i2c_rstn_apb	1	1: Assert reset 0: De-assert reset
[19]	rstn_u0_uart_rstn_apb	0	1: Assert reset 0: De-assert reset
[20]	rstn_u0_uart_rstn_core	0	1: Assert reset 0: De-assert reset
[21]	rstn_u1_uart_rstn_apb	1	1: Assert reset 0: De-assert reset
[22]	rstn_u1_uart_rstn_core	1	1: Assert reset 0: De-assert reset
[23]	rstn_u2_uart_rstn_apb	1	1: Assert reset 0: De-assert reset
[24]	rstn_u2_uart_rstn_core	1	1: Assert reset 0: De-assert reset
[25]	rstn_u3_uart_rstn_apb	1	1: Assert reset 0: De-assert reset
[26]	rstn_u3_uart_rstn_core	1	1: Assert reset 0: De-assert reset
[27]	rstn_u4_uart_rstn_apb	1	1: Assert reset 0: De-assert reset
[28]	rstn_u4_uart_rstn_core	1	1: Assert reset 0: De-assert reset
[29]	rstn_u5_uart_rstn_apb	1	1: Assert reset 0: De-assert reset
[30]	rstn_u5_uart_rstn_core	1	1: Assert reset 0: De-assert reset
[31]	rstn_u0_cdns_spdif_rstn_apb	1	1: Assert reset 0: De-assert reset

Software RESET 3 Address Selector

Table 194. Software RESET 3 Address Selector Register Description
Offset	16’h304
Access	RW
Bit	Name	Default	Description
[0]	rstn_u0_pwmdac_rstn_apb	1	1: Assert reset 0: De-assert reset
[1]	rstn_u0_pdm_4mic_rstn_dmic	1	1: Assert reset 0: De-assert reset
[2]	rstn_u0_pdm_4mic_rstn_apb	1	1: Assert reset 0: De-assert reset
[3]	rstn_u0_i2srx_3ch_rstn_apb	1	1: Assert reset 0: De-assert reset
[4]	rstn_u0_i2srx_3ch_rstn_bclk	1	1: Assert reset 0: De-assert reset
[5]	rstn_u0_i2stx_4ch_rstn_apb	1	1: Assert reset 0: De-assert reset
[6]	rstn_u0_i2stx_4ch_rstn_bclk	1	1: Assert reset 0: De-assert reset
[7]	rstn_u1_i2stx_4ch_rstn_apb	1	1: Assert reset 0: De-assert reset
[8]	rstn_u1_i2stx_4ch_rstn_bclk	1	1: Assert reset 0: De-assert reset
[9]	rstn_u0_tdm16slot_rstn_ahb	1	1: Assert reset 0: De-assert reset
[10]	rstn_u0_tdm16slot_rstn_tdm	1	1: Assert reset 0: De-assert reset
[11]	rstn_u0_tdm16slot_rstn_apb	1	1: Assert reset 0: De-assert reset
[12]	rstn_u0_pwm_8ch_rstn_apb	1	1: Assert reset 0: De-assert reset
[13]	rstn_u0_dskit_wdt_rstn_apb	1	1: Assert reset 0: De-assert reset
[14]	rstn_u0_dskit_wdt_rstn_wdt	1	1: Assert reset 0: De-assert reset
[15]	rstn_u0_can_ctrl_rstn_apb	1	1: Assert reset 0: De-assert reset
[16]	rstn_u0_can_ctrl_rstn_can	1	1: Assert reset 0: De-assert reset
[17]	rstn_u0_can_ctrl_rstn_timer	1	1: Assert reset 0: De-assert reset
[18]	rstn_u1_can_ctrl_rstn_apb	1	1: Assert reset 0: De-assert reset
[19]	rstn_u1_can_ctrl_rstn_can	1	1: Assert reset 0: De-assert reset
[20]	rstn_u1_can_ctrl_rstn_timer	1	1: Assert reset 0: De-assert reset
[21]	rstn_u0_si5_timer_rstn_apb	1	1: Assert reset 0: De-assert reset
[22]	rstn_u0_si5_timer_rstn_timer0	1	1: Assert reset 0: De-assert reset
[23]	rstn_u0_si5_timer_rstn_timer1	1	1: Assert reset 0: De-assert reset
[24]	rstn_u0_si5_timer_rstn_timer2	1	1: Assert reset 0: De-assert reset
[25]	rstn_u0_si5_timer_rstn_timer3	1	1: Assert reset 0: De-assert reset
[26]	rstn_u0_int_ctrl_rstn_apb	1	1: Assert reset 0: De-assert reset
[27]	rstn_u0_temp_sensor_rstn_apb	1	1: Assert reset 0: De-assert reset
[28]	rstn_u0_temp_sensor_rstn_temp	1	1: Assert reset 0: De-assert reset
[29]	rstn_u0_jtag_certification_rst_n	0	1: Assert reset 0: De-assert reset
[30:31]	Reserved	0	Reserved

SYSCRG RESET Status 0

Table 195. SYSCRG RESET Status 0 Register Description
Offset	16'h308
Access	RW
Bit	Name	Default	Description
[0]	rstn_u0_jtag2apb_presetn	1	1: Assert reset 0: De-assert reset
[1]	rstn_u0_sys_syscon_presetn	0	1: Assert reset 0: De-assert reset
[2]	rstn_u0_sys_iomux_presetn	0	1: Assert reset 0: De-assert reset
[3]	rst_u0_u7mc_sft7110_rst_bus	0	1: Assert reset 0: De-assert reset
[4]	rst_u0_u7mc_sft7110_debug_reset	0	1: Assert reset 0: De-assert reset
[5]	rst_u0_u7mc_sft7110_rst_core0	0	1: Assert reset 0: De-assert reset
[6]	rst_u0_u7mc_sft7110_rst_core1	0	1: Assert reset 0: De-assert reset
[7]	rst_u0_u7mc_sft7110_rst_core2	0	1: Assert reset 0: De-assert reset
[8]	rst_u0_u7mc_sft7110_rst_core3	0	1: Assert reset 0: De-assert reset
[9]	rst_u0_u7mc_sft7110_rst_core4	0	1: Assert reset 0: De-assert reset
[10]	rst_u0_u7mc_sft7110_rst_core0_st	0	1: Assert reset 0: De-assert reset
[11]	rst_u0_u7mc_sft7110_rst_core1_st	0	1: Assert reset 0: De-assert reset
[12]	rst_u0_u7mc_sft7110_rst_core2_st	0	1: Assert reset 0: De-assert reset
[13]	rst_u0_u7mc_sft7110_rst_core3_st	0	1: Assert reset 0: De-assert reset
[14]	rst_u0_u7mc_sft7110_rst_core4_st	0	1: Assert reset 0: De-assert reset
[15]	rst_u0_u7mc_sft7110_trace_rst0	0	1: Assert reset 0: De-assert reset
[16]	rst_u0_u7mc_sft7110_trace_rst1	0	1: Assert reset 0: De-assert reset
[17]	rst_u0_u7mc_sft7110_trace_rst2	0	1: Assert reset 0: De-assert reset
[18]	rst_u0_u7mc_sft7110_trace_rst3	0	1: Assert reset 0: De-assert reset
[19]	rst_u0_u7mc_sft7110_trace_rst4	0	1: Assert reset 0: De-assert reset
[20]	rst_u0_u7mc_sft7110_trace_com_rst	0	1: Assert reset 0: De-assert reset
[21]	rstn_u0_img_gpu_rstn_apb	1	1: Assert reset 0: De-assert reset
[22]	rstn_u0_img_gpu_rstn_doma	1	1: Assert reset 0: De-assert reset
[23]	rstn_u0_sft7110_noc_bus_reset_apb_bus_n	0	1: Assert reset 0: De-assert reset
[24]	rstn_u0_sft7110_noc_bus_reset_axicfg0_axi_n	0	1: Assert reset 0: De-assert reset
[25]	rstn_u0_sft7110_noc_bus_reset_cpu_axi_n	0	1: Assert reset 0: De-assert reset
[26]	rstn_u0_sft7110_noc_bus_reset_disp_axi_n	0	1: Assert reset 0: De-assert reset
[27]	rstn_u0_sft7110_noc_bus_reset_gpu_axi_n	0	1: Assert reset 0: De-assert reset
[28]	rstn_u0_sft7110_noc_bus_reset_isp_axi_n	0	1: Assert reset 0: De-assert reset
[29]	rstn_u0_sft7110_noc_bus_reset_ddrc_n	0	1: Assert reset 0: De-assert reset
[30]	rstn_u0_sft7110_noc_bus_reset_stg_axi_n	0	1: Assert reset 0: De-assert reset
[31]	rstn_u0_sft7110_noc_bus_reset_vdec_axi_n	0	1: Assert reset 0: De-assert reset

SYSCRG RESET Status 1

Table 196. SYSCRG RESET Status 1 Register Description
Offset	16'h30c
Access	RW
Bit	Name	Default	Description
[0]	rstn_u0_sft7110_noc_bus_reset_venc_axi_n	0	1: Assert reset 0: De-assert reset
[1]	rstn_u0_axi_cfg1_dec_rstn_ahb	0	1: Assert reset 0: De-assert reset
[2]	rstn_u0_axi_cfg1_dec_rstn_main	0	1: Assert reset 0: De-assert reset
[3]	rstn_u0_axi_cfg0_dec_rstn_main	0	1: Assert reset 0: De-assert reset
[4]	rstn_u0_axi_cfg0_dec_rstn_main_div	0	1: Assert reset 0: De-assert reset
[5]	rstn_u0_axi_cfg0_dec_rstn_hifi4	0	1: Assert reset 0: De-assert reset
[6]	rstn_u0_ddr_sft7110_rstn_axi	0	1: Assert reset 0: De-assert reset
[7]	rstn_u0_ddr_sft7110_rstn_osc	0	1: Assert reset 0: De-assert reset
[8]	rstn_u0_ddr_sft7110_rstn_apb	0	1: Assert reset 0: De-assert reset
[9]	rstn_u0_dom_isp_top_rstn_dom_isp_top_ip_top_reset_n	1	1: Assert reset 0: De-assert reset
[10]	rstn_u0_dom_isp_top_rstn_dom_isp_top_rstn_isp_axi	1	1: Assert reset 0: De-assert reset
[11]	rstn_u0_dom_vout_top_rstn_dom_vout_top_rstn_vout_src	1	1: Assert reset 0: De-assert reset
[12]	rstn_u0_CODAJ12_rstn_axi	1	1: Assert reset 0: De-assert reset
[13]	rstn_u0_CODAJ12_rstn_core	1	1: Assert reset 0: De-assert reset
[14]	rstn_u0_CODAJ12_rstn_apb	1	1: Assert reset 0: De-assert reset
[15]	rstn_u0_WAVE511_rstn_axi	1	1: Assert reset 0: De-assert reset
[16]	rstn_u0_WAVE511_rstn_bpu	1	1: Assert reset 0: De-assert reset
[17]	rstn_u0_WAVE511_rstn_vce	1	1: Assert reset 0: De-assert reset
[18]	rstn_u0_WAVE511_rstn_apb	1	1: Assert reset 0: De-assert reset
[19]	rstn_u0_vdec_jpg_arb_jpgresetn	0	1: Assert reset 0: De-assert reset
[20]	rstn_u0_vdec_jpg_arb_mainresetn	0	1: Assert reset 0: De-assert reset
[21]	rstn_u0_aximem_128b_rstn_axi	1	1: Assert reset 0: De-assert reset
[22]	rstn_u0_wave420l_rstn_axi	1	1: Assert reset 0: De-assert reset
[23]	rstn_u0_wave420l_rstn_bpu	1	1: Assert reset 0: De-assert reset
[24]	rstn_u0_wave420l_rstn_vce	1	1: Assert reset 0: De-assert reset
[25]	rstn_u0_wave420l_rstn_apb	1	1: Assert reset 0: De-assert reset
[26]	rstn_u1_aximem_128b_rstn_axi	1	1: Assert reset 0: De-assert reset
[27]	rstn_u2_aximem_128b_rstn_axi	0	1: Assert reset 0: De-assert reset
[28]	rstn_u0_intmem_rom_sram_rstn_rom	0	1: Assert reset 0: De-assert reset
[29]	rstn_u0_cdns_qspi_rstn_ahb	0	1: Assert reset 0: De-assert reset
[30]	rstn_u0_cdns_qspi_rstn_apb	0	1: Assert reset 0: De-assert reset
[31]	rstn_u0_cdns_qspi_rstn_ref	0	1: Assert reset 0: De-assert reset

SYSCRG RESET Status 2

Table 197. SYSCRG RESET Status 2 Register Description
Offset	16'h310
Access	RW
Bit	Name	Default	Description
[0]	rstn_u0_sdio_rstn_ahb	0	1: Assert reset 0: De-assert reset
[1]	rstn_u1_sdio_rstn_ahb	0	1: Assert reset 0: De-assert reset
[2]	rstn_u1_gmac5_axi64_aresetn_i	1	1: Assert reset 0: De-assert reset
[3]	rstn_u1_gmac5_axi64_hreset_n	1	1: Assert reset 0: De-assert reset
[4]	rstn_u0_mailbox_presetn	0	1: Assert reset 0: De-assert reset
[5]	rstn_u0_ssp_spi_rstn_apb	0	1: Assert reset 0: De-assert reset
[6]	rstn_u1_ssp_spi_rstn_apb	1	1: Assert reset 0: De-assert reset
[7]	rstn_u2_ssp_spi_rstn_apb	1	1: Assert reset 0: De-assert reset
[8]	rstn_u3_ssp_spi_rstn_apb	1	1: Assert reset 0: De-assert reset
[9]	rstn_u4_ssp_spi_rstn_apb	1	1: Assert reset 0: De-assert reset
[10]	rstn_u5_ssp_spi_rstn_apb	1	1: Assert reset 0: De-assert reset
[11]	rstn_u6_ssp_spi_rstn_apb	1	1: Assert reset 0: De-assert reset
[12]	rstn_u0_i2c_rstn_apb	0	1: Assert reset 0: De-assert reset
[13]	rstn_u1_i2c_rstn_apb	1	1: Assert reset 0: De-assert reset
[14]	rstn_u2_i2c_rstn_apb	1	1: Assert reset 0: De-assert reset
[15]	rstn_u3_i2c_rstn_apb	1	1: Assert reset 0: De-assert reset
[16]	rstn_u4_i2c_rstn_apb	1	1: Assert reset 0: De-assert reset
[17]	rstn_u5_i2c_rstn_apb	1	1: Assert reset 0: De-assert reset
[18]	rstn_u6_i2c_rstn_apb	1	1: Assert reset 0: De-assert reset
[19]	rstn_u0_uart_rstn_apb	0	1: Assert reset 0: De-assert reset
[20]	rstn_u0_uart_rstn_core	0	1: Assert reset 0: De-assert reset
[21]	rstn_u1_uart_rstn_apb	1	1: Assert reset 0: De-assert reset
[22]	rstn_u1_uart_rstn_core	1	1: Assert reset 0: De-assert reset
[23]	rstn_u2_uart_rstn_apb	1	1: Assert reset 0: De-assert reset
[24]	rstn_u2_uart_rstn_core	1	1: Assert reset 0: De-assert reset
[25]	rstn_u3_uart_rstn_apb	1	1: Assert reset 0: De-assert reset
[26]	rstn_u3_uart_rstn_core	1	1: Assert reset 0: De-assert reset
[27]	rstn_u4_uart_rstn_apb	1	1: Assert reset 0: De-assert reset
[28]	rstn_u4_uart_rstn_core	1	1: Assert reset 0: De-assert reset
[29]	rstn_u5_uart_rstn_apb	1	1: Assert reset 0: De-assert reset
[30]	rstn_u5_uart_rstn_core	1	1: Assert reset 0: De-assert reset
[31]	rstn_u0_cdns_spdif_rstn_apb	1	1: Assert reset 0: De-assert reset

SYSCRG RESET Status 3

Table 198. SYSCRG RESET Status 3 Register Description
Offset	16'h314
Access	RW
Bit	Name	Default	Description
[0]	rstn_u0_pwmdac_rstn_apb	1	1: Assert reset 0: De-assert reset
[1]	rstn_u0_pdm_4mic_rstn_dmic	1	1: Assert reset 0: De-assert reset
[2]	rstn_u0_pdm_4mic_rstn_apb	1	1: Assert reset 0: De-assert reset
[3]	rstn_u0_i2srx_3ch_rstn_apb	1	1: Assert reset 0: De-assert reset
[4]	rstn_u0_i2srx_3ch_rstn_bclk	1	1: Assert reset 0: De-assert reset
[5]	rstn_u0_i2stx_4ch_rstn_apb	1	1: Assert reset 0: De-assert reset
[6]	rstn_u0_i2stx_4ch_rstn_bclk	1	1: Assert reset 0: De-assert reset
[7]	rstn_u1_i2stx_4ch_rstn_apb	1	1: Assert reset 0: De-assert reset
[8]	rstn_u1_i2stx_4ch_rstn_bclk	1	1: Assert reset 0: De-assert reset
[9]	rstn_u0_tdm16slot_rstn_ahb	1	1: Assert reset 0: De-assert reset
[10]	rstn_u0_tdm16slot_rstn_tdm	1	1: Assert reset 0: De-assert reset
[11]	rstn_u0_tdm16slot_rstn_apb	1	1: Assert reset 0: De-assert reset
[12]	rstn_u0_pwm_8ch_rstn_apb	1	1: Assert reset 0: De-assert reset
[13]	rstn_u0_dskit_wdt_rstn_apb	1	1: Assert reset 0: De-assert reset
[14]	rstn_u0_dskit_wdt_rstn_wdt	1	1: Assert reset 0: De-assert reset
[15]	rstn_u0_can_ctrl_rstn_apb	1	1: Assert reset 0: De-assert reset
[16]	rstn_u0_can_ctrl_rstn_can	1	1: Assert reset 0: De-assert reset
[17]	rstn_u0_can_ctrl_rstn_timer	1	1: Assert reset 0: De-assert reset
[18]	rstn_u1_can_ctrl_rstn_apb	1	1: Assert reset 0: De-assert reset
[19]	rstn_u1_can_ctrl_rstn_can	1	1: Assert reset 0: De-assert reset
[20]	rstn_u1_can_ctrl_rstn_timer	1	1: Assert reset 0: De-assert reset
[21]	rstn_u0_si5_timer_rstn_apb	1	1: Assert reset 0: De-assert reset
[22]	rstn_u0_si5_timer_rstn_timer0	1	1: Assert reset 0: De-assert reset
[23]	rstn_u0_si5_timer_rstn_timer1	1	1: Assert reset 0: De-assert reset
[24]	rstn_u0_si5_timer_rstn_timer2	1	1: Assert reset 0: De-assert reset
[25]	rstn_u0_si5_timer_rstn_timer3	1	1: Assert reset 0: De-assert reset
[26]	rstn_u0_int_ctrl_rstn_apb	1	1: Assert reset 0: De-assert reset
[27]	rstn_u0_temp_sensor_rstn_apb	1	1: Assert reset 0: De-assert reset
[28]	rstn_u0_temp_sensor_rstn_temp	1	1: Assert reset 0: De-assert reset
[29]	rstn_u0_jtag_certification_rst_n	0	1: Assert reset 0: De-assert reset
[30:31]	reserved	0	reserved